Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268617
Alejandro Suanes, M. Dei, L. Terés, F. Serra-Graells
This paper presents a switched-capacitor Delta-Sigma modulator (ΔΣM) IP block for low-power high-resolution ADCs. The ΔΣM IP proposal does not require any circuit calibration neither internal supply bootstrapping. A complete design methodology from architecture to circuit levels with specific optimization of the overall power consumption is included. The presented ΔΣM IP block features a remarkable robustness against both process and temperature variations. For illustrative purposes, two 16-bit 50-kHz IP mapping examples in 1.8-V 180-nm and 1.2-V 65-nm mixed-signal CMOS technologies are presented with post-layout simulation results showing FOMS values around 177 dB.
本文介绍了一种用于低功耗高分辨率adc的开关电容Delta-Sigma调制器(ΔΣM) IP块。ΔΣM IP提案不需要任何电路校准，也不需要内部电源启动。一个完整的设计方法，从架构到电路水平与整体功耗的具体优化包括在内。所提出的ΔΣM IP块具有对工艺和温度变化的显著鲁棒性。为了说明问题，本文给出了两个采用1.8 v 180 nm和1.2 v 65 nm混合信号CMOS技术的16位50 khz IP映射示例，其布局后仿真结果显示FOMS值约为177 dB。
{"title":"A 16bit 50kHz 177dB-FOMS Calibration-Free Bootstrapping-Free SC Delta-Sigma Modulator IP Block for Low-Power High-Resolution ADCs","authors":"Alejandro Suanes, M. Dei, L. Terés, F. Serra-Graells","doi":"10.1109/DCIS51330.2020.9268617","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268617","url":null,"abstract":"This paper presents a switched-capacitor Delta-Sigma modulator (ΔΣM) IP block for low-power high-resolution ADCs. The ΔΣM IP proposal does not require any circuit calibration neither internal supply bootstrapping. A complete design methodology from architecture to circuit levels with specific optimization of the overall power consumption is included. The presented ΔΣM IP block features a remarkable robustness against both process and temperature variations. For illustrative purposes, two 16-bit 50-kHz IP mapping examples in 1.8-V 180-nm and 1.2-V 65-nm mixed-signal CMOS technologies are presented with post-layout simulation results showing FOMS values around 177 dB.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124805745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268630
Santiago Rodrigo, S. Abadal, E. Alarcón, C. G. Almudever
Being a very promising technology, with impressive advances in the recent years, it is still unclear how quantum computing will scale to satisfy the requirements of its most powerful applications. Although continued progress in the fabrication and control of qubits is required, quantum computing scalability will depend as well on a comprehensive architectural design considering a distributed multi-core approach as an alternative to the traditional monolithic version, hence including a communications perspective. However, this goes beyond introducing mere interconnects. Rather, it implies consolidating the full communications stack in the quantum computer structure. In this paper, we propose a double full-stack architecture encompassing quantum computation and quantum communications, which we use to address the monolithic versus distributed question with a structured design methodology. For that, we revisit the different quantum computing layers to capture and model their essence by highlighting the open design variables and performance metrics. Using behavioral models and actual measurements from existing quantum computers, the results of simulations suggest that multicore architectures may effectively unleash the full quantum computer potential.
{"title":"Will Quantum Computers Scale Without Inter-Chip Comms? A Structured Design Exploration to the Monolithic vs Distributed Architectures Quest","authors":"Santiago Rodrigo, S. Abadal, E. Alarcón, C. G. Almudever","doi":"10.1109/DCIS51330.2020.9268630","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268630","url":null,"abstract":"Being a very promising technology, with impressive advances in the recent years, it is still unclear how quantum computing will scale to satisfy the requirements of its most powerful applications. Although continued progress in the fabrication and control of qubits is required, quantum computing scalability will depend as well on a comprehensive architectural design considering a distributed multi-core approach as an alternative to the traditional monolithic version, hence including a communications perspective. However, this goes beyond introducing mere interconnects. Rather, it implies consolidating the full communications stack in the quantum computer structure. In this paper, we propose a double full-stack architecture encompassing quantum computation and quantum communications, which we use to address the monolithic versus distributed question with a structured design methodology. For that, we revisit the different quantum computing layers to capture and model their essence by highlighting the open design variables and performance metrics. Using behavioral models and actual measurements from existing quantum computers, the results of simulations suggest that multicore architectures may effectively unleash the full quantum computer potential.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116593825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268672
P. Pérez, A. Yúfera, J. A. Serrano, G. Huertas
This work presents a procedure to improve biomedical sensor design flow by including information taken from sensor technical specifications and data from its biomedical dynamics, in our case, the system described is sensing cell culture assays. The main structural components of a biosensor for cell culture with real-time monitoring are analyzed, modelled and incorporated into the system design flow in such a way that the resulting sensor designed by the procedure will engender analysis of the circuits’ constraints and cell sensitivity, together with the dynamics imposed by the living cells. The time evolution for general cell cultures is reproduced, and an image processing approach is applied to transduce the cell increments to the cell-electrode parameters as previously defined. The proposed tool is applied to the Electrical Cell-Substrate Sensing (ECIS) technique for cell culture test using herein the Oscillation Based Test (OBT) as a bioimpedance testing method. Other bioimpedance test techniques could be directly implemented into the proposed tool to profit similar results. The aforementioned tool, that fully models a cell-culture assay, was experimentally tested using the AA8 cell line, and the results presented in this paper validating the tool predictions.
{"title":"Designing bioimpedance based sensors for cell cultures test","authors":"P. Pérez, A. Yúfera, J. A. Serrano, G. Huertas","doi":"10.1109/DCIS51330.2020.9268672","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268672","url":null,"abstract":"This work presents a procedure to improve biomedical sensor design flow by including information taken from sensor technical specifications and data from its biomedical dynamics, in our case, the system described is sensing cell culture assays. The main structural components of a biosensor for cell culture with real-time monitoring are analyzed, modelled and incorporated into the system design flow in such a way that the resulting sensor designed by the procedure will engender analysis of the circuits’ constraints and cell sensitivity, together with the dynamics imposed by the living cells. The time evolution for general cell cultures is reproduced, and an image processing approach is applied to transduce the cell increments to the cell-electrode parameters as previously defined. The proposed tool is applied to the Electrical Cell-Substrate Sensing (ECIS) technique for cell culture test using herein the Oscillation Based Test (OBT) as a bioimpedance testing method. Other bioimpedance test techniques could be directly implemented into the proposed tool to profit similar results. The aforementioned tool, that fully models a cell-culture assay, was experimentally tested using the AA8 cell line, and the results presented in this paper validating the tool predictions.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132693608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268647
Eros Camacho-Ruiz, M. Martínez-Rodríguez, S. Sánchez-Solano, Piedad Brox Jiménez
The advent of quantum computers represents a serious threat to current public key cryptosystems. To face this problem the so-called Post-Quantum (PQ) cryptographic solutions are being developed, many of which have been presented to the competition launched by NIST to evaluate proposals of PQ cryptography for standardization and deployment. This paper addresses the implementation of the NTRU PQ cryptographic algorithm on embedded systems. Using a Python-based development framework to accelerate the design process, software-only and hybrid (HW/SW) implementations of NTRU are evaluated in terms of operation speed and resource consumption on a System-on-Chip (SoC). Results show that hardware implementation of critical operations in conjuction with a Python+C programming allows an increase in performance that ranges from 130 to 450 depending on the selected scenario to use the algorithm.
{"title":"Accelerating the Development of NTRU Algorithm on Embedded Systems","authors":"Eros Camacho-Ruiz, M. Martínez-Rodríguez, S. Sánchez-Solano, Piedad Brox Jiménez","doi":"10.1109/DCIS51330.2020.9268647","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268647","url":null,"abstract":"The advent of quantum computers represents a serious threat to current public key cryptosystems. To face this problem the so-called Post-Quantum (PQ) cryptographic solutions are being developed, many of which have been presented to the competition launched by NIST to evaluate proposals of PQ cryptography for standardization and deployment. This paper addresses the implementation of the NTRU PQ cryptographic algorithm on embedded systems. Using a Python-based development framework to accelerate the design process, software-only and hybrid (HW/SW) implementations of NTRU are evaluated in terms of operation speed and resource consumption on a System-on-Chip (SoC). Results show that hardware implementation of critical operations in conjuction with a Python+C programming allows an increase in performance that ranges from 130 to 450 depending on the selected scenario to use the algorithm.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"305 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132346570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268627
Kebria Naderi, Erwin H. T. Shad, M. Molinas, A. Heidari, T. Ytterdal
Although current-reuse amplifier has been widely used in biomedical applications because of their low input-referred thermal noise, they don’t have high output swing and their gain is limited. In this article, a rail-to-rail current-reuse amplifier with a 92 dB open-loop gain is introduced while its power and noise increment is just 7%. The proposed structure is a two stage amplifier which doesn’t need further compensation since all nodes are diode connected except for the output node. In order to show the merit of the proposed structure, the NEF, PEF and SEF of the proposed amplifier in a capacitively-coupled neural amplifier structure is compared to the state-of-the-art neural amplifiers. The amplifier is designed and simulated in a commercially available 0.18 µm CMOS technology. The midband gain of the neural amplifier is 40 dB in the bandwidth between 0.6 Hz and 5 kHz. The proposed structure consumes 1.07 µA current from a 1.2 V supply voltage. The NEF, PEF and SEF of proposed structure are 1.68, 3.4, 0.05, respectively. The total area consumption of the neural amplifier is 0.03 mm2 without pads.
{"title":"A Very Low SEF Neural Amplifier by Utilizing a High Swing Current-Reuse Amplifier","authors":"Kebria Naderi, Erwin H. T. Shad, M. Molinas, A. Heidari, T. Ytterdal","doi":"10.1109/DCIS51330.2020.9268627","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268627","url":null,"abstract":"Although current-reuse amplifier has been widely used in biomedical applications because of their low input-referred thermal noise, they don’t have high output swing and their gain is limited. In this article, a rail-to-rail current-reuse amplifier with a 92 dB open-loop gain is introduced while its power and noise increment is just 7%. The proposed structure is a two stage amplifier which doesn’t need further compensation since all nodes are diode connected except for the output node. In order to show the merit of the proposed structure, the NEF, PEF and SEF of the proposed amplifier in a capacitively-coupled neural amplifier structure is compared to the state-of-the-art neural amplifiers. The amplifier is designed and simulated in a commercially available 0.18 µm CMOS technology. The midband gain of the neural amplifier is 40 dB in the bandwidth between 0.6 Hz and 5 kHz. The proposed structure consumes 1.07 µA current from a 1.2 V supply voltage. The NEF, PEF and SEF of proposed structure are 1.68, 3.4, 0.05, respectively. The total area consumption of the neural amplifier is 0.03 mm2 without pads.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133407717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268649
Jaime Sancho, Gemma Urbanos, Luisa Ruiz, Marta Villanueva, Gonzalo Rosa, A. Diaz, M. Villa, M. Chavarrías, Alfonso Lagares, R. Salvador, E. Juárez, C. Sanz
HyperSpectral (HS) images are commonly used for classification tasks in different domains, such as medicine. In this field, a recent use is the differentiation between healthy tissues and different types of cancerous tissues. To this end, different machine learning techniques have been proposed to generate classification maps that indicate the type of tissue corresponding to each pixel in the image. These 2D representations can be used stand-alone, but they can not be properly registered with other valuable data sources like Magnetic Resonance Imaging (MRI), which can improve the accuracy of the system. For this reason, this paper builds the foundations of a multi-modal classification system that will incorporate 3D information into HS images. Specifically, we address the acceleration of one of the hotspots in depth estimation tools/algorithms.MPEG-I Depth Estimation Reference Software (DERS) provides high-quality depth maps relying on a global energy optimizer algorithm: Graph Cuts. However, this algorithm needs huge processing times, preventing its use during surgical operations. This work introduces GoRG (Graph cuts Reference depth estimation in GPU), a GPU accelerated DERS able to produce depth maps from RGB and HS images. In this paper, due to the lack of HS multi-view datasets at the moment, results are reported on RGB images to validate the acceleration strategy.GoRG shows a ×25 average speed-up compared to baseline DERS 8.0, reducing total computation time from around one hour for 8 frames to only a few minutes. A consequence of our parallelization is an average decrease of 1.6 dB in Weighted-to-Spherically-Uniform Peak-Signal-to-Noise-Ratio (WS-PSNR), with some remarkable disparities approaching 4 dB. However, using Structural Similarity Index (SSIM) as metric results come closer to baseline DERS. Effectively, an average decrease of only 1.20% is achieved showing that the obtained speed-up gains compesate the subjective quality losses.
{"title":"Towards GPU Accelerated HyperSpectral Depth Estimation in Medical Applications","authors":"Jaime Sancho, Gemma Urbanos, Luisa Ruiz, Marta Villanueva, Gonzalo Rosa, A. Diaz, M. Villa, M. Chavarrías, Alfonso Lagares, R. Salvador, E. Juárez, C. Sanz","doi":"10.1109/DCIS51330.2020.9268649","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268649","url":null,"abstract":"HyperSpectral (HS) images are commonly used for classification tasks in different domains, such as medicine. In this field, a recent use is the differentiation between healthy tissues and different types of cancerous tissues. To this end, different machine learning techniques have been proposed to generate classification maps that indicate the type of tissue corresponding to each pixel in the image. These 2D representations can be used stand-alone, but they can not be properly registered with other valuable data sources like Magnetic Resonance Imaging (MRI), which can improve the accuracy of the system. For this reason, this paper builds the foundations of a multi-modal classification system that will incorporate 3D information into HS images. Specifically, we address the acceleration of one of the hotspots in depth estimation tools/algorithms.MPEG-I Depth Estimation Reference Software (DERS) provides high-quality depth maps relying on a global energy optimizer algorithm: Graph Cuts. However, this algorithm needs huge processing times, preventing its use during surgical operations. This work introduces GoRG (Graph cuts Reference depth estimation in GPU), a GPU accelerated DERS able to produce depth maps from RGB and HS images. In this paper, due to the lack of HS multi-view datasets at the moment, results are reported on RGB images to validate the acceleration strategy.GoRG shows a ×25 average speed-up compared to baseline DERS 8.0, reducing total computation time from around one hour for 8 frames to only a few minutes. A consequence of our parallelization is an average decrease of 1.6 dB in Weighted-to-Spherically-Uniform Peak-Signal-to-Noise-Ratio (WS-PSNR), with some remarkable disparities approaching 4 dB. However, using Structural Similarity Index (SSIM) as metric results come closer to baseline DERS. Effectively, an average decrease of only 1.20% is achieved showing that the obtained speed-up gains compesate the subjective quality losses.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133058546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268624
Diego Golpe Molinos, H. Solar, A. Beriain, R. Berenguer
Due to the limited power that can be obtained from the RF field, UHF RFID systems need to be able to operate with few dozens of µW. Therefore, an efficient voltage multiplier is a key element to obtain tags able to operate at long ranges and with advanced functionalities. The objective of this work, is obtaining a topology able to provide the required operative voltage with the minimum RF input power. The highest possible sensitivity and efficiency will provide the longest range, which is a critical parameter in UHF RFID applications. Factors such as transistor and diode size and number of stages have been analyzed in order to obtain the maximum sensitivity and power conversion efficiency (PCE). In this paper, four voltage multipliers are developed and analysed, following the same methodology using a 180µm process. Sensitivities as high as -12dBm and PCEs up to 16% with a load of 7µA are obtained in the Schottky multiplier, during simulation of an input power range from - 15dBm to -8dBm.
{"title":"Voltage Multiplier Topologies Comparison for UHF RFID Applications","authors":"Diego Golpe Molinos, H. Solar, A. Beriain, R. Berenguer","doi":"10.1109/DCIS51330.2020.9268624","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268624","url":null,"abstract":"Due to the limited power that can be obtained from the RF field, UHF RFID systems need to be able to operate with few dozens of µW. Therefore, an efficient voltage multiplier is a key element to obtain tags able to operate at long ranges and with advanced functionalities. The objective of this work, is obtaining a topology able to provide the required operative voltage with the minimum RF input power. The highest possible sensitivity and efficiency will provide the longest range, which is a critical parameter in UHF RFID applications. Factors such as transistor and diode size and number of stages have been analyzed in order to obtain the maximum sensitivity and power conversion efficiency (PCE). In this paper, four voltage multipliers are developed and analysed, following the same methodology using a 180µm process. Sensitivities as high as -12dBm and PCEs up to 16% with a load of 7µA are obtained in the Schottky multiplier, during simulation of an input power range from - 15dBm to -8dBm.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133067363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268655
J. Ahmadi-Farsani, B. Linares-Barranco, T. Serrano-Gotarredona
This paper presents a current attenuator fabricated in a CMOS 180nm technology, which works based on a CMOS ladder scheme. The attenuation factor is 104.14 dB, while it shows a non-linearity feature of less than 1.8 %. The circuit occupies an area of 2448 µm2. Since the output current could be as low as tens of femtoamperes, an on-chip testing circuit is also proposed to make the lab-measurements as accurate as possible. The final results show that chip-measurements are following simulations. As a demonstrator, the current attenuator is internally connected to a compact CMOS neuron cell. The output membrane potential shows that the neuron is generating a real-time firing modality, and consequently approves that the current-attenuator is working robustly.
{"title":"A Current-Attenuator for Performing Read Operation in Memristor-Based Spiking Neural Networks","authors":"J. Ahmadi-Farsani, B. Linares-Barranco, T. Serrano-Gotarredona","doi":"10.1109/DCIS51330.2020.9268655","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268655","url":null,"abstract":"This paper presents a current attenuator fabricated in a CMOS 180nm technology, which works based on a CMOS ladder scheme. The attenuation factor is 104.14 dB, while it shows a non-linearity feature of less than 1.8 %. The circuit occupies an area of 2448 µm2. Since the output current could be as low as tens of femtoamperes, an on-chip testing circuit is also proposed to make the lab-measurements as accurate as possible. The final results show that chip-measurements are following simulations. As a demonstrator, the current attenuator is internally connected to a compact CMOS neuron cell. The output membrane potential shows that the neuron is generating a real-time firing modality, and consequently approves that the current-attenuator is working robustly.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114656347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268618
Jafar Shamsi, M. Avedillo, B. Linares-Barranco, T. Serrano-Gotarredona
Hebbian rule plays an important role in training of artificial neural networks. According to this rule, a synaptic weight between two neurons is increased or decreased depending on the activity of the presynaptic and postsynaptic neurons. In this paper, an oscillatory version of the Hebbian rule is proposed for ONNs and is called Oscillatory Hebbian Rule (OHR). OHR simply expresses the weight change as a function of the phase difference between the presynaptic and postsynaptic neurons. Similar to STDP that weight change is an exponential function of the time difference between the presynaptic and postsynaptic spikes, OHR relates weight change to the phase difference between the presynaptic and postsynaptic neurons using exponential functions. Specifically, when two neurons are in-phase, the weight between them is increased while a weight between two anti-phase neurons is decreased. Simulation results show the capability of OHR for both supervised and unsupervised learning. In supervised learning, a basic block of feedforward architectures is trained as a classifier. When the basic block is used in unsupervised mode, it is capable to learn patterns while the output phase is converged to a specific phase.
{"title":"Oscillatory Hebbian Rule (OHR): An adaption of the Hebbian rule to Oscillatory Neural Networks","authors":"Jafar Shamsi, M. Avedillo, B. Linares-Barranco, T. Serrano-Gotarredona","doi":"10.1109/DCIS51330.2020.9268618","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268618","url":null,"abstract":"Hebbian rule plays an important role in training of artificial neural networks. According to this rule, a synaptic weight between two neurons is increased or decreased depending on the activity of the presynaptic and postsynaptic neurons. In this paper, an oscillatory version of the Hebbian rule is proposed for ONNs and is called Oscillatory Hebbian Rule (OHR). OHR simply expresses the weight change as a function of the phase difference between the presynaptic and postsynaptic neurons. Similar to STDP that weight change is an exponential function of the time difference between the presynaptic and postsynaptic spikes, OHR relates weight change to the phase difference between the presynaptic and postsynaptic neurons using exponential functions. Specifically, when two neurons are in-phase, the weight between them is increased while a weight between two anti-phase neurons is decreased. Simulation results show the capability of OHR for both supervised and unsupervised learning. In supervised learning, a basic block of feedforward architectures is trained as a classifier. When the basic block is used in unsupervised mode, it is capable to learn patterns while the output phase is converged to a specific phase.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131877010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268623
Leidy Mabel Alvero-Gonzalez, Luis Hernandez Corporales, Eric Gutierrez
Highly dependence of the power consumption with respect to the voltage supply makes current finer CMOS technologies become supplied with lower-than-1 V. Voltage-controlled-oscillator based analog-to-digital converters implemented with ring-oscillators scales properly with that requirement. However, conventional implementations of ring-oscillators limit the oscillation frequency due to the lack of available voltage to feed high currents. In this manuscript, we propose a novel circuit for a ring-oscillator that overcomes this issue. With only two devices between the supply nodes a delay cell is built. This allows us to reduce the voltage supply for certain oscillation requirements. In addition, the lower number of devices connected to the output nodes supposes lower parasitic capacitance and a reduction in the minimum achievable time delay, which increases the potential resolution. The proposed circuit is theoretically described and validated by simulation in a 65-nm CMOS process. Comparisons to the conventional implementations are made, showing improvements in terms of resolution, power, and area.
{"title":"High-Speed and Energy-Efficient Ring-Oscillator for Analog-to-Digital Conversion","authors":"Leidy Mabel Alvero-Gonzalez, Luis Hernandez Corporales, Eric Gutierrez","doi":"10.1109/DCIS51330.2020.9268623","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268623","url":null,"abstract":"Highly dependence of the power consumption with respect to the voltage supply makes current finer CMOS technologies become supplied with lower-than-1 V. Voltage-controlled-oscillator based analog-to-digital converters implemented with ring-oscillators scales properly with that requirement. However, conventional implementations of ring-oscillators limit the oscillation frequency due to the lack of available voltage to feed high currents. In this manuscript, we propose a novel circuit for a ring-oscillator that overcomes this issue. With only two devices between the supply nodes a delay cell is built. This allows us to reduce the voltage supply for certain oscillation requirements. In addition, the lower number of devices connected to the output nodes supposes lower parasitic capacitance and a reduction in the minimum achievable time delay, which increases the potential resolution. The proposed circuit is theoretically described and validated by simulation in a 65-nm CMOS process. Comparisons to the conventional implementations are made, showing improvements in terms of resolution, power, and area.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133761858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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