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2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)最新文献

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A 16bit 50kHz 177dB-FOMS Calibration-Free Bootstrapping-Free SC Delta-Sigma Modulator IP Block for Low-Power High-Resolution ADCs 用于低功耗高分辨率adc的16位50kHz 177dB-FOMS无校准无启动SC δ - sigma调制器IP块
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268617
Alejandro Suanes, M. Dei, L. Terés, F. Serra-Graells
This paper presents a switched-capacitor Delta-Sigma modulator (ΔΣM) IP block for low-power high-resolution ADCs. The ΔΣM IP proposal does not require any circuit calibration neither internal supply bootstrapping. A complete design methodology from architecture to circuit levels with specific optimization of the overall power consumption is included. The presented ΔΣM IP block features a remarkable robustness against both process and temperature variations. For illustrative purposes, two 16-bit 50-kHz IP mapping examples in 1.8-V 180-nm and 1.2-V 65-nm mixed-signal CMOS technologies are presented with post-layout simulation results showing FOMS values around 177 dB.
本文介绍了一种用于低功耗高分辨率adc的开关电容Delta-Sigma调制器(ΔΣM) IP块。ΔΣM IP提案不需要任何电路校准,也不需要内部电源启动。一个完整的设计方法,从架构到电路水平与整体功耗的具体优化包括在内。所提出的ΔΣM IP块具有对工艺和温度变化的显著鲁棒性。为了说明问题,本文给出了两个采用1.8 v 180 nm和1.2 v 65 nm混合信号CMOS技术的16位50 khz IP映射示例,其布局后仿真结果显示FOMS值约为177 dB。
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引用次数: 1
Will Quantum Computers Scale Without Inter-Chip Comms? A Structured Design Exploration to the Monolithic vs Distributed Architectures Quest 没有芯片间通信,量子计算机能扩展吗?对单片与分布式架构探索的结构化设计
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268630
Santiago Rodrigo, S. Abadal, E. Alarcón, C. G. Almudever
Being a very promising technology, with impressive advances in the recent years, it is still unclear how quantum computing will scale to satisfy the requirements of its most powerful applications. Although continued progress in the fabrication and control of qubits is required, quantum computing scalability will depend as well on a comprehensive architectural design considering a distributed multi-core approach as an alternative to the traditional monolithic version, hence including a communications perspective. However, this goes beyond introducing mere interconnects. Rather, it implies consolidating the full communications stack in the quantum computer structure. In this paper, we propose a double full-stack architecture encompassing quantum computation and quantum communications, which we use to address the monolithic versus distributed question with a structured design methodology. For that, we revisit the different quantum computing layers to capture and model their essence by highlighting the open design variables and performance metrics. Using behavioral models and actual measurements from existing quantum computers, the results of simulations suggest that multicore architectures may effectively unleash the full quantum computer potential.
作为一项非常有前途的技术,近年来取得了令人印象深刻的进步,量子计算将如何扩展以满足其最强大应用的要求仍不清楚。虽然需要在量子比特的制造和控制方面继续取得进展,但量子计算的可扩展性也将取决于考虑分布式多核方法作为传统单片版本的替代方案的综合架构设计,因此包括通信角度。然而,这不仅仅是引入互连。相反,它意味着在量子计算机结构中整合完整的通信堆栈。在本文中,我们提出了一个包含量子计算和量子通信的双全栈架构,我们使用结构化设计方法来解决单片与分布式的问题。为此,我们重新审视不同的量子计算层,通过突出开放的设计变量和性能指标来捕捉和建模它们的本质。利用行为模型和现有量子计算机的实际测量,模拟结果表明,多核架构可以有效地释放量子计算机的全部潜力。
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引用次数: 6
Designing bioimpedance based sensors for cell cultures test 设计基于生物阻抗的细胞培养测试传感器
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268672
P. Pérez, A. Yúfera, J. A. Serrano, G. Huertas
This work presents a procedure to improve biomedical sensor design flow by including information taken from sensor technical specifications and data from its biomedical dynamics, in our case, the system described is sensing cell culture assays. The main structural components of a biosensor for cell culture with real-time monitoring are analyzed, modelled and incorporated into the system design flow in such a way that the resulting sensor designed by the procedure will engender analysis of the circuits’ constraints and cell sensitivity, together with the dynamics imposed by the living cells. The time evolution for general cell cultures is reproduced, and an image processing approach is applied to transduce the cell increments to the cell-electrode parameters as previously defined. The proposed tool is applied to the Electrical Cell-Substrate Sensing (ECIS) technique for cell culture test using herein the Oscillation Based Test (OBT) as a bioimpedance testing method. Other bioimpedance test techniques could be directly implemented into the proposed tool to profit similar results. The aforementioned tool, that fully models a cell-culture assay, was experimentally tested using the AA8 cell line, and the results presented in this paper validating the tool predictions.
这项工作提出了一个改进生物医学传感器设计流程的程序,包括从传感器技术规范中获取的信息和从生物医学动力学中获取的数据,在我们的案例中,所描述的系统是传感细胞培养分析。对用于实时监测细胞培养的生物传感器的主要结构组件进行分析、建模,并将其纳入系统设计流程中,从而使程序设计的最终传感器能够分析电路的约束和细胞灵敏度,以及活细胞施加的动力学。一般细胞培养的时间进化被复制,并应用图像处理方法将细胞增量转导到先前定义的细胞-电极参数。所提出的工具应用于细胞培养测试的电细胞-基质传感(ECIS)技术,使用基于振荡的测试(OBT)作为生物阻抗测试方法。其他生物阻抗测试技术可以直接应用到所提出的工具中,以获得类似的结果。上述工具完全模拟了细胞培养试验,并使用AA8细胞系进行了实验测试,本文中的结果验证了工具的预测。
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引用次数: 0
Accelerating the Development of NTRU Algorithm on Embedded Systems 加快嵌入式系统NTRU算法的发展
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268647
Eros Camacho-Ruiz, M. Martínez-Rodríguez, S. Sánchez-Solano, Piedad Brox Jiménez
The advent of quantum computers represents a serious threat to current public key cryptosystems. To face this problem the so-called Post-Quantum (PQ) cryptographic solutions are being developed, many of which have been presented to the competition launched by NIST to evaluate proposals of PQ cryptography for standardization and deployment. This paper addresses the implementation of the NTRU PQ cryptographic algorithm on embedded systems. Using a Python-based development framework to accelerate the design process, software-only and hybrid (HW/SW) implementations of NTRU are evaluated in terms of operation speed and resource consumption on a System-on-Chip (SoC). Results show that hardware implementation of critical operations in conjuction with a Python+C programming allows an increase in performance that ranges from 130 to 450 depending on the selected scenario to use the algorithm.
量子计算机的出现对当前的公钥密码系统构成了严重威胁。为了解决这个问题,人们正在开发所谓的后量子(PQ)加密解决方案,其中许多解决方案已提交给NIST发起的竞赛,以评估PQ加密的标准化和部署建议。本文讨论了NTRU PQ密码算法在嵌入式系统上的实现。使用基于python的开发框架来加速设计过程,NTRU的纯软件和混合(HW/SW)实现在芯片系统(SoC)上的运行速度和资源消耗方面进行了评估。结果表明,关键操作的硬件实现与Python+C编程相结合,可以使性能提高130到450不等,具体取决于所选择的使用算法的场景。
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引用次数: 2
A Very Low SEF Neural Amplifier by Utilizing a High Swing Current-Reuse Amplifier 利用高摆幅电流复用放大器的极低SEF神经放大器
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268627
Kebria Naderi, Erwin H. T. Shad, M. Molinas, A. Heidari, T. Ytterdal
Although current-reuse amplifier has been widely used in biomedical applications because of their low input-referred thermal noise, they don’t have high output swing and their gain is limited. In this article, a rail-to-rail current-reuse amplifier with a 92 dB open-loop gain is introduced while its power and noise increment is just 7%. The proposed structure is a two stage amplifier which doesn’t need further compensation since all nodes are diode connected except for the output node. In order to show the merit of the proposed structure, the NEF, PEF and SEF of the proposed amplifier in a capacitively-coupled neural amplifier structure is compared to the state-of-the-art neural amplifiers. The amplifier is designed and simulated in a commercially available 0.18 µm CMOS technology. The midband gain of the neural amplifier is 40 dB in the bandwidth between 0.6 Hz and 5 kHz. The proposed structure consumes 1.07 µA current from a 1.2 V supply voltage. The NEF, PEF and SEF of proposed structure are 1.68, 3.4, 0.05, respectively. The total area consumption of the neural amplifier is 0.03 mm2 without pads.
电流复用放大器由于其低输入参考热噪声而被广泛应用于生物医学领域,但其输出摆幅不高且增益有限。本文介绍了一种开环增益为92 dB的轨对轨电流复用放大器,其功率和噪声增量仅为7%。所提出的结构是一个两级放大器,不需要进一步的补偿,因为所有节点都是二极管连接,除了输出节点。为了显示所提出的结构的优点,在电容耦合神经放大器结构中,所提出的放大器的NEF, PEF和SEF与最先进的神经放大器进行了比较。该放大器采用市售的0.18µm CMOS技术进行设计和仿真。神经放大器的中频增益在0.6 Hz和5 kHz之间的带宽为40 dB。该结构在1.2 V电源电压下消耗1.07µA电流。该结构的NEF、PEF和SEF分别为1.68、3.4和0.05。神经放大器的总面积消耗为0.03 mm2,不含衬垫。
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引用次数: 5
Towards GPU Accelerated HyperSpectral Depth Estimation in Medical Applications GPU加速高光谱深度估计在医学中的应用
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268649
Jaime Sancho, Gemma Urbanos, Luisa Ruiz, Marta Villanueva, Gonzalo Rosa, A. Diaz, M. Villa, M. Chavarrías, Alfonso Lagares, R. Salvador, E. Juárez, C. Sanz
HyperSpectral (HS) images are commonly used for classification tasks in different domains, such as medicine. In this field, a recent use is the differentiation between healthy tissues and different types of cancerous tissues. To this end, different machine learning techniques have been proposed to generate classification maps that indicate the type of tissue corresponding to each pixel in the image. These 2D representations can be used stand-alone, but they can not be properly registered with other valuable data sources like Magnetic Resonance Imaging (MRI), which can improve the accuracy of the system. For this reason, this paper builds the foundations of a multi-modal classification system that will incorporate 3D information into HS images. Specifically, we address the acceleration of one of the hotspots in depth estimation tools/algorithms.MPEG-I Depth Estimation Reference Software (DERS) provides high-quality depth maps relying on a global energy optimizer algorithm: Graph Cuts. However, this algorithm needs huge processing times, preventing its use during surgical operations. This work introduces GoRG (Graph cuts Reference depth estimation in GPU), a GPU accelerated DERS able to produce depth maps from RGB and HS images. In this paper, due to the lack of HS multi-view datasets at the moment, results are reported on RGB images to validate the acceleration strategy.GoRG shows a ×25 average speed-up compared to baseline DERS 8.0, reducing total computation time from around one hour for 8 frames to only a few minutes. A consequence of our parallelization is an average decrease of 1.6 dB in Weighted-to-Spherically-Uniform Peak-Signal-to-Noise-Ratio (WS-PSNR), with some remarkable disparities approaching 4 dB. However, using Structural Similarity Index (SSIM) as metric results come closer to baseline DERS. Effectively, an average decrease of only 1.20% is achieved showing that the obtained speed-up gains compesate the subjective quality losses.
高光谱(HS)图像通常用于不同领域的分类任务,例如医学。在这一领域,最近的一个应用是区分健康组织和不同类型的癌组织。为此,已经提出了不同的机器学习技术来生成分类图,这些分类图表明图像中每个像素对应的组织类型。这些2D表示可以单独使用,但它们不能与其他有价值的数据源(如磁共振成像(MRI))正确注册,这可以提高系统的准确性。为此,本文建立了一个多模态分类系统的基础,将三维信息纳入到HS图像中。具体来说,我们解决了深度估计工具/算法中的一个热点加速问题。MPEG-I深度估计参考软件(DERS)提供高质量的深度图依赖于一个全局能量优化算法:图形切割。然而,该算法需要大量的处理时间,阻碍了其在外科手术中的应用。本文介绍了GoRG (Graph cuts Reference depth estimation in GPU),这是一种GPU加速的DERS,能够从RGB和HS图像中生成深度图。由于目前缺乏HS多视图数据集,本文报道了RGB图像上的结果来验证加速策略。与基线DERS 8.0相比,GoRG显示了×25平均加速,将总计算时间从8帧的大约1小时减少到仅几分钟。我们的并行化的结果是加权球均匀峰值信噪比(WS-PSNR)平均降低1.6 dB,其中一些显著的差异接近4 dB。然而,使用结构相似指数(SSIM)作为度量结果更接近基线DERS。有效地,平均仅降低了1.20%,表明所获得的加速增益补偿了主观质量损失。
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引用次数: 1
Voltage Multiplier Topologies Comparison for UHF RFID Applications 超高频RFID应用的电压乘法器拓扑比较
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268624
Diego Golpe Molinos, H. Solar, A. Beriain, R. Berenguer
Due to the limited power that can be obtained from the RF field, UHF RFID systems need to be able to operate with few dozens of µW. Therefore, an efficient voltage multiplier is a key element to obtain tags able to operate at long ranges and with advanced functionalities. The objective of this work, is obtaining a topology able to provide the required operative voltage with the minimum RF input power. The highest possible sensitivity and efficiency will provide the longest range, which is a critical parameter in UHF RFID applications. Factors such as transistor and diode size and number of stages have been analyzed in order to obtain the maximum sensitivity and power conversion efficiency (PCE). In this paper, four voltage multipliers are developed and analysed, following the same methodology using a 180µm process. Sensitivities as high as -12dBm and PCEs up to 16% with a load of 7µA are obtained in the Schottky multiplier, during simulation of an input power range from - 15dBm to -8dBm.
由于可以从射频场获得的功率有限,UHF RFID系统需要能够在几十μ W的情况下工作。因此,高效的电压倍增器是获得能够远距离操作并具有先进功能的标签的关键因素。这项工作的目标是获得一种拓扑结构,能够以最小的射频输入功率提供所需的工作电压。最高的灵敏度和效率将提供最长的范围,这是超高频RFID应用的关键参数。为了获得最大的灵敏度和功率转换效率(PCE),对晶体管和二极管的尺寸和级数等因素进行了分析。在本文中,开发和分析了四个电压倍增器,遵循相同的方法,使用180µm工艺。在模拟输入功率范围为- 15dBm至- 8dbm的情况下,肖特基乘子的灵敏度高达- 12dbm, pce高达16%,负载为7µa。
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引用次数: 0
A Current-Attenuator for Performing Read Operation in Memristor-Based Spiking Neural Networks 基于记忆阻器的脉冲神经网络读操作的电流衰减器
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268655
J. Ahmadi-Farsani, B. Linares-Barranco, T. Serrano-Gotarredona
This paper presents a current attenuator fabricated in a CMOS 180nm technology, which works based on a CMOS ladder scheme. The attenuation factor is 104.14 dB, while it shows a non-linearity feature of less than 1.8 %. The circuit occupies an area of 2448 µm2. Since the output current could be as low as tens of femtoamperes, an on-chip testing circuit is also proposed to make the lab-measurements as accurate as possible. The final results show that chip-measurements are following simulations. As a demonstrator, the current attenuator is internally connected to a compact CMOS neuron cell. The output membrane potential shows that the neuron is generating a real-time firing modality, and consequently approves that the current-attenuator is working robustly.
本文介绍了一种基于CMOS梯形结构的180nm CMOS电流衰减器。衰减系数为104.14 dB,非线性特性小于1.8%。电路占地面积为2448µm2。由于输出电流可以低至几十飞安培,因此还提出了一种片上测试电路,以使实验室测量尽可能准确。最终结果表明,芯片测量符合仿真。作为演示,电流衰减器内部连接到一个紧凑的CMOS神经元细胞。输出膜电位显示神经元正在产生实时放电模式,从而证实电流衰减器工作稳健。
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引用次数: 0
Oscillatory Hebbian Rule (OHR): An adaption of the Hebbian rule to Oscillatory Neural Networks 振荡Hebbian规则(OHR):将Hebbian规则应用于振荡神经网络
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268618
Jafar Shamsi, M. Avedillo, B. Linares-Barranco, T. Serrano-Gotarredona
Hebbian rule plays an important role in training of artificial neural networks. According to this rule, a synaptic weight between two neurons is increased or decreased depending on the activity of the presynaptic and postsynaptic neurons. In this paper, an oscillatory version of the Hebbian rule is proposed for ONNs and is called Oscillatory Hebbian Rule (OHR). OHR simply expresses the weight change as a function of the phase difference between the presynaptic and postsynaptic neurons. Similar to STDP that weight change is an exponential function of the time difference between the presynaptic and postsynaptic spikes, OHR relates weight change to the phase difference between the presynaptic and postsynaptic neurons using exponential functions. Specifically, when two neurons are in-phase, the weight between them is increased while a weight between two anti-phase neurons is decreased. Simulation results show the capability of OHR for both supervised and unsupervised learning. In supervised learning, a basic block of feedforward architectures is trained as a classifier. When the basic block is used in unsupervised mode, it is capable to learn patterns while the output phase is converged to a specific phase.
赫比规则在人工神经网络的训练中起着重要的作用。根据这一规则,两个神经元之间的突触权重的增加或减少取决于突触前和突触后神经元的活动。本文提出了一种振荡版的onn Hebbian规则,称为振荡Hebbian规则(OHR)。OHR简单地将权重变化表示为突触前和突触后神经元之间相位差的函数。与STDP相似,权重变化是突触前和突触后尖峰之间时间差的指数函数,OHR使用指数函数将权重变化与突触前和突触后神经元之间的相位差联系起来。具体来说,当两个神经元处于同相时,它们之间的权值增加,而两个反相神经元之间的权值减少。仿真结果表明,该方法具有监督学习和无监督学习的能力。在监督学习中,前馈结构的基本块被训练成分类器。当基本块在无监督模式下使用时,它能够在输出阶段收敛到特定阶段时学习模式。
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引用次数: 2
High-Speed and Energy-Efficient Ring-Oscillator for Analog-to-Digital Conversion 用于模数转换的高速节能环形振荡器
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268623
Leidy Mabel Alvero-Gonzalez, Luis Hernandez Corporales, Eric Gutierrez
Highly dependence of the power consumption with respect to the voltage supply makes current finer CMOS technologies become supplied with lower-than-1 V. Voltage-controlled-oscillator based analog-to-digital converters implemented with ring-oscillators scales properly with that requirement. However, conventional implementations of ring-oscillators limit the oscillation frequency due to the lack of available voltage to feed high currents. In this manuscript, we propose a novel circuit for a ring-oscillator that overcomes this issue. With only two devices between the supply nodes a delay cell is built. This allows us to reduce the voltage supply for certain oscillation requirements. In addition, the lower number of devices connected to the output nodes supposes lower parasitic capacitance and a reduction in the minimum achievable time delay, which increases the potential resolution. The proposed circuit is theoretically described and validated by simulation in a 65-nm CMOS process. Comparisons to the conventional implementations are made, showing improvements in terms of resolution, power, and area.
功耗与电压供应的高度依赖使得当前精细的CMOS技术的供电电压低于- 1v。采用环形振荡器实现的基于压控振荡器的模数转换器可以满足这一要求。然而,传统的环形振荡器的实现限制了振荡频率,因为缺乏可用的电压来馈送大电流。在本文中,我们提出了一种新的环形振荡器电路,克服了这个问题。只有两个设备之间的供应节点是建立一个延迟单元。这使我们能够减少某些振荡要求的电压供应。此外,连接到输出节点的器件数量越少,寄生电容就越低,可实现的最小时间延迟也会减少,从而提高了潜在的分辨率。对该电路进行了理论描述,并在65纳米CMOS工艺中进行了仿真验证。与传统实现进行了比较,显示了在分辨率、功耗和面积方面的改进。
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引用次数: 0
期刊
2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)
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