Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268613
L. Muguira, Jesús Lázaro, Sara Alonso, A. Astarloa, Mikel Rodríguez
The convergence of operational technology (OT) and information technology (IT) in the same network is essential for upcoming digitized scenarios, such as the Electric Sector, Smart-Grid, and Substation Automation Systems (SAS). The typical separation of these two areas in the traditional Ethernet standard is increasingly disappearing. Furthermore, security requirements must be fulfilled in the involved systems and infrastructures. It is the case of the Electric Sector, which is aware of this necessity and it is trying to protect all digitized data streams, even the most critical one with tight real-time requirements. The technology that allows this OT/IT integration is Deterministic Ethernet. The standard and interoperable Deterministic Ethernet alternative is named Time-Sensitive Networking (TSN) standard. TSN offers a convergent, interoperable, deterministic, and uniform network. However, it lacks from security mechanisms for real-time traffic. This paper presents a concept-proof work used to prove that the hard real-time traffic used in the power substations can be protected using wire-speed cryptography and data-flow hardware processing approach.
{"title":"Secure Critical Traffic of the Electric Sector over Time-Sensitive Networking","authors":"L. Muguira, Jesús Lázaro, Sara Alonso, A. Astarloa, Mikel Rodríguez","doi":"10.1109/DCIS51330.2020.9268613","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268613","url":null,"abstract":"The convergence of operational technology (OT) and information technology (IT) in the same network is essential for upcoming digitized scenarios, such as the Electric Sector, Smart-Grid, and Substation Automation Systems (SAS). The typical separation of these two areas in the traditional Ethernet standard is increasingly disappearing. Furthermore, security requirements must be fulfilled in the involved systems and infrastructures. It is the case of the Electric Sector, which is aware of this necessity and it is trying to protect all digitized data streams, even the most critical one with tight real-time requirements. The technology that allows this OT/IT integration is Deterministic Ethernet. The standard and interoperable Deterministic Ethernet alternative is named Time-Sensitive Networking (TSN) standard. TSN offers a convergent, interoperable, deterministic, and uniform network. However, it lacks from security mechanisms for real-time traffic. This paper presents a concept-proof work used to prove that the hard real-time traffic used in the power substations can be protected using wire-speed cryptography and data-flow hardware processing approach.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121651382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268628
J. A. Miranda, M. F. Canabal, L. Gutiérrez-Martín, J. M. Lanza-Gutiérrez, C. López-Ongil
The combination of smart sensors and affective computing capabilities in wearable devices enables future technological integration horizons for high added value applications. Among the usual information considered in the field of affective computing, those based on physiology have gained special attention in recent years, since it is related to the autonomic nervous system (ANS), which is responsible for physiological regulation for stress and relaxed situations. One usual physiological metric is heart rate variability (HRV), from which information related to ANS activation can be extracted. The analog front end circuitry for physiological smart sensors is facing a revolution including not only signal conditioning but signal processing capabilities as well. However, despite the efficiency offered by the sensors, an exhaustive design space exploration (DSE) for every sensor involved within the system is recommended to maximize the embedded resource usage. This paper presents a detailed DSE for every stage involved in an HRV based wearable affective computing device developed by the authors. Different signal processing elements are implemented, resulting in a collection of recommendations based on particular wearable applications needs, such as inference time and accuracy of useful affective information extracted. A particular continuous rapid inference use case by considering the DSE recommendations is implemented. This application reaches adequate precision for detecting stress by using only four second temporal processing window.
{"title":"A Design Space Exploration for Heart Rate Variability in a Wearable Smart Device","authors":"J. A. Miranda, M. F. Canabal, L. Gutiérrez-Martín, J. M. Lanza-Gutiérrez, C. López-Ongil","doi":"10.1109/DCIS51330.2020.9268628","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268628","url":null,"abstract":"The combination of smart sensors and affective computing capabilities in wearable devices enables future technological integration horizons for high added value applications. Among the usual information considered in the field of affective computing, those based on physiology have gained special attention in recent years, since it is related to the autonomic nervous system (ANS), which is responsible for physiological regulation for stress and relaxed situations. One usual physiological metric is heart rate variability (HRV), from which information related to ANS activation can be extracted. The analog front end circuitry for physiological smart sensors is facing a revolution including not only signal conditioning but signal processing capabilities as well. However, despite the efficiency offered by the sensors, an exhaustive design space exploration (DSE) for every sensor involved within the system is recommended to maximize the embedded resource usage. This paper presents a detailed DSE for every stage involved in an HRV based wearable affective computing device developed by the authors. Different signal processing elements are implemented, resulting in a collection of recommendations based on particular wearable applications needs, such as inference time and accuracy of useful affective information extracted. A particular continuous rapid inference use case by considering the DSE recommendations is implemented. This application reaches adequate precision for detecting stress by using only four second temporal processing window.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133298199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268645
Enrique Torres-Sánchez, Jesús Alastruey-Benedé, Enrique F. Torres Moreno
RISC-V is an emergent architecture that is gaining strength in low-power IoT applications. The stabilization of the architectural extensions and the start of commercialization of RISC-V based SOCs, like the Kendryte K210, raises the question of whether this open standard will facilitate the development of applications in specific markets or not.In this paper we evaluate the development environments, the toolchain, the debugging processes related to the Sipeed MAIX Go development board, as well as the standalone SDK and the Micropython port for the Kendryte K210. The training pipeline for the built-in convolutional neural network accelerator, with support for Tiny YOLO v2, has also been studied. In order to evaluate all the above aspects in depth, two low-cost, low-power, IoT edge applications based on AI have been developed. The first one is capable of recognizing movement in a house and autonomously identify whether it was caused by a human or by a house pet, like for example a dog or a cat. In the context of the current COVID-19 pandemic, the second application is capable of labeling whether a pedestrian is wearing a face mask or not, doing real-time object recognition at a mean rate of 13 FPS. Throughout the process, we can conclude that, despite the potential of the hardware and its excellent performance/cost ratio, the documentation for developers is scarce, the development environments are in low maturity levels, and the debugging processes are sometimes nonexistent.
{"title":"Developing an AI IoT application with open software on a RISC-V SoC","authors":"Enrique Torres-Sánchez, Jesús Alastruey-Benedé, Enrique F. Torres Moreno","doi":"10.1109/DCIS51330.2020.9268645","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268645","url":null,"abstract":"RISC-V is an emergent architecture that is gaining strength in low-power IoT applications. The stabilization of the architectural extensions and the start of commercialization of RISC-V based SOCs, like the Kendryte K210, raises the question of whether this open standard will facilitate the development of applications in specific markets or not.In this paper we evaluate the development environments, the toolchain, the debugging processes related to the Sipeed MAIX Go development board, as well as the standalone SDK and the Micropython port for the Kendryte K210. The training pipeline for the built-in convolutional neural network accelerator, with support for Tiny YOLO v2, has also been studied. In order to evaluate all the above aspects in depth, two low-cost, low-power, IoT edge applications based on AI have been developed. The first one is capable of recognizing movement in a house and autonomously identify whether it was caused by a human or by a house pet, like for example a dog or a cat. In the context of the current COVID-19 pandemic, the second application is capable of labeling whether a pedestrian is wearing a face mask or not, doing real-time object recognition at a mean rate of 13 FPS. Throughout the process, we can conclude that, despite the potential of the hardware and its excellent performance/cost ratio, the documentation for developers is scarce, the development environments are in low maturity levels, and the debugging processes are sometimes nonexistent.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116997352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268626
Álvaro Hernández, Rubén Nieto, David Fuentes, J. Ureña
In recent years the development and deployment of commercial Smart Meters in most households in developed countries have spread the appearance of certain applications and methods, mainly related to the fields of Smart Grids and Internet of Things, where Non-Intrusive Load Monitoring (NILM) is one of the most well-known. It takes advantage of the capability of Smart Meters to acquire the electrical signals of a household or building in real time, in order to implement a set of techniques oriented to disaggregate the power consumption, according to the different electrical loads plugged in the facility. Previous works are often based on a cloud-computing approach, where samples are transferred straightforwardly from the local meter to the cloud for further analysis. This implies that the sampling rates are low in order to keep the required bandwidth reduced, thus constraining the final performance achieved in the load identification. This work presents the design of a System-on-Chip (SoC) architecture based on a Field-Programmable Gate Array (FPGA) device that can be installed locally at the input of the electrical installation from a house or building. It is able to manage data rates at high sampling frequencies and to implement in real time those algorithms proposed for the electrical signal processing and load classification. Experimental results have preliminary validated the proposed architecture.
{"title":"Design of a SoC Architecture for the Edge Computing of NILM Techniques","authors":"Álvaro Hernández, Rubén Nieto, David Fuentes, J. Ureña","doi":"10.1109/DCIS51330.2020.9268626","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268626","url":null,"abstract":"In recent years the development and deployment of commercial Smart Meters in most households in developed countries have spread the appearance of certain applications and methods, mainly related to the fields of Smart Grids and Internet of Things, where Non-Intrusive Load Monitoring (NILM) is one of the most well-known. It takes advantage of the capability of Smart Meters to acquire the electrical signals of a household or building in real time, in order to implement a set of techniques oriented to disaggregate the power consumption, according to the different electrical loads plugged in the facility. Previous works are often based on a cloud-computing approach, where samples are transferred straightforwardly from the local meter to the cloud for further analysis. This implies that the sampling rates are low in order to keep the required bandwidth reduced, thus constraining the final performance achieved in the load identification. This work presents the design of a System-on-Chip (SoC) architecture based on a Field-Programmable Gate Array (FPGA) device that can be installed locally at the input of the electrical installation from a house or building. It is able to manage data rates at high sampling frequencies and to implement in real time those algorithms proposed for the electrical signal processing and load classification. Experimental results have preliminary validated the proposed architecture.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130669684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268659
Ingrid Kovacs, M. Topa, Monica Ene, Andi Buzo, G. Pelz
Adaptive verification appears to be an e client solution to overcome the coverage problem and to accurately characterize the failure region of high dimensional spaces at integrated circuits’ verification. Its main task is to gather more samples in the regions of interest based on the information learnt from previous samples. This helps engineers understand and interpret the behavior of the system under study with a reduced number of simulations/measurements compared to classical verification methods. To this end, we propose an adaptive sampling approach for the failure region characterization using the concept of metamodeling. Compared to other sampling methods for the failure region characterization, it has the advantage that it can detect and sample more in the near-failure region in the absence of a fail region. The concept has been applied on several synthetic test functions and on lab measurements of an analog integrated circuit. Results reveal that this adaptive sampling approach is very promising for failure region characterization.
{"title":"A metamodel-based adaptive sampling approach for efficient failure region characterization of integrated circuits","authors":"Ingrid Kovacs, M. Topa, Monica Ene, Andi Buzo, G. Pelz","doi":"10.1109/DCIS51330.2020.9268659","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268659","url":null,"abstract":"Adaptive verification appears to be an e client solution to overcome the coverage problem and to accurately characterize the failure region of high dimensional spaces at integrated circuits’ verification. Its main task is to gather more samples in the regions of interest based on the information learnt from previous samples. This helps engineers understand and interpret the behavior of the system under study with a reduced number of simulations/measurements compared to classical verification methods. To this end, we propose an adaptive sampling approach for the failure region characterization using the concept of metamodeling. Compared to other sampling methods for the failure region characterization, it has the advantage that it can detect and sample more in the near-failure region in the absence of a fail region. The concept has been applied on several synthetic test functions and on lab measurements of an analog integrated circuit. Results reveal that this adaptive sampling approach is very promising for failure region characterization.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133805429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268660
Samira Briongos, P. Malagón, Jose M. Moya, T. Eisenbarth
Trusted Execution Environments (TEEs) aim to provide integrity and confidentiality guarantees to certain computations irrespective of the state of the rest of the system. That is, they protect Trusted Applications (TAs) even if the Operating System or the hypervisor are compromised. The TEE runs in parallel with the OS and leverages a set of hardware and software components to create such an isolated environment. However, this isolation can be broken by exploiting microarchitectural side-channels. The state of the shared components of multi-core processors depends on the actual processes being executed, and as a result, some information is leaked from one process to any other running in the same processor. This leakage completely breaks the confidentiality guarantees that TEEs promise. The only way to completely avoid the leakage is to avoid the share of resources, but this is nearly impossible to achieve without a huge degradation in the performance of the processor. Assuming that it is possible that the leakage exists, and the attacker only can get information from the observable microarchitectural state, we propose to monitor the hardware resources to detect the microarchitectural state changes caused by the attacks. To this end, we have implemented a hardware module that compares at runtime pre-stored microarchitectural execution signatures of each enclave, with the actual execution trace, and triggers an alarm when it detects significant variation.
{"title":"Microarchitectural Isolation Guarantees Through Execution Based Signatures","authors":"Samira Briongos, P. Malagón, Jose M. Moya, T. Eisenbarth","doi":"10.1109/DCIS51330.2020.9268660","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268660","url":null,"abstract":"Trusted Execution Environments (TEEs) aim to provide integrity and confidentiality guarantees to certain computations irrespective of the state of the rest of the system. That is, they protect Trusted Applications (TAs) even if the Operating System or the hypervisor are compromised. The TEE runs in parallel with the OS and leverages a set of hardware and software components to create such an isolated environment. However, this isolation can be broken by exploiting microarchitectural side-channels. The state of the shared components of multi-core processors depends on the actual processes being executed, and as a result, some information is leaked from one process to any other running in the same processor. This leakage completely breaks the confidentiality guarantees that TEEs promise. The only way to completely avoid the leakage is to avoid the share of resources, but this is nearly impossible to achieve without a huge degradation in the performance of the processor. Assuming that it is possible that the leakage exists, and the attacker only can get information from the observable microarchitectural state, we propose to monitor the hardware resources to detect the microarchitectural state changes caused by the attacks. To this end, we have implemented a hardware module that compares at runtime pre-stored microarchitectural execution signatures of each enclave, with the actual execution trace, and triggers an alarm when it detects significant variation.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130112899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268625
Raquel León, Beatriz Martínez-Vega, H. Fabelo, S. Ortega, G. Callicó, Francisco Balea-Fernández, C. B. Sieyro
Neurocognitive disorders (NCD) affect over 50 million people globally. The detection biomarkers using brain imaging or cerebrospinal fluid are expensive procedures. Blood-based biomarkers such as plasma or serum present a cost-effective alternative. The work presented in this paper is focused on the use of hyperspectral (HS) imaging (HSI) to classify plasma samples in order to discriminate between patients with major NCD and healthy control subjects. HS images of plasma samples were obtained using a SWIR (Short-Wave Infrared) camera able to capture 273 bands within the 900-2,500 nm spectral range. A preliminary HSI database was obtained with 20 major NCD samples and 20 control samples. This data was segmented and classified using pixel-wise supervised classification algorithms, achieving 75% sensitivity and 100% specificity results with the best classifier in the test set.
{"title":"Hyperspectral Imaging for Major Neurocognitive Disorder Detection in Plasma Samples","authors":"Raquel León, Beatriz Martínez-Vega, H. Fabelo, S. Ortega, G. Callicó, Francisco Balea-Fernández, C. B. Sieyro","doi":"10.1109/DCIS51330.2020.9268625","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268625","url":null,"abstract":"Neurocognitive disorders (NCD) affect over 50 million people globally. The detection biomarkers using brain imaging or cerebrospinal fluid are expensive procedures. Blood-based biomarkers such as plasma or serum present a cost-effective alternative. The work presented in this paper is focused on the use of hyperspectral (HS) imaging (HSI) to classify plasma samples in order to discriminate between patients with major NCD and healthy control subjects. HS images of plasma samples were obtained using a SWIR (Short-Wave Infrared) camera able to capture 273 bands within the 900-2,500 nm spectral range. A preliminary HSI database was obtained with 20 major NCD samples and 20 control samples. This data was segmented and classified using pixel-wise supervised classification algorithms, achieving 75% sensitivity and 100% specificity results with the best classifier in the test set.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"319 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133314845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268668
Luis Esteban, J. A. Martín, A. Regadío
The implementation of algorithms in fixed-point format causes the apparition of Round-Off Noise which propagates through the different functional units of the system. This issue causes the Signal-to-Noise Ratio of the outputs is degraded. Given an algorithm, it is essential to estimate the integer and fractional bit-widths of all the variables and operations to comply with the Signal-to-Noise Ratio requirements. In this context, Affine Arithmetic can obtain fast and accurate estimations of the bit-widths for linear systems. However, for non-linear systems, Affine Arithmetic loses the temporal correlation of the variables. Other existing frameworks are either time consuming or lead to inaccurate bound estimations. In this paper, a Modified Affine Arithmetic framework with Legendre polynomials is used to obtain fast and accurate bound estimations also for non-linear systems. Moreover, the approach proposed in this paper obtains speedups in the range of 7 to 100 compared to Monte-Carlo simulations.
{"title":"Round-off noise estimation of fixed-point algorithms using Modified Affine Arithmetic and Legendre Polynomials","authors":"Luis Esteban, J. A. Martín, A. Regadío","doi":"10.1109/DCIS51330.2020.9268668","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268668","url":null,"abstract":"The implementation of algorithms in fixed-point format causes the apparition of Round-Off Noise which propagates through the different functional units of the system. This issue causes the Signal-to-Noise Ratio of the outputs is degraded. Given an algorithm, it is essential to estimate the integer and fractional bit-widths of all the variables and operations to comply with the Signal-to-Noise Ratio requirements. In this context, Affine Arithmetic can obtain fast and accurate estimations of the bit-widths for linear systems. However, for non-linear systems, Affine Arithmetic loses the temporal correlation of the variables. Other existing frameworks are either time consuming or lead to inaccurate bound estimations. In this paper, a Modified Affine Arithmetic framework with Legendre polynomials is used to obtain fast and accurate bound estimations also for non-linear systems. Moreover, the approach proposed in this paper obtains speedups in the range of 7 to 100 compared to Monte-Carlo simulations.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114780058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268670
Medina Bandic, Hossein Zarein, E. Alarcón, C. G. Almudever
Quantum algorithms can be expressed as quantum circuits when the circuit model of computation is adopted. Such a circuit description is usually hardware-agnostic, that is, it does not consider the limitations that the quantum hardware might have. In order to make quantum algorithms executable on quantum devices they need to comply to their constraints, which mainly affect the parallelism of quantum operations and the possible interactions between the qubits. The process of adapting a quantum circuit to meet the quantum chip restrictions is known as mapping. The resulting circuit usually has a higher number of gates and depth, decreasing the algorithm's reliability. Different mapping solutions have been already proposed. Most of them are meant for a specific quantum processor and differ in methodology, approach and features. In addition, they are usually only compared in terms of added gates, circuit depth and compilation time. No thorough comparative analysis of the different mapping solutions performance and features has been performed so far.In this paper, we propose to apply structured design space exploration (DSE) methodologies to the mapping procedures. This will allow not only to have a more in depth and structured analysis of their performance but also to identify what features are key and worth to implement. By using DSE we will be able to: i) determine in what regimes some mapping solutions outperform others; ii) derive optimal mapping strategies for specific quantum algorithms and quantum processors; and iii) perform an scalability analysis. In addition, DSE techniques cannot only be applied to the mapping layer that is key for bridging quantum applications to quantum devices, but also to the full-stack quantum computing system allowing for its crosslayer co-design.
{"title":"On Structured Design Space Exploration for Mapping of Quantum Algorithms","authors":"Medina Bandic, Hossein Zarein, E. Alarcón, C. G. Almudever","doi":"10.1109/DCIS51330.2020.9268670","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268670","url":null,"abstract":"Quantum algorithms can be expressed as quantum circuits when the circuit model of computation is adopted. Such a circuit description is usually hardware-agnostic, that is, it does not consider the limitations that the quantum hardware might have. In order to make quantum algorithms executable on quantum devices they need to comply to their constraints, which mainly affect the parallelism of quantum operations and the possible interactions between the qubits. The process of adapting a quantum circuit to meet the quantum chip restrictions is known as mapping. The resulting circuit usually has a higher number of gates and depth, decreasing the algorithm's reliability. Different mapping solutions have been already proposed. Most of them are meant for a specific quantum processor and differ in methodology, approach and features. In addition, they are usually only compared in terms of added gates, circuit depth and compilation time. No thorough comparative analysis of the different mapping solutions performance and features has been performed so far.In this paper, we propose to apply structured design space exploration (DSE) methodologies to the mapping procedures. This will allow not only to have a more in depth and structured analysis of their performance but also to identify what features are key and worth to implement. By using DSE we will be able to: i) determine in what regimes some mapping solutions outperform others; ii) derive optimal mapping strategies for specific quantum algorithms and quantum processors; and iii) perform an scalability analysis. In addition, DSE techniques cannot only be applied to the mapping layer that is key for bridging quantum applications to quantum devices, but also to the full-stack quantum computing system allowing for its crosslayer co-design.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"668 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122622249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/dcis51330.2020.9268657
{"title":"DCIS 2020 TOC","authors":"","doi":"10.1109/dcis51330.2020.9268657","DOIUrl":"https://doi.org/10.1109/dcis51330.2020.9268657","url":null,"abstract":"","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122244701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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