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2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)最新文献

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Secure Critical Traffic of the Electric Sector over Time-Sensitive Networking 确保电力部门在时间敏感网络上的关键流量
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268613
L. Muguira, Jesús Lázaro, Sara Alonso, A. Astarloa, Mikel Rodríguez
The convergence of operational technology (OT) and information technology (IT) in the same network is essential for upcoming digitized scenarios, such as the Electric Sector, Smart-Grid, and Substation Automation Systems (SAS). The typical separation of these two areas in the traditional Ethernet standard is increasingly disappearing. Furthermore, security requirements must be fulfilled in the involved systems and infrastructures. It is the case of the Electric Sector, which is aware of this necessity and it is trying to protect all digitized data streams, even the most critical one with tight real-time requirements. The technology that allows this OT/IT integration is Deterministic Ethernet. The standard and interoperable Deterministic Ethernet alternative is named Time-Sensitive Networking (TSN) standard. TSN offers a convergent, interoperable, deterministic, and uniform network. However, it lacks from security mechanisms for real-time traffic. This paper presents a concept-proof work used to prove that the hard real-time traffic used in the power substations can be protected using wire-speed cryptography and data-flow hardware processing approach.
运营技术(OT)和信息技术(IT)在同一网络中的融合对于即将到来的数字化场景至关重要,例如电力部门、智能电网和变电站自动化系统(SAS)。在传统的以太网标准中,这两个领域的典型分离正在逐渐消失。此外,所涉及的系统和基础设施必须满足安全需求。电力部门就是这样,它意识到这种必要性,并试图保护所有数字化数据流,即使是对实时要求最严格的最关键的数据流。允许这种OT/IT集成的技术是确定性以太网。标准和可互操作的确定性以太网替代方案被称为时间敏感网络(TSN)标准。TSN提供了一个融合的、可互操作的、确定的和统一的网络。然而,它缺乏对实时流量的安全机制。本文提出了一种概念验证工作,用于证明采用线速加密和数据流硬件处理方法可以保护变电站中使用的硬实时流量。
{"title":"Secure Critical Traffic of the Electric Sector over Time-Sensitive Networking","authors":"L. Muguira, Jesús Lázaro, Sara Alonso, A. Astarloa, Mikel Rodríguez","doi":"10.1109/DCIS51330.2020.9268613","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268613","url":null,"abstract":"The convergence of operational technology (OT) and information technology (IT) in the same network is essential for upcoming digitized scenarios, such as the Electric Sector, Smart-Grid, and Substation Automation Systems (SAS). The typical separation of these two areas in the traditional Ethernet standard is increasingly disappearing. Furthermore, security requirements must be fulfilled in the involved systems and infrastructures. It is the case of the Electric Sector, which is aware of this necessity and it is trying to protect all digitized data streams, even the most critical one with tight real-time requirements. The technology that allows this OT/IT integration is Deterministic Ethernet. The standard and interoperable Deterministic Ethernet alternative is named Time-Sensitive Networking (TSN) standard. TSN offers a convergent, interoperable, deterministic, and uniform network. However, it lacks from security mechanisms for real-time traffic. This paper presents a concept-proof work used to prove that the hard real-time traffic used in the power substations can be protected using wire-speed cryptography and data-flow hardware processing approach.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121651382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Design Space Exploration for Heart Rate Variability in a Wearable Smart Device 可穿戴智能设备中心率变异性的设计空间探索
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268628
J. A. Miranda, M. F. Canabal, L. Gutiérrez-Martín, J. M. Lanza-Gutiérrez, C. López-Ongil
The combination of smart sensors and affective computing capabilities in wearable devices enables future technological integration horizons for high added value applications. Among the usual information considered in the field of affective computing, those based on physiology have gained special attention in recent years, since it is related to the autonomic nervous system (ANS), which is responsible for physiological regulation for stress and relaxed situations. One usual physiological metric is heart rate variability (HRV), from which information related to ANS activation can be extracted. The analog front end circuitry for physiological smart sensors is facing a revolution including not only signal conditioning but signal processing capabilities as well. However, despite the efficiency offered by the sensors, an exhaustive design space exploration (DSE) for every sensor involved within the system is recommended to maximize the embedded resource usage. This paper presents a detailed DSE for every stage involved in an HRV based wearable affective computing device developed by the authors. Different signal processing elements are implemented, resulting in a collection of recommendations based on particular wearable applications needs, such as inference time and accuracy of useful affective information extracted. A particular continuous rapid inference use case by considering the DSE recommendations is implemented. This application reaches adequate precision for detecting stress by using only four second temporal processing window.
可穿戴设备中智能传感器和情感计算能力的结合,为高附加值应用的未来技术集成提供了前景。在情感计算领域通常考虑的信息中,基于生理学的信息近年来受到了特别的关注,因为它与自主神经系统(ANS)有关,而自主神经系统负责对压力和放松情况进行生理调节。一种常用的生理指标是心率变异性(HRV),从中可以提取与ANS激活相关的信息。生理智能传感器的模拟前端电路正面临着一场革命,不仅包括信号调理,还包括信号处理能力。然而,尽管传感器提供了效率,建议对系统中涉及的每个传感器进行详尽的设计空间探索(DSE),以最大限度地利用嵌入式资源。本文介绍了作者开发的基于HRV的可穿戴情感计算设备所涉及的每个阶段的详细DSE。实现了不同的信号处理元素,从而产生基于特定可穿戴应用需求的建议集合,例如提取有用情感信息的推理时间和准确性。通过考虑DSE建议,实现了一个特定的连续快速推理用例。该应用程序仅使用四秒的时间处理窗口,即可达到足够的应力检测精度。
{"title":"A Design Space Exploration for Heart Rate Variability in a Wearable Smart Device","authors":"J. A. Miranda, M. F. Canabal, L. Gutiérrez-Martín, J. M. Lanza-Gutiérrez, C. López-Ongil","doi":"10.1109/DCIS51330.2020.9268628","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268628","url":null,"abstract":"The combination of smart sensors and affective computing capabilities in wearable devices enables future technological integration horizons for high added value applications. Among the usual information considered in the field of affective computing, those based on physiology have gained special attention in recent years, since it is related to the autonomic nervous system (ANS), which is responsible for physiological regulation for stress and relaxed situations. One usual physiological metric is heart rate variability (HRV), from which information related to ANS activation can be extracted. The analog front end circuitry for physiological smart sensors is facing a revolution including not only signal conditioning but signal processing capabilities as well. However, despite the efficiency offered by the sensors, an exhaustive design space exploration (DSE) for every sensor involved within the system is recommended to maximize the embedded resource usage. This paper presents a detailed DSE for every stage involved in an HRV based wearable affective computing device developed by the authors. Different signal processing elements are implemented, resulting in a collection of recommendations based on particular wearable applications needs, such as inference time and accuracy of useful affective information extracted. A particular continuous rapid inference use case by considering the DSE recommendations is implemented. This application reaches adequate precision for detecting stress by using only four second temporal processing window.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133298199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Developing an AI IoT application with open software on a RISC-V SoC 在RISC-V SoC上使用开放软件开发AI物联网应用程序
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268645
Enrique Torres-Sánchez, Jesús Alastruey-Benedé, Enrique F. Torres Moreno
RISC-V is an emergent architecture that is gaining strength in low-power IoT applications. The stabilization of the architectural extensions and the start of commercialization of RISC-V based SOCs, like the Kendryte K210, raises the question of whether this open standard will facilitate the development of applications in specific markets or not.In this paper we evaluate the development environments, the toolchain, the debugging processes related to the Sipeed MAIX Go development board, as well as the standalone SDK and the Micropython port for the Kendryte K210. The training pipeline for the built-in convolutional neural network accelerator, with support for Tiny YOLO v2, has also been studied. In order to evaluate all the above aspects in depth, two low-cost, low-power, IoT edge applications based on AI have been developed. The first one is capable of recognizing movement in a house and autonomously identify whether it was caused by a human or by a house pet, like for example a dog or a cat. In the context of the current COVID-19 pandemic, the second application is capable of labeling whether a pedestrian is wearing a face mask or not, doing real-time object recognition at a mean rate of 13 FPS. Throughout the process, we can conclude that, despite the potential of the hardware and its excellent performance/cost ratio, the documentation for developers is scarce, the development environments are in low maturity levels, and the debugging processes are sometimes nonexistent.
RISC-V是一种新兴架构,在低功耗物联网应用中越来越强大。架构扩展的稳定和基于RISC-V的soc商业化的开始,比如Kendryte K210,提出了这个开放标准是否会促进特定市场应用程序的开发的问题。在本文中,我们评估了与Sipeed MAIX Go开发板相关的开发环境,工具链,调试过程,以及Kendryte K210的独立SDK和Micropython端口。本文还研究了支持Tiny YOLO v2的内置卷积神经网络加速器的训练管道。为了深入评估上述所有方面,我们开发了两个基于AI的低成本、低功耗物联网边缘应用。第一个能够识别房子里的运动,并自主识别它是由人类还是宠物引起的,比如狗或猫。在新型冠状病毒感染症(COVID-19)大流行的背景下,第二个应用程序能够标记行人是否戴着口罩,以平均每秒13帧的速度进行实时物体识别。在整个过程中,我们可以得出这样的结论:尽管硬件的潜力及其出色的性能/成本比,但开发人员的文档很少,开发环境处于较低的成熟度级别,并且有时不存在调试过程。
{"title":"Developing an AI IoT application with open software on a RISC-V SoC","authors":"Enrique Torres-Sánchez, Jesús Alastruey-Benedé, Enrique F. Torres Moreno","doi":"10.1109/DCIS51330.2020.9268645","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268645","url":null,"abstract":"RISC-V is an emergent architecture that is gaining strength in low-power IoT applications. The stabilization of the architectural extensions and the start of commercialization of RISC-V based SOCs, like the Kendryte K210, raises the question of whether this open standard will facilitate the development of applications in specific markets or not.In this paper we evaluate the development environments, the toolchain, the debugging processes related to the Sipeed MAIX Go development board, as well as the standalone SDK and the Micropython port for the Kendryte K210. The training pipeline for the built-in convolutional neural network accelerator, with support for Tiny YOLO v2, has also been studied. In order to evaluate all the above aspects in depth, two low-cost, low-power, IoT edge applications based on AI have been developed. The first one is capable of recognizing movement in a house and autonomously identify whether it was caused by a human or by a house pet, like for example a dog or a cat. In the context of the current COVID-19 pandemic, the second application is capable of labeling whether a pedestrian is wearing a face mask or not, doing real-time object recognition at a mean rate of 13 FPS. Throughout the process, we can conclude that, despite the potential of the hardware and its excellent performance/cost ratio, the documentation for developers is scarce, the development environments are in low maturity levels, and the debugging processes are sometimes nonexistent.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116997352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design of a SoC Architecture for the Edge Computing of NILM Techniques 面向NILM边缘计算技术的SoC架构设计
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268626
Álvaro Hernández, Rubén Nieto, David Fuentes, J. Ureña
In recent years the development and deployment of commercial Smart Meters in most households in developed countries have spread the appearance of certain applications and methods, mainly related to the fields of Smart Grids and Internet of Things, where Non-Intrusive Load Monitoring (NILM) is one of the most well-known. It takes advantage of the capability of Smart Meters to acquire the electrical signals of a household or building in real time, in order to implement a set of techniques oriented to disaggregate the power consumption, according to the different electrical loads plugged in the facility. Previous works are often based on a cloud-computing approach, where samples are transferred straightforwardly from the local meter to the cloud for further analysis. This implies that the sampling rates are low in order to keep the required bandwidth reduced, thus constraining the final performance achieved in the load identification. This work presents the design of a System-on-Chip (SoC) architecture based on a Field-Programmable Gate Array (FPGA) device that can be installed locally at the input of the electrical installation from a house or building. It is able to manage data rates at high sampling frequencies and to implement in real time those algorithms proposed for the electrical signal processing and load classification. Experimental results have preliminary validated the proposed architecture.
近年来,发达国家商用智能电表的发展和在大多数家庭中的部署,已经传播了一些应用和方法的出现,主要涉及智能电网和物联网领域,其中非侵入式负荷监测(NILM)最为人所知。它利用智能电表的功能实时获取家庭或建筑物的电信号,以便根据插入设备的不同电力负荷实施一套面向分解功耗的技术。以前的工作通常基于云计算方法,其中样品直接从本地仪表转移到云端进行进一步分析。这意味着采样率较低,以保持所需的带宽减少,从而限制了在负载识别中实现的最终性能。这项工作提出了基于现场可编程门阵列(FPGA)设备的片上系统(SoC)架构的设计,该设备可以安装在房屋或建筑物电气装置的本地输入处。它能够在高采样频率下管理数据速率,并实时实现用于电信号处理和负载分类的算法。实验结果初步验证了所提出的结构。
{"title":"Design of a SoC Architecture for the Edge Computing of NILM Techniques","authors":"Álvaro Hernández, Rubén Nieto, David Fuentes, J. Ureña","doi":"10.1109/DCIS51330.2020.9268626","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268626","url":null,"abstract":"In recent years the development and deployment of commercial Smart Meters in most households in developed countries have spread the appearance of certain applications and methods, mainly related to the fields of Smart Grids and Internet of Things, where Non-Intrusive Load Monitoring (NILM) is one of the most well-known. It takes advantage of the capability of Smart Meters to acquire the electrical signals of a household or building in real time, in order to implement a set of techniques oriented to disaggregate the power consumption, according to the different electrical loads plugged in the facility. Previous works are often based on a cloud-computing approach, where samples are transferred straightforwardly from the local meter to the cloud for further analysis. This implies that the sampling rates are low in order to keep the required bandwidth reduced, thus constraining the final performance achieved in the load identification. This work presents the design of a System-on-Chip (SoC) architecture based on a Field-Programmable Gate Array (FPGA) device that can be installed locally at the input of the electrical installation from a house or building. It is able to manage data rates at high sampling frequencies and to implement in real time those algorithms proposed for the electrical signal processing and load classification. Experimental results have preliminary validated the proposed architecture.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130669684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A metamodel-based adaptive sampling approach for efficient failure region characterization of integrated circuits 基于元模型的自适应采样方法在集成电路失效区域的有效表征
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268659
Ingrid Kovacs, M. Topa, Monica Ene, Andi Buzo, G. Pelz
Adaptive verification appears to be an e client solution to overcome the coverage problem and to accurately characterize the failure region of high dimensional spaces at integrated circuits’ verification. Its main task is to gather more samples in the regions of interest based on the information learnt from previous samples. This helps engineers understand and interpret the behavior of the system under study with a reduced number of simulations/measurements compared to classical verification methods. To this end, we propose an adaptive sampling approach for the failure region characterization using the concept of metamodeling. Compared to other sampling methods for the failure region characterization, it has the advantage that it can detect and sample more in the near-failure region in the absence of a fail region. The concept has been applied on several synthetic test functions and on lab measurements of an analog integrated circuit. Results reveal that this adaptive sampling approach is very promising for failure region characterization.
自适应验证是克服集成电路验证中覆盖问题和准确表征高维空间失效区域的一种客户端解决方案。它的主要任务是基于从以前的样本中学习到的信息,在感兴趣的区域收集更多的样本。与经典验证方法相比,这有助于工程师通过减少模拟/测量次数来理解和解释所研究系统的行为。为此,我们提出了一种使用元建模概念的自适应采样方法来表征故障区域。与其它失效区域表征的采样方法相比,它的优点是在没有失效区域的情况下,可以在近失效区域进行更多的检测和采样。该概念已应用于几种综合测试功能和模拟集成电路的实验室测量。结果表明,这种自适应采样方法在故障区域表征中具有很好的应用前景。
{"title":"A metamodel-based adaptive sampling approach for efficient failure region characterization of integrated circuits","authors":"Ingrid Kovacs, M. Topa, Monica Ene, Andi Buzo, G. Pelz","doi":"10.1109/DCIS51330.2020.9268659","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268659","url":null,"abstract":"Adaptive verification appears to be an e client solution to overcome the coverage problem and to accurately characterize the failure region of high dimensional spaces at integrated circuits’ verification. Its main task is to gather more samples in the regions of interest based on the information learnt from previous samples. This helps engineers understand and interpret the behavior of the system under study with a reduced number of simulations/measurements compared to classical verification methods. To this end, we propose an adaptive sampling approach for the failure region characterization using the concept of metamodeling. Compared to other sampling methods for the failure region characterization, it has the advantage that it can detect and sample more in the near-failure region in the absence of a fail region. The concept has been applied on several synthetic test functions and on lab measurements of an analog integrated circuit. Results reveal that this adaptive sampling approach is very promising for failure region characterization.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133805429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Microarchitectural Isolation Guarantees Through Execution Based Signatures 通过基于执行的签名保证微架构隔离
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268660
Samira Briongos, P. Malagón, Jose M. Moya, T. Eisenbarth
Trusted Execution Environments (TEEs) aim to provide integrity and confidentiality guarantees to certain computations irrespective of the state of the rest of the system. That is, they protect Trusted Applications (TAs) even if the Operating System or the hypervisor are compromised. The TEE runs in parallel with the OS and leverages a set of hardware and software components to create such an isolated environment. However, this isolation can be broken by exploiting microarchitectural side-channels. The state of the shared components of multi-core processors depends on the actual processes being executed, and as a result, some information is leaked from one process to any other running in the same processor. This leakage completely breaks the confidentiality guarantees that TEEs promise. The only way to completely avoid the leakage is to avoid the share of resources, but this is nearly impossible to achieve without a huge degradation in the performance of the processor. Assuming that it is possible that the leakage exists, and the attacker only can get information from the observable microarchitectural state, we propose to monitor the hardware resources to detect the microarchitectural state changes caused by the attacks. To this end, we have implemented a hardware module that compares at runtime pre-stored microarchitectural execution signatures of each enclave, with the actual execution trace, and triggers an alarm when it detects significant variation.
可信执行环境(tee)旨在为某些计算提供完整性和机密性保证,而不管系统其余部分的状态如何。也就是说,即使操作系统或管理程序受到威胁,它们也可以保护受信任的应用程序(ta)。TEE与操作系统并行运行,并利用一组硬件和软件组件来创建这样一个隔离的环境。然而,这种隔离可以通过利用微体系结构侧通道来打破。多核处理器的共享组件的状态取决于正在执行的实际进程,因此,一些信息会从一个进程泄露给同一处理器中运行的任何其他进程。这种泄漏完全破坏了tee承诺的机密性保证。完全避免泄漏的唯一方法是避免资源共享,但这几乎不可能在处理器性能不大幅下降的情况下实现。假设可能存在泄漏,攻击者只能从可观察到的微体系结构状态中获取信息,我们提出对硬件资源进行监控,检测攻击引起的微体系结构状态变化。为此,我们实现了一个硬件模块,它可以在运行时将每个enclave预存储的微架构执行签名与实际执行跟踪进行比较,并在检测到显著变化时触发警报。
{"title":"Microarchitectural Isolation Guarantees Through Execution Based Signatures","authors":"Samira Briongos, P. Malagón, Jose M. Moya, T. Eisenbarth","doi":"10.1109/DCIS51330.2020.9268660","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268660","url":null,"abstract":"Trusted Execution Environments (TEEs) aim to provide integrity and confidentiality guarantees to certain computations irrespective of the state of the rest of the system. That is, they protect Trusted Applications (TAs) even if the Operating System or the hypervisor are compromised. The TEE runs in parallel with the OS and leverages a set of hardware and software components to create such an isolated environment. However, this isolation can be broken by exploiting microarchitectural side-channels. The state of the shared components of multi-core processors depends on the actual processes being executed, and as a result, some information is leaked from one process to any other running in the same processor. This leakage completely breaks the confidentiality guarantees that TEEs promise. The only way to completely avoid the leakage is to avoid the share of resources, but this is nearly impossible to achieve without a huge degradation in the performance of the processor. Assuming that it is possible that the leakage exists, and the attacker only can get information from the observable microarchitectural state, we propose to monitor the hardware resources to detect the microarchitectural state changes caused by the attacks. To this end, we have implemented a hardware module that compares at runtime pre-stored microarchitectural execution signatures of each enclave, with the actual execution trace, and triggers an alarm when it detects significant variation.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130112899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hyperspectral Imaging for Major Neurocognitive Disorder Detection in Plasma Samples 血浆样品中主要神经认知障碍检测的高光谱成像
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268625
Raquel León, Beatriz Martínez-Vega, H. Fabelo, S. Ortega, G. Callicó, Francisco Balea-Fernández, C. B. Sieyro
Neurocognitive disorders (NCD) affect over 50 million people globally. The detection biomarkers using brain imaging or cerebrospinal fluid are expensive procedures. Blood-based biomarkers such as plasma or serum present a cost-effective alternative. The work presented in this paper is focused on the use of hyperspectral (HS) imaging (HSI) to classify plasma samples in order to discriminate between patients with major NCD and healthy control subjects. HS images of plasma samples were obtained using a SWIR (Short-Wave Infrared) camera able to capture 273 bands within the 900-2,500 nm spectral range. A preliminary HSI database was obtained with 20 major NCD samples and 20 control samples. This data was segmented and classified using pixel-wise supervised classification algorithms, achieving 75% sensitivity and 100% specificity results with the best classifier in the test set.
神经认知障碍(NCD)影响着全球5000多万人。使用脑成像或脑脊液检测生物标志物是昂贵的程序。以血液为基础的生物标志物,如血浆或血清,是一种具有成本效益的替代方法。本文的工作重点是利用高光谱(HS)成像(HSI)对血浆样本进行分类,以区分非传染性疾病患者和健康对照者。等离子体样品的HS图像使用SWIR(短波红外)相机获得,该相机能够捕获900-2,500 nm光谱范围内的273个波段。初步建立了20个主要非传染性疾病样本和20个对照样本的HSI数据库。该数据使用逐像素监督分类算法进行分割和分类,使用测试集中最好的分类器获得75%的灵敏度和100%的特异性结果。
{"title":"Hyperspectral Imaging for Major Neurocognitive Disorder Detection in Plasma Samples","authors":"Raquel León, Beatriz Martínez-Vega, H. Fabelo, S. Ortega, G. Callicó, Francisco Balea-Fernández, C. B. Sieyro","doi":"10.1109/DCIS51330.2020.9268625","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268625","url":null,"abstract":"Neurocognitive disorders (NCD) affect over 50 million people globally. The detection biomarkers using brain imaging or cerebrospinal fluid are expensive procedures. Blood-based biomarkers such as plasma or serum present a cost-effective alternative. The work presented in this paper is focused on the use of hyperspectral (HS) imaging (HSI) to classify plasma samples in order to discriminate between patients with major NCD and healthy control subjects. HS images of plasma samples were obtained using a SWIR (Short-Wave Infrared) camera able to capture 273 bands within the 900-2,500 nm spectral range. A preliminary HSI database was obtained with 20 major NCD samples and 20 control samples. This data was segmented and classified using pixel-wise supervised classification algorithms, achieving 75% sensitivity and 100% specificity results with the best classifier in the test set.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"319 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133314845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Round-off noise estimation of fixed-point algorithms using Modified Affine Arithmetic and Legendre Polynomials 基于修正仿射算法和勒让德多项式的不动点算法的舍入噪声估计
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268668
Luis Esteban, J. A. Martín, A. Regadío
The implementation of algorithms in fixed-point format causes the apparition of Round-Off Noise which propagates through the different functional units of the system. This issue causes the Signal-to-Noise Ratio of the outputs is degraded. Given an algorithm, it is essential to estimate the integer and fractional bit-widths of all the variables and operations to comply with the Signal-to-Noise Ratio requirements. In this context, Affine Arithmetic can obtain fast and accurate estimations of the bit-widths for linear systems. However, for non-linear systems, Affine Arithmetic loses the temporal correlation of the variables. Other existing frameworks are either time consuming or lead to inaccurate bound estimations. In this paper, a Modified Affine Arithmetic framework with Legendre polynomials is used to obtain fast and accurate bound estimations also for non-linear systems. Moreover, the approach proposed in this paper obtains speedups in the range of 7 to 100 compared to Monte-Carlo simulations.
以定点格式实现算法会导致舍入噪声的出现,该噪声通过系统的不同功能单元传播。这个问题导致输出的信噪比降低。给定一个算法,估计所有变量和操作的整数和分数比特宽度以符合信噪比要求是至关重要的。在这种情况下,仿射算法可以快速准确地估计线性系统的比特宽度。然而,对于非线性系统,仿射算法失去了变量的时间相关性。其他现有框架要么耗时,要么导致不准确的边界估计。本文提出了一种带有勒让德多项式的改进仿射算法框架,用于非线性系统的快速准确的界估计。此外,与蒙特卡罗模拟相比,本文提出的方法获得了7到100的加速范围。
{"title":"Round-off noise estimation of fixed-point algorithms using Modified Affine Arithmetic and Legendre Polynomials","authors":"Luis Esteban, J. A. Martín, A. Regadío","doi":"10.1109/DCIS51330.2020.9268668","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268668","url":null,"abstract":"The implementation of algorithms in fixed-point format causes the apparition of Round-Off Noise which propagates through the different functional units of the system. This issue causes the Signal-to-Noise Ratio of the outputs is degraded. Given an algorithm, it is essential to estimate the integer and fractional bit-widths of all the variables and operations to comply with the Signal-to-Noise Ratio requirements. In this context, Affine Arithmetic can obtain fast and accurate estimations of the bit-widths for linear systems. However, for non-linear systems, Affine Arithmetic loses the temporal correlation of the variables. Other existing frameworks are either time consuming or lead to inaccurate bound estimations. In this paper, a Modified Affine Arithmetic framework with Legendre polynomials is used to obtain fast and accurate bound estimations also for non-linear systems. Moreover, the approach proposed in this paper obtains speedups in the range of 7 to 100 compared to Monte-Carlo simulations.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114780058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On Structured Design Space Exploration for Mapping of Quantum Algorithms 面向量子算法映射的结构化设计空间探索
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268670
Medina Bandic, Hossein Zarein, E. Alarcón, C. G. Almudever
Quantum algorithms can be expressed as quantum circuits when the circuit model of computation is adopted. Such a circuit description is usually hardware-agnostic, that is, it does not consider the limitations that the quantum hardware might have. In order to make quantum algorithms executable on quantum devices they need to comply to their constraints, which mainly affect the parallelism of quantum operations and the possible interactions between the qubits. The process of adapting a quantum circuit to meet the quantum chip restrictions is known as mapping. The resulting circuit usually has a higher number of gates and depth, decreasing the algorithm's reliability. Different mapping solutions have been already proposed. Most of them are meant for a specific quantum processor and differ in methodology, approach and features. In addition, they are usually only compared in terms of added gates, circuit depth and compilation time. No thorough comparative analysis of the different mapping solutions performance and features has been performed so far.In this paper, we propose to apply structured design space exploration (DSE) methodologies to the mapping procedures. This will allow not only to have a more in depth and structured analysis of their performance but also to identify what features are key and worth to implement. By using DSE we will be able to: i) determine in what regimes some mapping solutions outperform others; ii) derive optimal mapping strategies for specific quantum algorithms and quantum processors; and iii) perform an scalability analysis. In addition, DSE techniques cannot only be applied to the mapping layer that is key for bridging quantum applications to quantum devices, but also to the full-stack quantum computing system allowing for its crosslayer co-design.
采用计算电路模型时,量子算法可以表示为量子电路。这样的电路描述通常是与硬件无关的,也就是说,它不考虑量子硬件可能具有的限制。为了使量子算法在量子设备上可执行,它们需要遵守约束,这些约束主要影响量子运算的并行性和量子比特之间可能的相互作用。调整量子电路以满足量子芯片限制的过程被称为映射。得到的电路通常具有较高的门数和深度,降低了算法的可靠性。已经提出了不同的映射解决方案。它们中的大多数都适用于特定的量子处理器,并且在方法,方法和功能上有所不同。此外,它们通常只在增加的门数、电路深度和编译时间方面进行比较。到目前为止,还没有对不同映射解决方案的性能和特性进行彻底的比较分析。在本文中,我们建议将结构化设计空间探索(DSE)方法应用于映射过程。这不仅可以对它们的性能进行更深入和结构化的分析,还可以确定哪些功能是关键和值得实现的。通过使用DSE,我们将能够:i)确定在什么情况下一些映射解决方案优于其他解决方案;Ii)推导特定量子算法和量子处理器的最优映射策略;iii)执行可伸缩性分析。此外,DSE技术不仅可以应用于映射层,这是将量子应用桥接到量子器件的关键,还可以应用于允许其跨层协同设计的全堆栈量子计算系统。
{"title":"On Structured Design Space Exploration for Mapping of Quantum Algorithms","authors":"Medina Bandic, Hossein Zarein, E. Alarcón, C. G. Almudever","doi":"10.1109/DCIS51330.2020.9268670","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268670","url":null,"abstract":"Quantum algorithms can be expressed as quantum circuits when the circuit model of computation is adopted. Such a circuit description is usually hardware-agnostic, that is, it does not consider the limitations that the quantum hardware might have. In order to make quantum algorithms executable on quantum devices they need to comply to their constraints, which mainly affect the parallelism of quantum operations and the possible interactions between the qubits. The process of adapting a quantum circuit to meet the quantum chip restrictions is known as mapping. The resulting circuit usually has a higher number of gates and depth, decreasing the algorithm's reliability. Different mapping solutions have been already proposed. Most of them are meant for a specific quantum processor and differ in methodology, approach and features. In addition, they are usually only compared in terms of added gates, circuit depth and compilation time. No thorough comparative analysis of the different mapping solutions performance and features has been performed so far.In this paper, we propose to apply structured design space exploration (DSE) methodologies to the mapping procedures. This will allow not only to have a more in depth and structured analysis of their performance but also to identify what features are key and worth to implement. By using DSE we will be able to: i) determine in what regimes some mapping solutions outperform others; ii) derive optimal mapping strategies for specific quantum algorithms and quantum processors; and iii) perform an scalability analysis. In addition, DSE techniques cannot only be applied to the mapping layer that is key for bridging quantum applications to quantum devices, but also to the full-stack quantum computing system allowing for its crosslayer co-design.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"668 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122622249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
DCIS 2020 TOC
Pub Date : 2020-11-18 DOI: 10.1109/dcis51330.2020.9268657
{"title":"DCIS 2020 TOC","authors":"","doi":"10.1109/dcis51330.2020.9268657","DOIUrl":"https://doi.org/10.1109/dcis51330.2020.9268657","url":null,"abstract":"","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122244701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
期刊
2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)
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