Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268636
Rafael F. Santos, João Afonso, J. Monteiro
The analysis of input conditions that may cause a short-circuit in a logic circuit has recently become a critical issue, due to the potential presence of parasitic circuit elements after layout. This analysis is strongly related to the problem of determining paths in a graph whose edges are defined by related logic functions. Logic circuits can be modeled as a generic graph, where edges are a logic function of static input variable combinations, representing transistors that act like logic switches. The solution to this problem must address a complex SAT-problem involving an extensive inspection of all possible paths between two nodes, the power supply and ground. We describe an efficient method, based on a Quantified Boolean Formula (QBF) model, that solves this problem in an incremental way. We propose a parallel implementation for multi-core shared-memory machines. The Espresso logic minimization tool was critical to keep the size of the intermediate logic functions manageable. In order to be able to use this tool in parallel, we developed a thread-safe version of Espresso and have made it available to the community. The proposed solution was validated against a set of benchmarks that show the effectiveness of our parallel implementation, allowing to address instances of transistor-level circuits for a wide range of inputs and internal nodes efficiently.
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Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268620
A. Astarloa, Mikel Rodríguez, F. Durán, J. Jiménez, Jesús Lázaro
Because of its reliability demands, Industry has not previously trusted in commercial Ethernet for data communication, despite being the cheapest option and the de facto standard. Nevertheless, during the last years, some technological innovations have enhanced its safety and predictability so much, that Ethernet has turned into the industrial network. Critical sectors, such as Electric Power, with high-availability and strict timing requirement, have taken advantage of these developments, after having driven them.To allow some other crucial applications to get benefit from these innovations, the next step is providing system integrators with validated and compatible equipment. For this purpose, our paper presents a Smart PCIe card that delivers a common main clock throughout the industrial data network. Our design supports zero-delay recovery sub-standards (HSR and PRP), and autonomously manages Precise-Time-Protocol (PTP or IEEE 1588), for accurate synchronization over Ethernet. Besides, the board integrates a clock protocol gateway, so that legacy systems, not compatible with the PTP reference, can be synchronously attached. As an example, the presented use-case synchronizes a SCADA system by taking the time reference from the Windows Operating system that is synchronized using the native Network Time Protocol (NTP) slave. This clock is provided by the NTP master embedded in the PCIe card.
{"title":"Synchronizing NTP Referenced SCADA Systems Interconnected by High-availability Networks","authors":"A. Astarloa, Mikel Rodríguez, F. Durán, J. Jiménez, Jesús Lázaro","doi":"10.1109/DCIS51330.2020.9268620","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268620","url":null,"abstract":"Because of its reliability demands, Industry has not previously trusted in commercial Ethernet for data communication, despite being the cheapest option and the de facto standard. Nevertheless, during the last years, some technological innovations have enhanced its safety and predictability so much, that Ethernet has turned into the industrial network. Critical sectors, such as Electric Power, with high-availability and strict timing requirement, have taken advantage of these developments, after having driven them.To allow some other crucial applications to get benefit from these innovations, the next step is providing system integrators with validated and compatible equipment. For this purpose, our paper presents a Smart PCIe card that delivers a common main clock throughout the industrial data network. Our design supports zero-delay recovery sub-standards (HSR and PRP), and autonomously manages Precise-Time-Protocol (PTP or IEEE 1588), for accurate synchronization over Ethernet. Besides, the board integrates a clock protocol gateway, so that legacy systems, not compatible with the PTP reference, can be synchronously attached. As an example, the presented use-case synchronizes a SCADA system by taking the time reference from the Windows Operating system that is synchronized using the native Network Time Protocol (NTP) slave. This clock is provided by the NTP master embedded in the PCIe card.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"610 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125332694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/dcis51330.2020.9268656
{"title":"DCIS 2020 Subject Index Page","authors":"","doi":"10.1109/dcis51330.2020.9268656","DOIUrl":"https://doi.org/10.1109/dcis51330.2020.9268656","url":null,"abstract":"","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126448900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-18DOI: 10.1109/DCIS51330.2020.9268619
M. Montón, Xavier Salazar
This document explains the basic concepts related to software and hardware licenses, and it summarizes the most popular licenses that are currently used for hardware projects. Two case studies of hardware projects at different levels of abstraction are also presented, together with a discussion of license applicability, commercial issues, code protection, and related concerns.This paper intends to help the reader understand how to release open hardware with the most appropriate license, and to answer questions that are of current interest. We have been mainly motivated by the growing influence of the open RISC-V ISA, but trying to address a wider hardware point of view.
{"title":"On licenses for [Open] Hardware","authors":"M. Montón, Xavier Salazar","doi":"10.1109/DCIS51330.2020.9268619","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268619","url":null,"abstract":"This document explains the basic concepts related to software and hardware licenses, and it summarizes the most popular licenses that are currently used for hardware projects. Two case studies of hardware projects at different levels of abstraction are also presented, together with a discussion of license applicability, commercial issues, code protection, and related concerns.This paper intends to help the reader understand how to release open hardware with the most appropriate license, and to answer questions that are of current interest. We have been mainly motivated by the growing influence of the open RISC-V ISA, but trying to address a wider hardware point of view.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127255442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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