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2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)最新文献

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Short-circuit Analysis using a Parallel QBF Solver 基于并行QBF求解器的短路分析
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268636
Rafael F. Santos, João Afonso, J. Monteiro
The analysis of input conditions that may cause a short-circuit in a logic circuit has recently become a critical issue, due to the potential presence of parasitic circuit elements after layout. This analysis is strongly related to the problem of determining paths in a graph whose edges are defined by related logic functions. Logic circuits can be modeled as a generic graph, where edges are a logic function of static input variable combinations, representing transistors that act like logic switches. The solution to this problem must address a complex SAT-problem involving an extensive inspection of all possible paths between two nodes, the power supply and ground. We describe an efficient method, based on a Quantified Boolean Formula (QBF) model, that solves this problem in an incremental way. We propose a parallel implementation for multi-core shared-memory machines. The Espresso logic minimization tool was critical to keep the size of the intermediate logic functions manageable. In order to be able to use this tool in parallel, we developed a thread-safe version of Espresso and have made it available to the community. The proposed solution was validated against a set of benchmarks that show the effectiveness of our parallel implementation, allowing to address instances of transistor-level circuits for a wide range of inputs and internal nodes efficiently.
由于布局后可能存在寄生电路元件,因此分析可能导致逻辑电路短路的输入条件已成为一个关键问题。这种分析与图中路径的确定问题密切相关,图的边是由相关逻辑函数定义的。逻辑电路可以建模为一个通用图,其中边是静态输入变量组合的逻辑函数,表示充当逻辑开关的晶体管。这个问题的解决方案必须解决一个复杂的sat问题,包括对两个节点,电源和地之间所有可能的路径进行广泛的检查。本文描述了一种基于量化布尔公式(QBF)模型的有效方法,以增量的方式解决了这一问题。我们提出了一种多核共享内存机器的并行实现。Espresso逻辑最小化工具对于保持中间逻辑功能的可管理大小至关重要。为了能够并行使用这个工具,我们开发了一个线程安全的Espresso版本,并将其提供给社区。针对一组基准测试验证了所提出的解决方案,这些基准测试显示了我们并行实现的有效性,允许有效地解决晶体管级电路的实例,用于广泛的输入和内部节点。
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引用次数: 0
Synchronizing NTP Referenced SCADA Systems Interconnected by High-availability Networks 同步NTP引用SCADA系统通过高可用性网络互联
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268620
A. Astarloa, Mikel Rodríguez, F. Durán, J. Jiménez, Jesús Lázaro
Because of its reliability demands, Industry has not previously trusted in commercial Ethernet for data communication, despite being the cheapest option and the de facto standard. Nevertheless, during the last years, some technological innovations have enhanced its safety and predictability so much, that Ethernet has turned into the industrial network. Critical sectors, such as Electric Power, with high-availability and strict timing requirement, have taken advantage of these developments, after having driven them.To allow some other crucial applications to get benefit from these innovations, the next step is providing system integrators with validated and compatible equipment. For this purpose, our paper presents a Smart PCIe card that delivers a common main clock throughout the industrial data network. Our design supports zero-delay recovery sub-standards (HSR and PRP), and autonomously manages Precise-Time-Protocol (PTP or IEEE 1588), for accurate synchronization over Ethernet. Besides, the board integrates a clock protocol gateway, so that legacy systems, not compatible with the PTP reference, can be synchronously attached. As an example, the presented use-case synchronizes a SCADA system by taking the time reference from the Windows Operating system that is synchronized using the native Network Time Protocol (NTP) slave. This clock is provided by the NTP master embedded in the PCIe card.
由于其可靠性要求,工业界以前不相信商业以太网用于数据通信,尽管它是最便宜的选择和事实上的标准。然而,在过去的几年里,一些技术创新大大提高了它的安全性和可预测性,以太网已经变成了工业网络。电力等具有高可用性和严格时间要求的关键部门,在推动了这些发展之后,已经利用了这些发展。为了让其他关键应用从这些创新中受益,下一步是为系统集成商提供经过验证的兼容设备。为此,我们的论文提出了一种智能PCIe卡,它在整个工业数据网络中提供一个公共主时钟。我们的设计支持零延迟恢复子标准(HSR和PRP),并自主管理精确时间协议(PTP或IEEE 1588),实现以太网上的精确同步。此外,该板还集成了时钟协议网关,可以同步连接不兼容PTP参考的遗留系统。作为一个示例,本文给出的用例通过使用本地网络时间协议(NTP)从站同步Windows操作系统的时间引用来同步SCADA系统。该时钟由嵌入在PCIe卡中的NTP主时钟提供。
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引用次数: 1
DCIS 2020 Subject Index Page DCIS 2020主题索引页
Pub Date : 2020-11-18 DOI: 10.1109/dcis51330.2020.9268656
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引用次数: 0
On licenses for [Open] Hardware 关于[开放]硬件的许可
Pub Date : 2020-10-18 DOI: 10.1109/DCIS51330.2020.9268619
M. Montón, Xavier Salazar
This document explains the basic concepts related to software and hardware licenses, and it summarizes the most popular licenses that are currently used for hardware projects. Two case studies of hardware projects at different levels of abstraction are also presented, together with a discussion of license applicability, commercial issues, code protection, and related concerns.This paper intends to help the reader understand how to release open hardware with the most appropriate license, and to answer questions that are of current interest. We have been mainly motivated by the growing influence of the open RISC-V ISA, but trying to address a wider hardware point of view.
本文档介绍了软件和硬件许可证的基本概念,并总结了当前硬件项目中最常用的许可证。本文还介绍了不同抽象层次上硬件项目的两个案例研究,并讨论了许可证的适用性、商业问题、代码保护和相关问题。本文旨在帮助读者理解如何使用最合适的许可证发布开放硬件,并回答当前感兴趣的问题。我们主要受到开放RISC-V ISA日益增长的影响力的推动,但试图解决更广泛的硬件观点。
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引用次数: 1
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2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)
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