首页 > 最新文献

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)最新文献

英文 中文
DCIS 2020 Index DCIS 2020指数
Pub Date : 2020-11-18 DOI: 10.1109/dcis51330.2020.9268651
{"title":"DCIS 2020 Index","authors":"","doi":"10.1109/dcis51330.2020.9268651","DOIUrl":"https://doi.org/10.1109/dcis51330.2020.9268651","url":null,"abstract":"","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133499556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Autonomous self-powered potentiostat architecture for biomedical wearable applications. 用于生物医学可穿戴应用的自主自供电电位器架构。
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268667
Javier Aguilar, Albert Álvarez-Carulla, Valeria Colmena, Oscar Carreras, Genis Rabost, M. Puig-Vidal, J. Colomer-Farrarons, Xavier Muñoz, P. Miribel-Català, J. Punter-Villagrasa
In this work, we present an architecture of an envisaged autonomous self-powered potentiostat for biomedical wearable applications. This architecture has been conceived as a versatile and compact analog front-end for electrochemical disposable sensors, specifically as a key component of a wearable non-invasive biomedical device. This architecture is composed by a custom made three electrode potentiostat, a power management circuit for power regulation and to generate the bias voltage needed for proper electrochemical sensor operation, and finally an energy harvesting circuit for power generation. Initial characterization and validation of the potentiostat amplifier demonstrates good resolution, linearity and range, operating at ± 1.5V (450μW), being able to operate as an autonomous unit while being highly customizable for different electrochemical sensors.
在这项工作中,我们提出了一种设想的用于生物医学可穿戴应用的自主自供电电位器架构。该架构被认为是电化学一次性传感器的多功能和紧凑的模拟前端,特别是作为可穿戴非侵入性生物医学设备的关键组件。该结构由一个定制的三电极恒电位器、一个用于功率调节和产生适当电化学传感器工作所需的偏置电压的电源管理电路以及一个用于发电的能量收集电路组成。初步表征和验证表明,恒电位器放大器具有良好的分辨率、线性度和工作范围,工作电压为±1.5V (450μW),能够作为一个独立的单元工作,同时可高度定制不同的电化学传感器。
{"title":"Autonomous self-powered potentiostat architecture for biomedical wearable applications.","authors":"Javier Aguilar, Albert Álvarez-Carulla, Valeria Colmena, Oscar Carreras, Genis Rabost, M. Puig-Vidal, J. Colomer-Farrarons, Xavier Muñoz, P. Miribel-Català, J. Punter-Villagrasa","doi":"10.1109/DCIS51330.2020.9268667","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268667","url":null,"abstract":"In this work, we present an architecture of an envisaged autonomous self-powered potentiostat for biomedical wearable applications. This architecture has been conceived as a versatile and compact analog front-end for electrochemical disposable sensors, specifically as a key component of a wearable non-invasive biomedical device. This architecture is composed by a custom made three electrode potentiostat, a power management circuit for power regulation and to generate the bias voltage needed for proper electrochemical sensor operation, and finally an energy harvesting circuit for power generation. Initial characterization and validation of the potentiostat amplifier demonstrates good resolution, linearity and range, operating at ± 1.5V (450μW), being able to operate as an autonomous unit while being highly customizable for different electrochemical sensors.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130124834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysing the interference of Xen hypervisor in the network speed 分析Xen hypervisor对网络速度的干扰
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268648
Sara Alonso, Jesús Lázaro, J. Jiménez, L. Muguira, Alejandro Largacha
The use of hypervisors is constantly growing on account of their benefits. For some applications with hard realtime constraints, it is interesting to analyze the speed reduction that could cause. MPSoC boards are suitable for the use of hypervisors thanks to having an FPGA which allows the user to design the hardware and Cortex A53 cores, with armv8 architecture, which have virtualization extensions. The board has been validated with Xen hypervisor. This paper compares five scenarios to characterize the impact of the hypervisor layer on the speed of a network connection: a standalone application, Petalinux directly running on hardware, Petalinux running in Xen Dom0, Petalinux running in Xen DomU paravirtualizing the network and a Petalinux running in Xen DomU pass-throughing the network. It also characterizes the delay of the network connection in some scenarios as a complementary measurement. All the cases are implemented in the Zynq ZCU102 board. It is shown that a Xen hypervisor layer creates a considerable reduction in network speed. Provided that the network is settled down in passthrough mode, the network speed in DomU is almost the same as if there was no hypervisor.
管理程序的使用由于其优点而不断增长。对于一些具有硬实时约束的应用程序,分析可能导致的速度降低是很有趣的。MPSoC板适合使用虚拟机管理程序,因为它有一个FPGA,允许用户设计硬件和Cortex A53内核,具有armv8架构,具有虚拟化扩展。已通过Xen hypervisor的验证。本文比较了五种场景,以描述管理程序层对网络连接速度的影响:独立应用程序、直接在硬件上运行的Petalinux、在Xen Dom0中运行的Petalinux、在Xen DomU中运行的准虚拟化网络以及在Xen DomU中运行的Petalinux通过网络。在某些情况下,它还表征了网络连接的延迟,作为一种补充测量。所有的案例都在Zynq ZCU102板上实现。结果表明,Xen管理程序层大大降低了网络速度。如果网络以直通模式设置,那么DomU中的网络速度几乎与没有管理程序时相同。
{"title":"Analysing the interference of Xen hypervisor in the network speed","authors":"Sara Alonso, Jesús Lázaro, J. Jiménez, L. Muguira, Alejandro Largacha","doi":"10.1109/DCIS51330.2020.9268648","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268648","url":null,"abstract":"The use of hypervisors is constantly growing on account of their benefits. For some applications with hard realtime constraints, it is interesting to analyze the speed reduction that could cause. MPSoC boards are suitable for the use of hypervisors thanks to having an FPGA which allows the user to design the hardware and Cortex A53 cores, with armv8 architecture, which have virtualization extensions. The board has been validated with Xen hypervisor. This paper compares five scenarios to characterize the impact of the hypervisor layer on the speed of a network connection: a standalone application, Petalinux directly running on hardware, Petalinux running in Xen Dom0, Petalinux running in Xen DomU paravirtualizing the network and a Petalinux running in Xen DomU pass-throughing the network. It also characterizes the delay of the network connection in some scenarios as a complementary measurement. All the cases are implemented in the Zynq ZCU102 board. It is shown that a Xen hypervisor layer creates a considerable reduction in network speed. Provided that the network is settled down in passthrough mode, the network speed in DomU is almost the same as if there was no hypervisor.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117071503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FrailWear: A Wearable IoT Device for Daily Activity Monitoring of Elderly Patients frrailwear:一种用于老年患者日常活动监测的可穿戴物联网设备
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268629
Sergio Lluva Plaza, J. M. V. Carrizo, Juan Jesús García Domínguez, Ana Jiménez Martín, David Gualda Gómez
This paper introduces an IoT wearable, specifically designed for the analysis of the physical activity of elderly people, in order to provide objective information to the healthcare staff to assess the frailty in these patients. The device, called FrailWear, is based on a STM32 low cost, low power and high-performance microcontroller. It is a multisensory system that includes an IMU and atmospheric pressure sensor for collecting data. In addition, it is possible to obtain the centimetric-accuracy position of the patient, if the infrastructure includes an external ultrasonic local positioning system. The wearable also includes a LoRaWAN based architecture, to communicate the system and the cloud, where the acquired data will be stored for a later analysis. Both physical activity and localization information are obtained, able to be analysed in real time or to be requested on demand by the carers. First test results of FrailWear are very promising and show its feasibility for this application.
本文介绍了一种物联网可穿戴设备,专门用于分析老年人的身体活动,为医护人员提供客观的信息来评估这些患者的虚弱程度。该设备名为frrailwear,基于STM32低成本、低功耗和高性能微控制器。它是一个多传感器系统,包括一个IMU和用于收集数据的大气压力传感器。此外,如果基础设施包括外部超声局部定位系统,则可以获得患者的厘米精度位置。可穿戴设备还包括一个基于LoRaWAN的架构,用于系统和云之间的通信,获取的数据将存储在云上,供以后分析使用。获得身体活动和定位信息,能够实时分析或根据护理人员的需要提出要求。FrailWear的初步测试结果非常有希望,并显示了其在该应用中的可行性。
{"title":"FrailWear: A Wearable IoT Device for Daily Activity Monitoring of Elderly Patients","authors":"Sergio Lluva Plaza, J. M. V. Carrizo, Juan Jesús García Domínguez, Ana Jiménez Martín, David Gualda Gómez","doi":"10.1109/DCIS51330.2020.9268629","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268629","url":null,"abstract":"This paper introduces an IoT wearable, specifically designed for the analysis of the physical activity of elderly people, in order to provide objective information to the healthcare staff to assess the frailty in these patients. The device, called FrailWear, is based on a STM32 low cost, low power and high-performance microcontroller. It is a multisensory system that includes an IMU and atmospheric pressure sensor for collecting data. In addition, it is possible to obtain the centimetric-accuracy position of the patient, if the infrastructure includes an external ultrasonic local positioning system. The wearable also includes a LoRaWAN based architecture, to communicate the system and the cloud, where the acquired data will be stored for a later analysis. Both physical activity and localization information are obtained, able to be analysed in real time or to be requested on demand by the carers. First test results of FrailWear are very promising and show its feasibility for this application.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117123405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hyperspectral Images Acquisition: an Efficient Capture and Processing Stitching Procedure for Medical Environments 高光谱图像采集:用于医疗环境的高效捕获和处理拼接程序
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268658
Gonzalo Rosa, Marta Villanueva, Jaime Sancho, Gemma Urbanos, Luisa Ruiz, M. Villa, Alberto Martín, E. Juárez, Luis Jiménez, M. Chavarrías, Alfonso Lagares, C. Sanz
The complexity of the Hyperspectral (HS) imaging-based applications demands faster and more efficient acquisition and processing systems. Moreover, HSI technology is being more and more used within the medical imaging field, increasing and making more restrictive the requirements of the implementations. In this work, the authors present an efficient methodology for the acquisition and stitching processes when capturing line-scan based HS images. In order to verify the proposed methodology, a full hardware and software setup has been implemented. The proposed method has been tested scanning a reference polymer at different working distances and scroll speeds. The obtained results in laboratory show that the delta in PSNR keeps below 5% for all cases. Also, the correlation between comparable spectral signatures are not affected neither by the working distance nor by the acquisition speed.
基于高光谱(HS)成像应用的复杂性要求更快、更高效的采集和处理系统。此外,HSI技术越来越多地应用于医学成像领域,增加并限制了实现的要求。在这项工作中,作者提出了一种有效的方法,用于捕获基于线扫描的HS图像时的采集和拼接过程。为了验证所提出的方法,已经实现了完整的硬件和软件设置。在不同的工作距离和滚动速度下,对所提出的方法进行了测试。实验结果表明,在所有情况下,PSNR的δ都保持在5%以下。此外,可比较的光谱特征之间的相关性不受工作距离和采集速度的影响。
{"title":"Hyperspectral Images Acquisition: an Efficient Capture and Processing Stitching Procedure for Medical Environments","authors":"Gonzalo Rosa, Marta Villanueva, Jaime Sancho, Gemma Urbanos, Luisa Ruiz, M. Villa, Alberto Martín, E. Juárez, Luis Jiménez, M. Chavarrías, Alfonso Lagares, C. Sanz","doi":"10.1109/DCIS51330.2020.9268658","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268658","url":null,"abstract":"The complexity of the Hyperspectral (HS) imaging-based applications demands faster and more efficient acquisition and processing systems. Moreover, HSI technology is being more and more used within the medical imaging field, increasing and making more restrictive the requirements of the implementations. In this work, the authors present an efficient methodology for the acquisition and stitching processes when capturing line-scan based HS images. In order to verify the proposed methodology, a full hardware and software setup has been implemented. The proposed method has been tested scanning a reference polymer at different working distances and scroll speeds. The obtained results in laboratory show that the delta in PSNR keeps below 5% for all cases. Also, the correlation between comparable spectral signatures are not affected neither by the working distance nor by the acquisition speed.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115361078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
RISC-V processors design: a methodology for cores development RISC-V处理器设计:一种核心开发方法
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268639
A. Barriga
This communication describes a design methodology that facilitates the implementation of processors based on the ISA of RISC-V. As an example of application of the proposed methodology, the design of three processors with different architectures and features is described.
本通信描述了一种便于基于RISC-V的ISA实现处理器的设计方法。作为应用该方法的一个例子,描述了具有不同架构和特性的三种处理器的设计。
{"title":"RISC-V processors design: a methodology for cores development","authors":"A. Barriga","doi":"10.1109/DCIS51330.2020.9268639","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268639","url":null,"abstract":"This communication describes a design methodology that facilitates the implementation of processors based on the ISA of RISC-V. As an example of application of the proposed methodology, the design of three processors with different architectures and features is described.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"104 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114048163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Hardware-Accelerated Qubit Control System for Quantum Information Processing 量子信息处理的硬件加速量子比特控制系统
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268643
N. Messaoudi, C. Crocker, M. Almendros
In this paper we present a flexible, highperformance, integrated qubit control system using modular PXIe equipment. To manipulate qubits, a classical control system is required to generate and acquire a mix of baseband, radio frequency, and/or optical signals, with the specific mix different for each qubit technology. Typically, a quantum system requires many of these signals with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. The proposed system is scalable to hundreds of channels, all of them being phase coherent and fully time-synchronized.The system includes a programmable real-time sequencer for precise execution timing and decision making; and open FPGA capabilities for custom Digital Signal Processing (DSP) by hardware. Using the latter, we present FPGA IP to generate one-/two-qubit gates efficiently with the AWG, and to analyze high-frequency signals to measure the qubit states in real time on the digitizers. This IP features very low latencies for Quantum Error Correction (QEC) and Frequency Division Multiplexing (FDM) capabilities, among others.
在本文中,我们提出了一个灵活的,高性能的集成量子比特控制系统,使用模块化PXIe设备。为了操纵量子比特,需要一个经典的控制系统来生成和获取基带、射频和/或光学信号的混合,每种量子比特技术的具体混合是不同的。通常,量子系统需要许多具有高度同步和相位相干性的信号,并且越来越需要实时数据处理和实时排序能力来进行反馈实验。该系统可扩展到数百个通道,所有通道都是相位相干和完全时间同步的。该系统包括一个可编程的实时序列器,用于精确的执行时序和决策;和开放的FPGA功能,可通过硬件定制数字信号处理(DSP)。对于后者,我们提出了FPGA IP,利用AWG高效地生成一个/两个量子比特的门,并分析高频信号,实时测量数字化仪上的量子比特状态。该IP在量子纠错(QEC)和频分复用(FDM)功能等方面具有非常低的延迟。
{"title":"A Hardware-Accelerated Qubit Control System for Quantum Information Processing","authors":"N. Messaoudi, C. Crocker, M. Almendros","doi":"10.1109/DCIS51330.2020.9268643","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268643","url":null,"abstract":"In this paper we present a flexible, highperformance, integrated qubit control system using modular PXIe equipment. To manipulate qubits, a classical control system is required to generate and acquire a mix of baseband, radio frequency, and/or optical signals, with the specific mix different for each qubit technology. Typically, a quantum system requires many of these signals with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. The proposed system is scalable to hundreds of channels, all of them being phase coherent and fully time-synchronized.The system includes a programmable real-time sequencer for precise execution timing and decision making; and open FPGA capabilities for custom Digital Signal Processing (DSP) by hardware. Using the latter, we present FPGA IP to generate one-/two-qubit gates efficiently with the AWG, and to analyze high-frequency signals to measure the qubit states in real time on the digitizers. This IP features very low latencies for Quantum Error Correction (QEC) and Frequency Division Multiplexing (FDM) capabilities, among others.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114970786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and Characterization of Non-planar 3D-printed Passive UHF-RFID Tag 非平面3d打印无源超高频rfid标签的设计与表征
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268666
N. Vidal, Arnau Salas Barenys, Aleix Garcia, J. Romeu, Giselle González, L. Jofre, J. López-Villegas
This paper presents the design and preliminary characterization of a novel 3D passive UHF-RFID tag. The prototype is fabricated using additive manufacturing techniques: 3D printing and copper electroplating. The design, manufacturing process and measurement set-up are presented and discussed in detail. We propose a biconical antenna design with helical strips in the cones to provide compactness without breaking the symmetry of the component and to improve bandwidth. The antenna is matched to a commercial UHF-RFID integrated circuit. The good agreement between results and simulations allows us to validate the whole process.
本文介绍了一种新型三维无源超高频射频标签的设计和初步表征。原型是使用增材制造技术制造的:3D打印和镀铜。详细介绍了该系统的设计、制造过程和测量装置。我们提出了一种锥形螺旋带天线设计,在不破坏组件对称性的情况下提供紧凑性并提高带宽。天线与商用超高频射频识别集成电路相匹配。结果与模拟结果吻合良好,使我们能够对整个过程进行验证。
{"title":"Design and Characterization of Non-planar 3D-printed Passive UHF-RFID Tag","authors":"N. Vidal, Arnau Salas Barenys, Aleix Garcia, J. Romeu, Giselle González, L. Jofre, J. López-Villegas","doi":"10.1109/DCIS51330.2020.9268666","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268666","url":null,"abstract":"This paper presents the design and preliminary characterization of a novel 3D passive UHF-RFID tag. The prototype is fabricated using additive manufacturing techniques: 3D printing and copper electroplating. The design, manufacturing process and measurement set-up are presented and discussed in detail. We propose a biconical antenna design with helical strips in the cones to provide compactness without breaking the symmetry of the component and to improve bandwidth. The antenna is matched to a commercial UHF-RFID integrated circuit. The good agreement between results and simulations allows us to validate the whole process.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127739093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Selection of SRAM Cells to improve Reliable PUF implementation using Cell Mismatch Metric 使用单元失配度量来选择SRAM单元以提高可靠的PUF实现
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268669
A. Alheyasat, G. Torrens, S. Bota, B. Alorda
Physically Unclonable Functions (PUFs) are low-cost cryptographic primitives implemented in secret key generation and device authentication strategies. SRAM-PUFs are widely well-known as entropy source; however, they mainly experience a low reproducibility of the challenge-response pair because of non-deterministic noise conditions during the process of power-up. The reliability of SRAM-PUFs achieved these days comes by using complex error correcting codes (ECCs) combined with Fuzzy extractor structures introducing an increment in terms of power consumption, area cost and complexity of the design. In this paper we define an effective metric to classify the SRAM cells identifying the most reliable cells generating high reproductible responses for the PUF implementation and, identifying the most unpredictable ones for Random Number Generator (RNG). This metric is obtained from the mismatch between the cell’s inverters and the start-up behavior. Also, the noise in the PUF is modeled to validate the classification results obtained by the proposed metric. The proposed metric can be used during SRAM PUF design to explore the impact on reliable cells significantly increasing the reproducibility of the PUF and minimizing the dependability on ECCs and Fuzzy extractor.
物理不可克隆函数(puf)是在密钥生成和设备身份验证策略中实现的低成本加密原语。SRAM-PUFs是众所周知的熵源;然而,由于在上电过程中存在不确定的噪声条件,它们的挑战-响应对的再现性较低。目前,sram - puf的可靠性是通过使用复杂的纠错码(ecc)和模糊提取器结构来实现的,这在功耗、面积成本和设计复杂性方面带来了增加。在本文中,我们定义了一个有效的度量来对SRAM单元进行分类,识别最可靠的单元,为PUF实现产生高可重复性响应,并识别最不可预测的随机数生成器(RNG)。该指标是由电池逆变器和启动行为之间的不匹配获得的。此外,还对PUF中的噪声进行了建模,以验证所提出度量所获得的分类结果。该指标可用于SRAM PUF设计,以探索对可靠细胞的影响,显著提高PUF的可重复性,并最大限度地降低对ECCs和模糊提取器的可靠性。
{"title":"Selection of SRAM Cells to improve Reliable PUF implementation using Cell Mismatch Metric","authors":"A. Alheyasat, G. Torrens, S. Bota, B. Alorda","doi":"10.1109/DCIS51330.2020.9268669","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268669","url":null,"abstract":"Physically Unclonable Functions (PUFs) are low-cost cryptographic primitives implemented in secret key generation and device authentication strategies. SRAM-PUFs are widely well-known as entropy source; however, they mainly experience a low reproducibility of the challenge-response pair because of non-deterministic noise conditions during the process of power-up. The reliability of SRAM-PUFs achieved these days comes by using complex error correcting codes (ECCs) combined with Fuzzy extractor structures introducing an increment in terms of power consumption, area cost and complexity of the design. In this paper we define an effective metric to classify the SRAM cells identifying the most reliable cells generating high reproductible responses for the PUF implementation and, identifying the most unpredictable ones for Random Number Generator (RNG). This metric is obtained from the mismatch between the cell’s inverters and the start-up behavior. Also, the noise in the PUF is modeled to validate the classification results obtained by the proposed metric. The proposed metric can be used during SRAM PUF design to explore the impact on reliable cells significantly increasing the reproducibility of the PUF and minimizing the dependability on ECCs and Fuzzy extractor.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"49 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120885619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
DAC mismatch shaping in Discrete Time Sigma Delta ADCs with non uniform quantizer 带非均匀量化器的离散时间σ δ adc的DAC失配整形
Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268615
Pablo Vera, S. Patón
Discrete time Σ∆ modulators habitually use a multi-level uniform quantizer (UQ); with this type of quantizer the maximum resolution is reached around full scale and system stability is improved. In this work, we propose the use of a multi-level non uniform quantizer (NUQ) to improve resolution for low input amplitude signals. The proposed architecture is compared with a uniform quantizer, and the effect of feedback DAC mismatch is analyzed. Different DAC mismatch shaping techniques are tested to compare their effects on SNR and SFDR, focusing on rotational element selection and Bi-DWA. Simulations are performed with MATLAB using behavioral modeled blocks. Results indicate that DAC mismatch produces a noticeable SNR degradation in converters with non uniform quantizer; DAC mismatch shaping methods are compared, rotational element selection being better in terms of SNR and Bi-DWA is better in terms of SFDR.
离散时间Σ∆调制器习惯使用多级均匀量化器(UQ);使用这种类型的量化器可以在满量程附近达到最大分辨率,并且提高了系统的稳定性。在这项工作中,我们提出使用多级非均匀量化器(NUQ)来提高低输入幅度信号的分辨率。将该结构与均匀量化器进行了比较,并分析了反馈DAC失配的影响。测试了不同的DAC失配整形技术,比较了它们对信噪比和SFDR的影响,重点是旋转元件选择和Bi-DWA。在MATLAB中使用行为建模模块进行仿真。结果表明,在非均匀量化器的变换器中,DAC失配会产生明显的信噪比下降;比较了DAC失配整形方法,旋转元件选择在信噪比方面更好,Bi-DWA在SFDR方面更好。
{"title":"DAC mismatch shaping in Discrete Time Sigma Delta ADCs with non uniform quantizer","authors":"Pablo Vera, S. Patón","doi":"10.1109/DCIS51330.2020.9268615","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268615","url":null,"abstract":"Discrete time Σ∆ modulators habitually use a multi-level uniform quantizer (UQ); with this type of quantizer the maximum resolution is reached around full scale and system stability is improved. In this work, we propose the use of a multi-level non uniform quantizer (NUQ) to improve resolution for low input amplitude signals. The proposed architecture is compared with a uniform quantizer, and the effect of feedback DAC mismatch is analyzed. Different DAC mismatch shaping techniques are tested to compare their effects on SNR and SFDR, focusing on rotational element selection and Bi-DWA. Simulations are performed with MATLAB using behavioral modeled blocks. Results indicate that DAC mismatch produces a noticeable SNR degradation in converters with non uniform quantizer; DAC mismatch shaping methods are compared, rotational element selection being better in terms of SNR and Bi-DWA is better in terms of SFDR.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120985454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
期刊
2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)
全部 Acc. Chem. Res. ACS Applied Bio Materials ACS Appl. Electron. Mater. ACS Appl. Energy Mater. ACS Appl. Mater. Interfaces ACS Appl. Nano Mater. ACS Appl. Polym. Mater. ACS BIOMATER-SCI ENG ACS Catal. ACS Cent. Sci. ACS Chem. Biol. ACS Chemical Health & Safety ACS Chem. Neurosci. ACS Comb. Sci. ACS Earth Space Chem. ACS Energy Lett. ACS Infect. Dis. ACS Macro Lett. ACS Mater. Lett. ACS Med. Chem. Lett. ACS Nano ACS Omega ACS Photonics ACS Sens. ACS Sustainable Chem. Eng. ACS Synth. Biol. Anal. Chem. BIOCHEMISTRY-US Bioconjugate Chem. BIOMACROMOLECULES Chem. Res. Toxicol. Chem. Rev. Chem. Mater. CRYST GROWTH DES ENERG FUEL Environ. Sci. Technol. Environ. Sci. Technol. Lett. Eur. J. Inorg. Chem. IND ENG CHEM RES Inorg. Chem. J. Agric. Food. Chem. J. Chem. Eng. Data J. Chem. Educ. J. Chem. Inf. Model. J. Chem. Theory Comput. J. Med. Chem. J. Nat. Prod. J PROTEOME RES J. Am. Chem. Soc. LANGMUIR MACROMOLECULES Mol. Pharmaceutics Nano Lett. Org. Lett. ORG PROCESS RES DEV ORGANOMETALLICS J. Org. Chem. J. Phys. Chem. J. Phys. Chem. A J. Phys. Chem. B J. Phys. Chem. C J. Phys. Chem. Lett. Analyst Anal. Methods Biomater. Sci. Catal. Sci. Technol. Chem. Commun. Chem. Soc. Rev. CHEM EDUC RES PRACT CRYSTENGCOMM Dalton Trans. Energy Environ. Sci. ENVIRON SCI-NANO ENVIRON SCI-PROC IMP ENVIRON SCI-WAT RES Faraday Discuss. Food Funct. Green Chem. Inorg. Chem. Front. Integr. Biol. J. Anal. At. Spectrom. J. Mater. Chem. A J. Mater. Chem. B J. Mater. Chem. C Lab Chip Mater. Chem. Front. Mater. Horiz. MEDCHEMCOMM Metallomics Mol. Biosyst. Mol. Syst. Des. Eng. Nanoscale Nanoscale Horiz. Nat. Prod. Rep. New J. Chem. Org. Biomol. Chem. Org. Chem. Front. PHOTOCH PHOTOBIO SCI PCCP Polym. Chem.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1