Pub Date : 2020-11-18DOI: 10.1109/dcis51330.2020.9268651
{"title":"DCIS 2020 Index","authors":"","doi":"10.1109/dcis51330.2020.9268651","DOIUrl":"https://doi.org/10.1109/dcis51330.2020.9268651","url":null,"abstract":"","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133499556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268667
Javier Aguilar, Albert Álvarez-Carulla, Valeria Colmena, Oscar Carreras, Genis Rabost, M. Puig-Vidal, J. Colomer-Farrarons, Xavier Muñoz, P. Miribel-Català, J. Punter-Villagrasa
In this work, we present an architecture of an envisaged autonomous self-powered potentiostat for biomedical wearable applications. This architecture has been conceived as a versatile and compact analog front-end for electrochemical disposable sensors, specifically as a key component of a wearable non-invasive biomedical device. This architecture is composed by a custom made three electrode potentiostat, a power management circuit for power regulation and to generate the bias voltage needed for proper electrochemical sensor operation, and finally an energy harvesting circuit for power generation. Initial characterization and validation of the potentiostat amplifier demonstrates good resolution, linearity and range, operating at ± 1.5V (450μW), being able to operate as an autonomous unit while being highly customizable for different electrochemical sensors.
{"title":"Autonomous self-powered potentiostat architecture for biomedical wearable applications.","authors":"Javier Aguilar, Albert Álvarez-Carulla, Valeria Colmena, Oscar Carreras, Genis Rabost, M. Puig-Vidal, J. Colomer-Farrarons, Xavier Muñoz, P. Miribel-Català, J. Punter-Villagrasa","doi":"10.1109/DCIS51330.2020.9268667","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268667","url":null,"abstract":"In this work, we present an architecture of an envisaged autonomous self-powered potentiostat for biomedical wearable applications. This architecture has been conceived as a versatile and compact analog front-end for electrochemical disposable sensors, specifically as a key component of a wearable non-invasive biomedical device. This architecture is composed by a custom made three electrode potentiostat, a power management circuit for power regulation and to generate the bias voltage needed for proper electrochemical sensor operation, and finally an energy harvesting circuit for power generation. Initial characterization and validation of the potentiostat amplifier demonstrates good resolution, linearity and range, operating at ± 1.5V (450μW), being able to operate as an autonomous unit while being highly customizable for different electrochemical sensors.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130124834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268648
Sara Alonso, Jesús Lázaro, J. Jiménez, L. Muguira, Alejandro Largacha
The use of hypervisors is constantly growing on account of their benefits. For some applications with hard realtime constraints, it is interesting to analyze the speed reduction that could cause. MPSoC boards are suitable for the use of hypervisors thanks to having an FPGA which allows the user to design the hardware and Cortex A53 cores, with armv8 architecture, which have virtualization extensions. The board has been validated with Xen hypervisor. This paper compares five scenarios to characterize the impact of the hypervisor layer on the speed of a network connection: a standalone application, Petalinux directly running on hardware, Petalinux running in Xen Dom0, Petalinux running in Xen DomU paravirtualizing the network and a Petalinux running in Xen DomU pass-throughing the network. It also characterizes the delay of the network connection in some scenarios as a complementary measurement. All the cases are implemented in the Zynq ZCU102 board. It is shown that a Xen hypervisor layer creates a considerable reduction in network speed. Provided that the network is settled down in passthrough mode, the network speed in DomU is almost the same as if there was no hypervisor.
{"title":"Analysing the interference of Xen hypervisor in the network speed","authors":"Sara Alonso, Jesús Lázaro, J. Jiménez, L. Muguira, Alejandro Largacha","doi":"10.1109/DCIS51330.2020.9268648","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268648","url":null,"abstract":"The use of hypervisors is constantly growing on account of their benefits. For some applications with hard realtime constraints, it is interesting to analyze the speed reduction that could cause. MPSoC boards are suitable for the use of hypervisors thanks to having an FPGA which allows the user to design the hardware and Cortex A53 cores, with armv8 architecture, which have virtualization extensions. The board has been validated with Xen hypervisor. This paper compares five scenarios to characterize the impact of the hypervisor layer on the speed of a network connection: a standalone application, Petalinux directly running on hardware, Petalinux running in Xen Dom0, Petalinux running in Xen DomU paravirtualizing the network and a Petalinux running in Xen DomU pass-throughing the network. It also characterizes the delay of the network connection in some scenarios as a complementary measurement. All the cases are implemented in the Zynq ZCU102 board. It is shown that a Xen hypervisor layer creates a considerable reduction in network speed. Provided that the network is settled down in passthrough mode, the network speed in DomU is almost the same as if there was no hypervisor.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117071503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268629
Sergio Lluva Plaza, J. M. V. Carrizo, Juan Jesús García Domínguez, Ana Jiménez Martín, David Gualda Gómez
This paper introduces an IoT wearable, specifically designed for the analysis of the physical activity of elderly people, in order to provide objective information to the healthcare staff to assess the frailty in these patients. The device, called FrailWear, is based on a STM32 low cost, low power and high-performance microcontroller. It is a multisensory system that includes an IMU and atmospheric pressure sensor for collecting data. In addition, it is possible to obtain the centimetric-accuracy position of the patient, if the infrastructure includes an external ultrasonic local positioning system. The wearable also includes a LoRaWAN based architecture, to communicate the system and the cloud, where the acquired data will be stored for a later analysis. Both physical activity and localization information are obtained, able to be analysed in real time or to be requested on demand by the carers. First test results of FrailWear are very promising and show its feasibility for this application.
{"title":"FrailWear: A Wearable IoT Device for Daily Activity Monitoring of Elderly Patients","authors":"Sergio Lluva Plaza, J. M. V. Carrizo, Juan Jesús García Domínguez, Ana Jiménez Martín, David Gualda Gómez","doi":"10.1109/DCIS51330.2020.9268629","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268629","url":null,"abstract":"This paper introduces an IoT wearable, specifically designed for the analysis of the physical activity of elderly people, in order to provide objective information to the healthcare staff to assess the frailty in these patients. The device, called FrailWear, is based on a STM32 low cost, low power and high-performance microcontroller. It is a multisensory system that includes an IMU and atmospheric pressure sensor for collecting data. In addition, it is possible to obtain the centimetric-accuracy position of the patient, if the infrastructure includes an external ultrasonic local positioning system. The wearable also includes a LoRaWAN based architecture, to communicate the system and the cloud, where the acquired data will be stored for a later analysis. Both physical activity and localization information are obtained, able to be analysed in real time or to be requested on demand by the carers. First test results of FrailWear are very promising and show its feasibility for this application.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117123405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268658
Gonzalo Rosa, Marta Villanueva, Jaime Sancho, Gemma Urbanos, Luisa Ruiz, M. Villa, Alberto Martín, E. Juárez, Luis Jiménez, M. Chavarrías, Alfonso Lagares, C. Sanz
The complexity of the Hyperspectral (HS) imaging-based applications demands faster and more efficient acquisition and processing systems. Moreover, HSI technology is being more and more used within the medical imaging field, increasing and making more restrictive the requirements of the implementations. In this work, the authors present an efficient methodology for the acquisition and stitching processes when capturing line-scan based HS images. In order to verify the proposed methodology, a full hardware and software setup has been implemented. The proposed method has been tested scanning a reference polymer at different working distances and scroll speeds. The obtained results in laboratory show that the delta in PSNR keeps below 5% for all cases. Also, the correlation between comparable spectral signatures are not affected neither by the working distance nor by the acquisition speed.
{"title":"Hyperspectral Images Acquisition: an Efficient Capture and Processing Stitching Procedure for Medical Environments","authors":"Gonzalo Rosa, Marta Villanueva, Jaime Sancho, Gemma Urbanos, Luisa Ruiz, M. Villa, Alberto Martín, E. Juárez, Luis Jiménez, M. Chavarrías, Alfonso Lagares, C. Sanz","doi":"10.1109/DCIS51330.2020.9268658","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268658","url":null,"abstract":"The complexity of the Hyperspectral (HS) imaging-based applications demands faster and more efficient acquisition and processing systems. Moreover, HSI technology is being more and more used within the medical imaging field, increasing and making more restrictive the requirements of the implementations. In this work, the authors present an efficient methodology for the acquisition and stitching processes when capturing line-scan based HS images. In order to verify the proposed methodology, a full hardware and software setup has been implemented. The proposed method has been tested scanning a reference polymer at different working distances and scroll speeds. The obtained results in laboratory show that the delta in PSNR keeps below 5% for all cases. Also, the correlation between comparable spectral signatures are not affected neither by the working distance nor by the acquisition speed.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115361078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268639
A. Barriga
This communication describes a design methodology that facilitates the implementation of processors based on the ISA of RISC-V. As an example of application of the proposed methodology, the design of three processors with different architectures and features is described.
{"title":"RISC-V processors design: a methodology for cores development","authors":"A. Barriga","doi":"10.1109/DCIS51330.2020.9268639","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268639","url":null,"abstract":"This communication describes a design methodology that facilitates the implementation of processors based on the ISA of RISC-V. As an example of application of the proposed methodology, the design of three processors with different architectures and features is described.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"104 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114048163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268643
N. Messaoudi, C. Crocker, M. Almendros
In this paper we present a flexible, highperformance, integrated qubit control system using modular PXIe equipment. To manipulate qubits, a classical control system is required to generate and acquire a mix of baseband, radio frequency, and/or optical signals, with the specific mix different for each qubit technology. Typically, a quantum system requires many of these signals with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. The proposed system is scalable to hundreds of channels, all of them being phase coherent and fully time-synchronized.The system includes a programmable real-time sequencer for precise execution timing and decision making; and open FPGA capabilities for custom Digital Signal Processing (DSP) by hardware. Using the latter, we present FPGA IP to generate one-/two-qubit gates efficiently with the AWG, and to analyze high-frequency signals to measure the qubit states in real time on the digitizers. This IP features very low latencies for Quantum Error Correction (QEC) and Frequency Division Multiplexing (FDM) capabilities, among others.
{"title":"A Hardware-Accelerated Qubit Control System for Quantum Information Processing","authors":"N. Messaoudi, C. Crocker, M. Almendros","doi":"10.1109/DCIS51330.2020.9268643","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268643","url":null,"abstract":"In this paper we present a flexible, highperformance, integrated qubit control system using modular PXIe equipment. To manipulate qubits, a classical control system is required to generate and acquire a mix of baseband, radio frequency, and/or optical signals, with the specific mix different for each qubit technology. Typically, a quantum system requires many of these signals with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. The proposed system is scalable to hundreds of channels, all of them being phase coherent and fully time-synchronized.The system includes a programmable real-time sequencer for precise execution timing and decision making; and open FPGA capabilities for custom Digital Signal Processing (DSP) by hardware. Using the latter, we present FPGA IP to generate one-/two-qubit gates efficiently with the AWG, and to analyze high-frequency signals to measure the qubit states in real time on the digitizers. This IP features very low latencies for Quantum Error Correction (QEC) and Frequency Division Multiplexing (FDM) capabilities, among others.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114970786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268666
N. Vidal, Arnau Salas Barenys, Aleix Garcia, J. Romeu, Giselle González, L. Jofre, J. López-Villegas
This paper presents the design and preliminary characterization of a novel 3D passive UHF-RFID tag. The prototype is fabricated using additive manufacturing techniques: 3D printing and copper electroplating. The design, manufacturing process and measurement set-up are presented and discussed in detail. We propose a biconical antenna design with helical strips in the cones to provide compactness without breaking the symmetry of the component and to improve bandwidth. The antenna is matched to a commercial UHF-RFID integrated circuit. The good agreement between results and simulations allows us to validate the whole process.
{"title":"Design and Characterization of Non-planar 3D-printed Passive UHF-RFID Tag","authors":"N. Vidal, Arnau Salas Barenys, Aleix Garcia, J. Romeu, Giselle González, L. Jofre, J. López-Villegas","doi":"10.1109/DCIS51330.2020.9268666","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268666","url":null,"abstract":"This paper presents the design and preliminary characterization of a novel 3D passive UHF-RFID tag. The prototype is fabricated using additive manufacturing techniques: 3D printing and copper electroplating. The design, manufacturing process and measurement set-up are presented and discussed in detail. We propose a biconical antenna design with helical strips in the cones to provide compactness without breaking the symmetry of the component and to improve bandwidth. The antenna is matched to a commercial UHF-RFID integrated circuit. The good agreement between results and simulations allows us to validate the whole process.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127739093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268669
A. Alheyasat, G. Torrens, S. Bota, B. Alorda
Physically Unclonable Functions (PUFs) are low-cost cryptographic primitives implemented in secret key generation and device authentication strategies. SRAM-PUFs are widely well-known as entropy source; however, they mainly experience a low reproducibility of the challenge-response pair because of non-deterministic noise conditions during the process of power-up. The reliability of SRAM-PUFs achieved these days comes by using complex error correcting codes (ECCs) combined with Fuzzy extractor structures introducing an increment in terms of power consumption, area cost and complexity of the design. In this paper we define an effective metric to classify the SRAM cells identifying the most reliable cells generating high reproductible responses for the PUF implementation and, identifying the most unpredictable ones for Random Number Generator (RNG). This metric is obtained from the mismatch between the cell’s inverters and the start-up behavior. Also, the noise in the PUF is modeled to validate the classification results obtained by the proposed metric. The proposed metric can be used during SRAM PUF design to explore the impact on reliable cells significantly increasing the reproducibility of the PUF and minimizing the dependability on ECCs and Fuzzy extractor.
{"title":"Selection of SRAM Cells to improve Reliable PUF implementation using Cell Mismatch Metric","authors":"A. Alheyasat, G. Torrens, S. Bota, B. Alorda","doi":"10.1109/DCIS51330.2020.9268669","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268669","url":null,"abstract":"Physically Unclonable Functions (PUFs) are low-cost cryptographic primitives implemented in secret key generation and device authentication strategies. SRAM-PUFs are widely well-known as entropy source; however, they mainly experience a low reproducibility of the challenge-response pair because of non-deterministic noise conditions during the process of power-up. The reliability of SRAM-PUFs achieved these days comes by using complex error correcting codes (ECCs) combined with Fuzzy extractor structures introducing an increment in terms of power consumption, area cost and complexity of the design. In this paper we define an effective metric to classify the SRAM cells identifying the most reliable cells generating high reproductible responses for the PUF implementation and, identifying the most unpredictable ones for Random Number Generator (RNG). This metric is obtained from the mismatch between the cell’s inverters and the start-up behavior. Also, the noise in the PUF is modeled to validate the classification results obtained by the proposed metric. The proposed metric can be used during SRAM PUF design to explore the impact on reliable cells significantly increasing the reproducibility of the PUF and minimizing the dependability on ECCs and Fuzzy extractor.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"49 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120885619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268615
Pablo Vera, S. Patón
Discrete time Σ∆ modulators habitually use a multi-level uniform quantizer (UQ); with this type of quantizer the maximum resolution is reached around full scale and system stability is improved. In this work, we propose the use of a multi-level non uniform quantizer (NUQ) to improve resolution for low input amplitude signals. The proposed architecture is compared with a uniform quantizer, and the effect of feedback DAC mismatch is analyzed. Different DAC mismatch shaping techniques are tested to compare their effects on SNR and SFDR, focusing on rotational element selection and Bi-DWA. Simulations are performed with MATLAB using behavioral modeled blocks. Results indicate that DAC mismatch produces a noticeable SNR degradation in converters with non uniform quantizer; DAC mismatch shaping methods are compared, rotational element selection being better in terms of SNR and Bi-DWA is better in terms of SFDR.
{"title":"DAC mismatch shaping in Discrete Time Sigma Delta ADCs with non uniform quantizer","authors":"Pablo Vera, S. Patón","doi":"10.1109/DCIS51330.2020.9268615","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268615","url":null,"abstract":"Discrete time Σ∆ modulators habitually use a multi-level uniform quantizer (UQ); with this type of quantizer the maximum resolution is reached around full scale and system stability is improved. In this work, we propose the use of a multi-level non uniform quantizer (NUQ) to improve resolution for low input amplitude signals. The proposed architecture is compared with a uniform quantizer, and the effect of feedback DAC mismatch is analyzed. Different DAC mismatch shaping techniques are tested to compare their effects on SNR and SFDR, focusing on rotational element selection and Bi-DWA. Simulations are performed with MATLAB using behavioral modeled blocks. Results indicate that DAC mismatch produces a noticeable SNR degradation in converters with non uniform quantizer; DAC mismatch shaping methods are compared, rotational element selection being better in terms of SNR and Bi-DWA is better in terms of SFDR.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120985454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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