Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268654
H. Fabelo, Raquel León, S. Ortega, Francisco Balea-Fernández, C. Bilbao, G. Callicó, A. Wagner
Alzheimer’s disease (AD) is a gradually progressive neurocognitive disorder (NCD) with a preclinical phase where the patient can be asymptomatic for many years. The detection of AD in its earliest stages is one of the most active areas in Alzheimer’s science. This early diagnosis could potentially allow for early intervention and improved prognosis, once effective treatment is available. This paper proposes a novel methodology based on spectral unmixing for the identification of biomarkers in plasma samples using visual and near infrared (VNIR) hyperspectral microscopy (HSM). The study was performed using ten drop plasma samples from 10 patients (5 control and 5 case subjects affected by NCD) captured with HSM at two different magnifications: 5× and 20×. This data was processed, and a statistical analysis of the abundance estimation was performed to identify relevant endmembers to differentiate case and control groups. The results suggest the potential of HSM and plasma samples as a cost-effective early diagnosis tool.
{"title":"Novel Methodology for Alzheimer's Disease Biomarker Identification in Plasma using Hyperspectral Microscopy","authors":"H. Fabelo, Raquel León, S. Ortega, Francisco Balea-Fernández, C. Bilbao, G. Callicó, A. Wagner","doi":"10.1109/DCIS51330.2020.9268654","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268654","url":null,"abstract":"Alzheimer’s disease (AD) is a gradually progressive neurocognitive disorder (NCD) with a preclinical phase where the patient can be asymptomatic for many years. The detection of AD in its earliest stages is one of the most active areas in Alzheimer’s science. This early diagnosis could potentially allow for early intervention and improved prognosis, once effective treatment is available. This paper proposes a novel methodology based on spectral unmixing for the identification of biomarkers in plasma samples using visual and near infrared (VNIR) hyperspectral microscopy (HSM). The study was performed using ten drop plasma samples from 10 patients (5 control and 5 case subjects affected by NCD) captured with HSM at two different magnifications: 5× and 20×. This data was processed, and a statistical analysis of the abundance estimation was performed to identify relevant endmembers to differentiate case and control groups. The results suggest the potential of HSM and plasma samples as a cost-effective early diagnosis tool.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126105245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268638
G. Carvalho, J. Ferreira, V. Tavares
Typical analogue-to-digital conversion (ADC) architectures, at Nyquist rate, tend to occupy a big portion of the integrated circuit die area and to consume more power than desired. Recently, with the rise of Interet-of-Things (IoT), there is a high demand for architectures that can have both reduced area and power consumption. Time encoding machines (TEM) might be a promising alternative. These types of encoders result in very simple and low-power analogue circuits, shifting most of its complexity to the decoding stage, typically stationed in a place with access to more resources. This paper focuses on a particular TEM, the integrate-and-fire neuron (IFN). The IFN modulation is based on a simplified first-order model of neural operation and it encodes the signal in a very power efficient manner. In the end, a novel hardware architecture for the reconstruction of the IFN encoded signal based on a spiking model will be presented. The method is demonstrated and implemented on FPGA, reaching an ENOB as high as 8.23.
{"title":"Hardware architecture for integrate-and-fire signal reconstruction on FPGA","authors":"G. Carvalho, J. Ferreira, V. Tavares","doi":"10.1109/DCIS51330.2020.9268638","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268638","url":null,"abstract":"Typical analogue-to-digital conversion (ADC) architectures, at Nyquist rate, tend to occupy a big portion of the integrated circuit die area and to consume more power than desired. Recently, with the rise of Interet-of-Things (IoT), there is a high demand for architectures that can have both reduced area and power consumption. Time encoding machines (TEM) might be a promising alternative. These types of encoders result in very simple and low-power analogue circuits, shifting most of its complexity to the decoding stage, typically stationed in a place with access to more resources. This paper focuses on a particular TEM, the integrate-and-fire neuron (IFN). The IFN modulation is based on a simplified first-order model of neural operation and it encodes the signal in a very power efficient manner. In the end, a novel hardware architecture for the reconstruction of the IFN encoded signal based on a spiking model will be presented. The method is demonstrated and implemented on FPGA, reaching an ENOB as high as 8.23.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"76 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120891743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268633
Samuel López Asunción, M. López-Vallejo, J. Grajal
Linear and quadratic regressions are techniques widely used in digital signal processing applications. This paper proposes a procedure and hardware architecture for the implementation of both regression methods and their mean square error (MSE) on FPGAs. Efficient computation of the bit widths of the coefficients of the regressions is carried out by finding their maxima and minima. Based on this optimization, a low-latency memory-less implementation for the computation of the MSE is proposed. Additionally, we have implemented the proposed architecture as part of a signal modulation classifier with hard real-time constraints.
{"title":"Algorithm-Architecture Optimization for Linear and Quadratic Regression on Reconfigurable Platforms","authors":"Samuel López Asunción, M. López-Vallejo, J. Grajal","doi":"10.1109/DCIS51330.2020.9268633","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268633","url":null,"abstract":"Linear and quadratic regressions are techniques widely used in digital signal processing applications. This paper proposes a procedure and hardware architecture for the implementation of both regression methods and their mean square error (MSE) on FPGAs. Efficient computation of the bit widths of the coefficients of the regressions is carried out by finding their maxima and minima. Based on this optimization, a low-latency memory-less implementation for the computation of the MSE is proposed. Additionally, we have implemented the proposed architecture as part of a signal modulation classifier with hard real-time constraints.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124036739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268652
Antonio J. Pérez-Ávila, G. González-Cordero, E. Pérez, E. Quesada, Mamathamba Kalishettyhalli Mahadevaiaha, C. Wenger, J. Roldán, F. Jiménez-Molinos
An artificial neural network based on resistive switching memristors is implemented and simulated in LTspice. The influence of memristor variability and the reduction of the continuous range of synaptic weights into a discrete set of conductance levels is analyzed. To do so, a behavioral model is proposed for multilevel resistive switching memristors based on Al-doped HfO2 dielectrics, and it is implemented in a spice based circuit simulator. The model provides an accurate description of the conductance in the different conductive states in addition to describe the device-to-device variability.
{"title":"Behavioral modeling of multilevel HfO2-based memristors for neuromorphic circuit simulation","authors":"Antonio J. Pérez-Ávila, G. González-Cordero, E. Pérez, E. Quesada, Mamathamba Kalishettyhalli Mahadevaiaha, C. Wenger, J. Roldán, F. Jiménez-Molinos","doi":"10.1109/DCIS51330.2020.9268652","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268652","url":null,"abstract":"An artificial neural network based on resistive switching memristors is implemented and simulated in LTspice. The influence of memristor variability and the reduction of the continuous range of synaptic weights into a discrete set of conductance levels is analyzed. To do so, a behavioral model is proposed for multilevel resistive switching memristors based on Al-doped HfO2 dielectrics, and it is implemented in a spice based circuit simulator. The model provides an accurate description of the conductance in the different conductive states in addition to describe the device-to-device variability.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"56 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126256055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268671
H. Posadas, Javier Merino, E. Villar
The design of increasingly complex embedded systems requires powerful solutions from the very beginning of the design process. Model Based Design (MBD) and early simulation have proven to be capable technologies to perform initial design space analysis to optimize system design. Traditional MBD methods and tools typically rely on fixed elements, which makes difficult the evaluation of different platform configurations, communication alternatives or models of computation. Addressing these challenges require flexible design technologies able to support, from a high-level abstract model, full design space exploration, including system specification, binary generation and performance evaluation. In this context, this paper proposes a UML/MARTE based approach able to address the challenges mentioned above by improving design flexibility and evaluation capabilities, including automatic code generation, trace execution collection and trace analysis from the initial UML models. The approach focuses on the definition and analysis of the paths data follow through the different application components, as a way to understand the behavior or the different design solutions.
{"title":"Data flow analysis from UML/MARTE models based on binary traces","authors":"H. Posadas, Javier Merino, E. Villar","doi":"10.1109/DCIS51330.2020.9268671","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268671","url":null,"abstract":"The design of increasingly complex embedded systems requires powerful solutions from the very beginning of the design process. Model Based Design (MBD) and early simulation have proven to be capable technologies to perform initial design space analysis to optimize system design. Traditional MBD methods and tools typically rely on fixed elements, which makes difficult the evaluation of different platform configurations, communication alternatives or models of computation. Addressing these challenges require flexible design technologies able to support, from a high-level abstract model, full design space exploration, including system specification, binary generation and performance evaluation. In this context, this paper proposes a UML/MARTE based approach able to address the challenges mentioned above by improving design flexibility and evaluation capabilities, including automatic code generation, trace execution collection and trace analysis from the initial UML models. The approach focuses on the definition and analysis of the paths data follow through the different application components, as a way to understand the behavior or the different design solutions.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126407183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/dcis51330.2020.9268635
{"title":"DCIS 2020 Commentary","authors":"","doi":"10.1109/dcis51330.2020.9268635","DOIUrl":"https://doi.org/10.1109/dcis51330.2020.9268635","url":null,"abstract":"","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131842209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268621
José Luis Saiz-Pérez, J. Pino, D. Mayor-Duarte, S. Khemchandani, Mario San Miguel-Montesdeoca, S. Mateos-Angulo
A Distributed Power Amplifier (DPA) with a tapered drain line is presented in this paper. The drain line impedance tapering technique allows to obtain a higher output power and efficiency compared to the conventional approach, whereas a constant drain line impedance avoids impedance changes in the power supply drive signal. The design was implemented using the D01GH/Si technology provided by the foundry OMMIC. The DPA achieves a Psat of 32 dBm and a flat gain over 14 dB in a frequency range that ranges from 1 to 8 GHz. Moreover, this circuit achieves a Power Added Efficiency (PAE) of 50%. Finally, the occupied area of the DPA is 2.2x1.2mm2 excluding pads.
{"title":"Distributed power amplifier in GaN technology with tapered drain lines","authors":"José Luis Saiz-Pérez, J. Pino, D. Mayor-Duarte, S. Khemchandani, Mario San Miguel-Montesdeoca, S. Mateos-Angulo","doi":"10.1109/DCIS51330.2020.9268621","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268621","url":null,"abstract":"A Distributed Power Amplifier (DPA) with a tapered drain line is presented in this paper. The drain line impedance tapering technique allows to obtain a higher output power and efficiency compared to the conventional approach, whereas a constant drain line impedance avoids impedance changes in the power supply drive signal. The design was implemented using the D01GH/Si technology provided by the foundry OMMIC. The DPA achieves a Psat of 32 dBm and a flat gain over 14 dB in a frequency range that ranges from 1 to 8 GHz. Moreover, this circuit achieves a Power Added Efficiency (PAE) of 50%. Finally, the occupied area of the DPA is 2.2x1.2mm2 excluding pads.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134239585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268614
Rafael Medina Morillas, P. Ituero
The rise of popularity of Spiking Neural Networks has resulted in a growing interest for simulating synaptic plasticity. Among the existing choices, Spike-Timing-Dependent Plasticity (STDP) represents a reliable solution whose main weakness consists on its high computational cost. This paper proposes several high-frequency FPGA architectures for the realization of pair-based STDP. It also presents a comparison between these implementations and previous ones, and analyzes the compromise between area utilization and precision. We also suggest a SNN architecture capable of implementing in-board STDP learning. The results show that our proposals achieve high throughput and maximum frequencies starting at 400MHz, with a reasonable area utilization and precision loss. The wide range of presented designs makes this work valuable for the decision-taking process in the design and implementation of large scale SNN with different area and precision requirements.
{"title":"STDP Design Trade-offs for FPGA-Based Spiking Neural Networks","authors":"Rafael Medina Morillas, P. Ituero","doi":"10.1109/DCIS51330.2020.9268614","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268614","url":null,"abstract":"The rise of popularity of Spiking Neural Networks has resulted in a growing interest for simulating synaptic plasticity. Among the existing choices, Spike-Timing-Dependent Plasticity (STDP) represents a reliable solution whose main weakness consists on its high computational cost. This paper proposes several high-frequency FPGA architectures for the realization of pair-based STDP. It also presents a comparison between these implementations and previous ones, and analyzes the compromise between area utilization and precision. We also suggest a SNN architecture capable of implementing in-board STDP learning. The results show that our proposals achieve high throughput and maximum frequencies starting at 400MHz, with a reasonable area utilization and precision loss. The wide range of presented designs makes this work valuable for the decision-taking process in the design and implementation of large scale SNN with different area and precision requirements.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115658580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268650
Luisa Ruiz, Alberto Martín, Gemma Urbanos, Marta Villanueva, Jaime Sancho, Gonzalo Rosa, M. Villa, M. Chavarrías, Ángel Pérez, E. Juárez, Alfonso Lagares, C. Sanz
Hyperspectral Imaging (HSI) can be used as a non invasive medical diagnostic method when used in combination with Machine Learning (ML) algorithms. The significant captured data in HSI can be useful for classifying different types of brain tissues, since they gather reflectance values from different band widths below and beyond the visual spectrum. This allows ML algorithms like Support Vector Machines (SVM) and Random Forest (RF) to classify brain tissues such as tumors. Predicted results can be used to create visualizations and support neurosurgeons before injuring any tissue. This way neurosurgeons can be more precise, reducing any possible damages on healthy tissues. In this work, a proposal for the classification of in-vivo brain hyperspectral images using SVM and RF classifiers is presented. A total of four hyperspectral images from four different patients with glioblastoma grade IV (GBM) brain tumor have been selected to train models and, therefore, classify them. Five different classes have been defined during experiments: healthy tissue, tumor, venous blood vessel, arterial blood vessel and dura mater. Results obtained suggest that SVM usually performs better than RF, generally achieving up to 97% of mean accuracy (ACC). However, RF performance had better results than SVM when classifying images used during training, obtaining almost 100% of mean ACC for all 5 classes described. This study shows the robustness of SVM and the potential of RF for real-time brain cancer detection.
{"title":"Multiclass Brain Tumor Classification Using Hyperspectral Imaging and Supervised Machine Learning","authors":"Luisa Ruiz, Alberto Martín, Gemma Urbanos, Marta Villanueva, Jaime Sancho, Gonzalo Rosa, M. Villa, M. Chavarrías, Ángel Pérez, E. Juárez, Alfonso Lagares, C. Sanz","doi":"10.1109/DCIS51330.2020.9268650","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268650","url":null,"abstract":"Hyperspectral Imaging (HSI) can be used as a non invasive medical diagnostic method when used in combination with Machine Learning (ML) algorithms. The significant captured data in HSI can be useful for classifying different types of brain tissues, since they gather reflectance values from different band widths below and beyond the visual spectrum. This allows ML algorithms like Support Vector Machines (SVM) and Random Forest (RF) to classify brain tissues such as tumors. Predicted results can be used to create visualizations and support neurosurgeons before injuring any tissue. This way neurosurgeons can be more precise, reducing any possible damages on healthy tissues. In this work, a proposal for the classification of in-vivo brain hyperspectral images using SVM and RF classifiers is presented. A total of four hyperspectral images from four different patients with glioblastoma grade IV (GBM) brain tumor have been selected to train models and, therefore, classify them. Five different classes have been defined during experiments: healthy tissue, tumor, venous blood vessel, arterial blood vessel and dura mater. Results obtained suggest that SVM usually performs better than RF, generally achieving up to 97% of mean accuracy (ACC). However, RF performance had better results than SVM when classifying images used during training, obtaining almost 100% of mean ACC for all 5 classes described. This study shows the robustness of SVM and the potential of RF for real-time brain cancer detection.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114389490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-18DOI: 10.1109/DCIS51330.2020.9268632
L. Parrilla, Encarnación Castillo, Antonio García
The increase in the frequency of pandemic crises in recent years, with the current example of COVID-19, leads to the need of having technological tools that help to control the spread of these diseases in the first instance, and to avoid the generation of new outbreaks in the phases of back to normality. The main issue in these tools is the how to make their effectiveness compatible with privacy. In this work we present a system enabling secure distribution of people in closed environments such as public transport, restaurants or cinemas while maintaining privacy of health data. The system is based on Elliptic Curve Cryptography and it has been implemented on low-cost FPGA devices.
{"title":"Privacy-enabled system based on Elliptic Curve Cryptography to reduce risks of contagion in pandemics","authors":"L. Parrilla, Encarnación Castillo, Antonio García","doi":"10.1109/DCIS51330.2020.9268632","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268632","url":null,"abstract":"The increase in the frequency of pandemic crises in recent years, with the current example of COVID-19, leads to the need of having technological tools that help to control the spread of these diseases in the first instance, and to avoid the generation of new outbreaks in the phases of back to normality. The main issue in these tools is the how to make their effectiveness compatible with privacy. In this work we present a system enabling secure distribution of people in closed environments such as public transport, restaurants or cinemas while maintaining privacy of health data. The system is based on Elliptic Curve Cryptography and it has been implemented on low-cost FPGA devices.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127001090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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