Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988945
T. Matsudai, K. Endo, T. Ogura, T. Matsumoto, K. Uchiyama, F. Niikura, K. Koshikawa
This paper proposes a direct photo emission monitoring during avalanche operation for IGBTs (Insulated Gate Bipolar Transistors) using a streak camera. IGBTs have been developed to improve trade-off relation between on-state losses and switching losses. And also reliability enhancement is very important issue. To enhance reliability, it is important to investigate avalanche phenomenon of IGBTs, directly. During avalanche operation, it is well known that visible light is emitted from the device. This is the study to succeed in observing photo emission directly from avalanche phenomena under UIS (Undamped Inductive Switching) condition of IGBTs. We have also measured moving emission region in edge termination area.
{"title":"Direct photo emission monitoring for analysis of IGBT destruction mechanism using streak camera","authors":"T. Matsudai, K. Endo, T. Ogura, T. Matsumoto, K. Uchiyama, F. Niikura, K. Koshikawa","doi":"10.23919/ISPSD.2017.7988945","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988945","url":null,"abstract":"This paper proposes a direct photo emission monitoring during avalanche operation for IGBTs (Insulated Gate Bipolar Transistors) using a streak camera. IGBTs have been developed to improve trade-off relation between on-state losses and switching losses. And also reliability enhancement is very important issue. To enhance reliability, it is important to investigate avalanche phenomenon of IGBTs, directly. During avalanche operation, it is well known that visible light is emitted from the device. This is the study to succeed in observing photo emission directly from avalanche phenomena under UIS (Undamped Inductive Switching) condition of IGBTs. We have also measured moving emission region in edge termination area.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125137079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988969
Weicheng Zhou, Shu Yang, Xinke Wu, Kuang Sheng
SWicoii Carbide (SiC) MOSFET, enabling high frequency, high temperature and high power density, are attractive for power electronics applications. However, due to the limited area of a single chip, paralleling SiC MOSFETs is a necessary approach to increase the capacity of the power module. In this work, targeted at 20kW DC/DC converter for HEV application, we have designed and fabricated 1200V/100A SiC MOSFETs modules using different numbers of 1200V/80mΩ SiC MOSFET chips. The influence of chip number on switching loss and efficiency of the power modules have been analyzed for module optimization. Furthermore, the operating frequency and efficiency of the power module basing on SiC MOSFET and Si IGBT are compared and investigated.
SWicoii碳化物(SiC) MOSFET具有高频、高温和高功率密度的特性，在电力电子应用中具有很大的吸引力。然而，由于单个芯片的面积有限，并联SiC mosfet是增加功率模块容量的必要方法。在这项工作中，我们针对HEV应用的20kW DC/DC转换器，使用不同数量的1200V/80mΩ SiC MOSFET芯片设计和制造了1200V/100A SiC MOSFET模块。分析了芯片数量对功率模块开关损耗和效率的影响，对模块进行了优化。并对基于SiC MOSFET和基于Si IGBT的功率模块的工作频率和效率进行了比较和研究。
{"title":"Optimal design of SiC MOSFETs for 20kW DCDC converter","authors":"Weicheng Zhou, Shu Yang, Xinke Wu, Kuang Sheng","doi":"10.23919/ISPSD.2017.7988969","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988969","url":null,"abstract":"SWicoii Carbide (SiC) MOSFET, enabling high frequency, high temperature and high power density, are attractive for power electronics applications. However, due to the limited area of a single chip, paralleling SiC MOSFETs is a necessary approach to increase the capacity of the power module. In this work, targeted at 20kW DC/DC converter for HEV application, we have designed and fabricated 1200V/100A SiC MOSFETs modules using different numbers of 1200V/80mΩ SiC MOSFET chips. The influence of chip number on switching loss and efficiency of the power modules have been analyzed for module optimization. Furthermore, the operating frequency and efficiency of the power module basing on SiC MOSFET and Si IGBT are compared and investigated.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129411488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988930
Chao Liu, Wanjun Chen, H. Tao, Yijun Shi, Xuefeng Tang, Wuhao Gao, Qi Zhou, Zhaoji Li, Bo Zhang
In this paper, the transient overvoltage induced failure during high di/dt discharge is studied based on a cathode-short MOS controlled thyristor (CS-MCT). The intrinsic reason of this failure is that the pulse current with high di/dt flowing though the inherent parasitic cathode inductance, produces a high transient overvoltage that makes breakage of the gate oxide. The mechanism of the transient overvoltage is theoretically detailed. A simple solution is proposed by adding a second emitter lead, which is called the Kelvin connection. The Kelvin emitter greatly clamps the overvoltage at high di/dt condition, preventing gate oxide from being broken down. The advantage of Kelvin connection against the normal connection was experimentally demonstrated and validated.
{"title":"Transient overvoltage induced failure of MOS-controlled thyristor under ultra-high di/dt condition","authors":"Chao Liu, Wanjun Chen, H. Tao, Yijun Shi, Xuefeng Tang, Wuhao Gao, Qi Zhou, Zhaoji Li, Bo Zhang","doi":"10.23919/ISPSD.2017.7988930","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988930","url":null,"abstract":"In this paper, the transient overvoltage induced failure during high di/dt discharge is studied based on a cathode-short MOS controlled thyristor (CS-MCT). The intrinsic reason of this failure is that the pulse current with high di/dt flowing though the inherent parasitic cathode inductance, produces a high transient overvoltage that makes breakage of the gate oxide. The mechanism of the transient overvoltage is theoretically detailed. A simple solution is proposed by adding a second emitter lead, which is called the Kelvin connection. The Kelvin emitter greatly clamps the overvoltage at high di/dt condition, preventing gate oxide from being broken down. The advantage of Kelvin connection against the normal connection was experimentally demonstrated and validated.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116199938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988975
K. Saito, T. Miyoshi, Daisuke Kawase, S. Hayakawa, T. Masuda, Y. Sasajima
We propose a method to design a module structure avoiding the risk of self-excited (SE) oscillation. By simplifying both the semiconductor device and lumped circuit model, oscillatory conditions can be extracted analytically. Results show good agreement with T-CAD simulation and measurement results of test modules. The method is applied to the design of next generation common package, which has realized very low system inductance. SE oscillation can be prevented for latest generation Si-IGBTs having very small feedback capacitance and SiC-MOS having high output capacitance mounted in the same common package design.
{"title":"Suppression of self-excited oscillation for common package of Si-IGBT and SiC-MOS","authors":"K. Saito, T. Miyoshi, Daisuke Kawase, S. Hayakawa, T. Masuda, Y. Sasajima","doi":"10.23919/ISPSD.2017.7988975","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988975","url":null,"abstract":"We propose a method to design a module structure avoiding the risk of self-excited (SE) oscillation. By simplifying both the semiconductor device and lumped circuit model, oscillatory conditions can be extracted analytically. Results show good agreement with T-CAD simulation and measurement results of test modules. The method is applied to the design of next generation common package, which has realized very low system inductance. SE oscillation can be prevented for latest generation Si-IGBTs having very small feedback capacitance and SiC-MOS having high output capacitance mounted in the same common package design.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127816051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988936
A. Korzenietz, G. Wachutka, F. Hille, C. Sandow, F. Niedernostheide
Hydrogen-related donors can be advantageously used in IGBTs and power diodes with a view to creating field-stop layers and to optimising the electrical performance. In this work, the influence of hydrogen-related donors on the on-state plasma profile in field-stop IGBTs is analysed by means of free-carrier absorption measurements. For these investigations, dedicated IGBT test structures were used, which had been adapted to the specific properties of the employed measurement set-up. Two different hydrogen-related donor profiles were implanted into these IGBT samples and, subsequently, measurements with different current densities were compared to 2D TCAD numerical simulations. In the next step, the simulation models were adjusted, with respect to carrier lifetime and mobility to reflect the impact of a possible variation of these properties.
{"title":"Free-carrier absorption experiments for the investigation of the physical device properties in IGBTs with hydrogen-related donors","authors":"A. Korzenietz, G. Wachutka, F. Hille, C. Sandow, F. Niedernostheide","doi":"10.23919/ISPSD.2017.7988936","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988936","url":null,"abstract":"Hydrogen-related donors can be advantageously used in IGBTs and power diodes with a view to creating field-stop layers and to optimising the electrical performance. In this work, the influence of hydrogen-related donors on the on-state plasma profile in field-stop IGBTs is analysed by means of free-carrier absorption measurements. For these investigations, dedicated IGBT test structures were used, which had been adapted to the specific properties of the employed measurement set-up. Two different hydrogen-related donor profiles were implanted into these IGBT samples and, subsequently, measurements with different current densities were compared to 2D TCAD numerical simulations. In the next step, the simulation models were adjusted, with respect to carrier lifetime and mobility to reflect the impact of a possible variation of these properties.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128768906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988991
R. Rupp, R. Elpelt, R. Gerlach, Reinhold Schömer, M. Draghici
In this paper we introduce a new generation of silicon carbide (SiC) Schottky diodes with reduced threshold voltage. A detailed comparison with Infineon's 5th generation of SiC diodes (G5) is done. With a Mo-based Schottky metal system, the new generation of diodes (G6) was designed in such a way that the increased reverse power loss is more than balanced by the efficiency gained by the low threshold voltage. Therefore, in spite of a higher reverse current, due to a lower Schottky barrier, it is shown that the efficiency of G6 is higher and the ohmic losses are reduced in comparison with G5 over a wide load range. G6 also demonstrates similar surge current capabilities as G5 and high ruggedness of the Schottky barrier.
{"title":"A new SiC diode with significantly reduced threshold voltage","authors":"R. Rupp, R. Elpelt, R. Gerlach, Reinhold Schömer, M. Draghici","doi":"10.23919/ISPSD.2017.7988991","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988991","url":null,"abstract":"In this paper we introduce a new generation of silicon carbide (SiC) Schottky diodes with reduced threshold voltage. A detailed comparison with Infineon's 5th generation of SiC diodes (G5) is done. With a Mo-based Schottky metal system, the new generation of diodes (G6) was designed in such a way that the increased reverse power loss is more than balanced by the efficiency gained by the low threshold voltage. Therefore, in spite of a higher reverse current, due to a lower Schottky barrier, it is shown that the efficiency of G6 is higher and the ohmic losses are reduced in comparison with G5 over a wide load range. G6 also demonstrates similar surge current capabilities as G5 and high ruggedness of the Schottky barrier.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133822248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988974
Seita Iwahashi, T. Otsuka, Takashi Nakamura
The transfer-molded package with ceramic substrate is widely developed for power modules in the industrial and automobile applications. However, the difference in coefficient of thermal expansion (Δ CTE) between the ceramics and the molding resin is a significant problem, which is the fundamental cause of “warpage”. This research provides a new concept where the stacked resin structure is composed of two kinds of molding resins and as a result, the advantage of reduced warpage can be confirmed. Generally, the warpage is designed to be reduced by adjusting the properties of the molding resins to minimize the ACTE from the substrate. Meanwhile, our FEA simulation revealed that using two molding resins with the large and small ACTE from the substrate reduce more effectively the warpage than the one with the small ACTE. This mechanism is due to warping stress contribution from the stacked resins in the opposite of the original warpage direction. We fabricated the transfer-molded package with the stacked-resin structure and confirmed that the warpage can be reduced compared to the conventional structure. Also, the experimental results of the warpage showed good agreement with the simulation results.
{"title":"Stacked resin structure for reducing warpage of transfer-molded modules","authors":"Seita Iwahashi, T. Otsuka, Takashi Nakamura","doi":"10.23919/ISPSD.2017.7988974","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988974","url":null,"abstract":"The transfer-molded package with ceramic substrate is widely developed for power modules in the industrial and automobile applications. However, the difference in coefficient of thermal expansion (Δ CTE) between the ceramics and the molding resin is a significant problem, which is the fundamental cause of “warpage”. This research provides a new concept where the stacked resin structure is composed of two kinds of molding resins and as a result, the advantage of reduced warpage can be confirmed. Generally, the warpage is designed to be reduced by adjusting the properties of the molding resins to minimize the ACTE from the substrate. Meanwhile, our FEA simulation revealed that using two molding resins with the large and small ACTE from the substrate reduce more effectively the warpage than the one with the small ACTE. This mechanism is due to warping stress contribution from the stacked resins in the opposite of the original warpage direction. We fabricated the transfer-molded package with the stacked-resin structure and confirmed that the warpage can be reduced compared to the conventional structure. Also, the experimental results of the warpage showed good agreement with the simulation results.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127772888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988968
J. Ewanchuk, J. Brandelero, S. Mollov
The full utilization of the active devices within a SiC power module can be limited by the common stray inductive path imposed by the substrate layout. In this paper, the prospect of integrating individual gate bulfers per power die is explored for lowering the total losses of a power module, while maintaining a good thermal distribution across the set of dies. Each die within the power module has an increased utilization due not only having lowered losses, but due to the similar source inductive path for die, similar thermal loading. Using a 50kVA, 1.2kV, 8-die prototype power module, the overall switching losses using per-die bulfers is found to be reduced by a factor of 25%, while significantly improving the thermal distribution from die to die.
{"title":"Improving the die utilization and lifetime in a multi-die SiC power module by means of integrated per-die gate buffers","authors":"J. Ewanchuk, J. Brandelero, S. Mollov","doi":"10.23919/ISPSD.2017.7988968","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988968","url":null,"abstract":"The full utilization of the active devices within a SiC power module can be limited by the common stray inductive path imposed by the substrate layout. In this paper, the prospect of integrating individual gate bulfers per power die is explored for lowering the total losses of a power module, while maintaining a good thermal distribution across the set of dies. Each die within the power module has an increased utilization due not only having lowered losses, but due to the similar source inductive path for die, similar thermal loading. Using a 50kVA, 1.2kV, 8-die prototype power module, the overall switching losses using per-die bulfers is found to be reduced by a factor of 25%, while significantly improving the thermal distribution from die to die.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127934154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988916
M. Fernández, X. Perpiñà, M. Vellvehí, X. Jordà, J. Roig, F. Bauwens, M. Tack
Gallium Nitride (GaN) Enhancement-mode High-Electron-Mobility Transistors (EHEMTs) are promising devices for motor drives. Hence, ensuring and gaining insight into their ruggedness against Short-Circuit (SC) faults become essential. Thus, SC stresses (types I and II) are studied for the first time in commercial EHEMTs with similar on-state resistance (∼ 100 mΩ) and breakdown voltage (∼ 600 V). As SC failure mechanisms, thermal (SC I) and dielectric (SC II) breakdown are identified.
{"title":"Short-circuit capability in p-GaNHEMTs and GaNMISHEMTs","authors":"M. Fernández, X. Perpiñà, M. Vellvehí, X. Jordà, J. Roig, F. Bauwens, M. Tack","doi":"10.23919/ISPSD.2017.7988916","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988916","url":null,"abstract":"Gallium Nitride (GaN) Enhancement-mode High-Electron-Mobility Transistors (EHEMTs) are promising devices for motor drives. Hence, ensuring and gaining insight into their ruggedness against Short-Circuit (SC) faults become essential. Thus, SC stresses (types I and II) are studied for the first time in commercial EHEMTs with similar on-state resistance (∼ 100 mΩ) and breakdown voltage (∼ 600 V). As SC failure mechanisms, thermal (SC I) and dielectric (SC II) breakdown are identified.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128957287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988903
Shu Yang, Chunhua Zhou, Shaowen Han, Kuang Sheng, K. J. Chen
Buffer traps in GaN-on-Si power devices can interact with electrons injected from Si substrate at high-voltage OFF state, leading to buffer-related dynamic ON-resistance degradation. In this work, we performed transient back-gating measurements on GaN-on-Si power transistors under both high negative and positive substrate biases. The opposite top-to-substrate bias polarities not only yield asymmetric vertical leakage, but also induce distinct buffer-trapping due to the fundamentally different electron injection mechanisms. The injected electrons interact with acceptor and donor traps in the buffer layer, which can impose modulation to the 2DEG channel. It is suggested that suppressing electron injection from Si substrate can possibly enhance devices' dynamic performance and blocking capability.
{"title":"Buffer trapping-induced RON degradation in GaN-on-Si power transistors: Role of electron injection from Si substrate","authors":"Shu Yang, Chunhua Zhou, Shaowen Han, Kuang Sheng, K. J. Chen","doi":"10.23919/ISPSD.2017.7988903","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988903","url":null,"abstract":"Buffer traps in GaN-on-Si power devices can interact with electrons injected from Si substrate at high-voltage OFF state, leading to buffer-related dynamic ON-resistance degradation. In this work, we performed transient back-gating measurements on GaN-on-Si power transistors under both high negative and positive substrate biases. The opposite top-to-substrate bias polarities not only yield asymmetric vertical leakage, but also induce distinct buffer-trapping due to the fundamentally different electron injection mechanisms. The injected electrons interact with acceptor and donor traps in the buffer layer, which can impose modulation to the 2DEG channel. It is suggested that suppressing electron injection from Si substrate can possibly enhance devices' dynamic performance and blocking capability.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116246779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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