Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988941
F. Rodriguez, D. Schloegl, F. Hille, P. Brandt, M. Pfaffenlehner, A. Stegner, A. Haertl
Electrical characterization results (e.g. softness, cosmic ray hardness, surge current) of a novel freewheeling diode with reduced thickness and copper metallization are shown.
{"title":"Novel emitter controlled diode with copper metallization in ultrathin wafer technology: Setting a performance benchmark","authors":"F. Rodriguez, D. Schloegl, F. Hille, P. Brandt, M. Pfaffenlehner, A. Stegner, A. Haertl","doi":"10.23919/ISPSD.2017.7988941","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988941","url":null,"abstract":"Electrical characterization results (e.g. softness, cosmic ray hardness, surge current) of a novel freewheeling diode with reduced thickness and copper metallization are shown.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126945675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988996
Woongje Sung, Kijeong Han, B. Baliga
This paper provides detailed comparison of electrical characteristics of accumulation mode and inversion mode 1.2 kV SiC MOSFETs, including performance at high temperatures (up to 200 °C). Statistical data measured from over 50 dies on 6-inch SiC wafers was used for this comparison. It is concluded that the accumulation mode SiC MOSFET provides a lower specific on-resistance than the inversion mode MOSFET due to a higher channel mobility (∼ 22 cm2/V·s) while achieving a reasonable threshold voltage (∼ 2.3 V). Based on statistical data analyses, a strong correlation between the threshold voltage and the field effect channel mobility was identified.
本文详细比较了1.2 kV SiC mosfet的积累模式和反转模式的电特性，包括高温(高达200°C)下的性能。从50多个6英寸SiC晶圆上测量的统计数据用于此比较。结果表明，积累模式SiC MOSFET具有较高的沟道迁移率(~ 22 cm2/V·s)，且具有合理的阈值电压(~ 2.3 V)，因此比逆变模式MOSFET具有更低的导通电阻。基于统计数据分析，阈值电压与场效应沟道迁移率之间存在很强的相关性。
{"title":"A comparative study of channel designs for SiC MOSFETs: Accumulation mode channel vs. inversion mode channel","authors":"Woongje Sung, Kijeong Han, B. Baliga","doi":"10.23919/ISPSD.2017.7988996","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988996","url":null,"abstract":"This paper provides detailed comparison of electrical characteristics of accumulation mode and inversion mode 1.2 kV SiC MOSFETs, including performance at high temperatures (up to 200 °C). Statistical data measured from over 50 dies on 6-inch SiC wafers was used for this comparison. It is concluded that the accumulation mode SiC MOSFET provides a lower specific on-resistance than the inversion mode MOSFET due to a higher channel mobility (∼ 22 cm2/V·s) while achieving a reasonable threshold voltage (∼ 2.3 V). Based on statistical data analyses, a strong correlation between the threshold voltage and the field effect channel mobility was identified.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122896594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988905
L. Knoll, A. Mihaila, F. Bauer, V. Sundaramoorthy, E. Bianda, R. Minamisawa, L. Kranz, M. Bellini, U. Vemulapati, H. Bartolf, S. Kicin, S. Skibin, C. Papadopoulos, Munaf T. A. Rahimo
An approach to implement electrically robust MOSFETs in a functioning half-bridge will be investigated. For the first time, reverse conducting 3.3kV SiC MOSFETs have been fabricated with dilferent cell pitches from 14μm (p1.0) to 26μm (pl.8) that are able to withstand short circuit pulse of up to 10μs and a 9ms surge current event up to 15x the nominal current. LinPak half-bridge modules have been fabricated showing reduction of the switching loss by more than 90% compared to a silicon IGBT/diode half bridge.
我们将研究在半桥电路中实现电稳健性mosfet的方法。研究人员首次制造出具有14μm (p1.0)到26μm (pl.8)不同间距的3.3kV SiC mosfet，能够承受高达10μs的短路脉冲和高达15倍标称电流的9ms浪涌电流事件。LinPak半桥模块已经制造出来，与硅IGBT/二极管半桥相比，开关损耗降低了90%以上。
{"title":"Robust 3.3kV silicon carbide MOSFETs with surge and short circuit capability","authors":"L. Knoll, A. Mihaila, F. Bauer, V. Sundaramoorthy, E. Bianda, R. Minamisawa, L. Kranz, M. Bellini, U. Vemulapati, H. Bartolf, S. Kicin, S. Skibin, C. Papadopoulos, Munaf T. A. Rahimo","doi":"10.23919/ISPSD.2017.7988905","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988905","url":null,"abstract":"An approach to implement electrically robust MOSFETs in a functioning half-bridge will be investigated. For the first time, reverse conducting 3.3kV SiC MOSFETs have been fabricated with dilferent cell pitches from 14μm (p1.0) to 26μm (pl.8) that are able to withstand short circuit pulse of up to 10μs and a 9ms surge current event up to 15x the nominal current. LinPak half-bridge modules have been fabricated showing reduction of the switching loss by more than 90% compared to a silicon IGBT/diode half bridge.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129787117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988933
P. Diaz Reigosa, F. Iannuzzo, Munaf T. A. Rahimo
Insulated-Gate Bipolar Transistors (IGBTs) exhibit a gate-voltage oscillation phenomenon during short-circuit, which can result in a gate-oxide breakdown. The oscillations have been investigated through device simulations and experimental investigations of a 3.3-kV IGBT. It has been found that the oscillations are more likely to occur at low DC-link voltages, high gate voltages and low temperatures due to a charge-storage effect at the surface of the IGBT. Based on this insight, the charge-storage effect can be explained with a reduction in carrier velocity due to the electric field shape rotation during short circuit.
{"title":"TCAD analysis of short-circuit oscillations in IGBTs","authors":"P. Diaz Reigosa, F. Iannuzzo, Munaf T. A. Rahimo","doi":"10.23919/ISPSD.2017.7988933","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988933","url":null,"abstract":"Insulated-Gate Bipolar Transistors (IGBTs) exhibit a gate-voltage oscillation phenomenon during short-circuit, which can result in a gate-oxide breakdown. The oscillations have been investigated through device simulations and experimental investigations of a 3.3-kV IGBT. It has been found that the oscillations are more likely to occur at low DC-link voltages, high gate voltages and low temperatures due to a charge-storage effect at the surface of the IGBT. Based on this insight, the charge-storage effect can be explained with a reduction in carrier velocity due to the electric field shape rotation during short circuit.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129002980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988890
Huaping Jiang, Jin Wei, X. Dai, C. Zheng, Maolong Ke, Xiaochuan Deng, Y. Sharma, I. Deviny, P. Mawby
A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) for 10-kV application is proposed in this paper, which features a built-in Schottky barrier diode (SBD). Therefore, the body diode is free from activation during the third quadrant conduction state, which is beneficial for reducing the switching loss and suppressing bipolar degradation. Numerical simulations with Sentaurus TCAD are carried out to investigate the characteristics of the proposed structure in comparison to the conventional MOSFET and SBD pair. It is found that the proposed structure achieves lower reverse recovery charge and switching loss owing to three factors, i.e., faster switching speed, smaller capacitive charge, and body diode deactivation, and therefore is a superior choice for 10-kV applications.
{"title":"SiC MOSFET with built-in SBD for reduction of reverse recovery charge and switching loss in 10-kV applications","authors":"Huaping Jiang, Jin Wei, X. Dai, C. Zheng, Maolong Ke, Xiaochuan Deng, Y. Sharma, I. Deviny, P. Mawby","doi":"10.23919/ISPSD.2017.7988890","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988890","url":null,"abstract":"A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) for 10-kV application is proposed in this paper, which features a built-in Schottky barrier diode (SBD). Therefore, the body diode is free from activation during the third quadrant conduction state, which is beneficial for reducing the switching loss and suppressing bipolar degradation. Numerical simulations with Sentaurus TCAD are carried out to investigate the characteristics of the proposed structure in comparison to the conventional MOSFET and SBD pair. It is found that the proposed structure achieves lower reverse recovery charge and switching loss owing to three factors, i.e., faster switching speed, smaller capacitive charge, and body diode deactivation, and therefore is a superior choice for 10-kV applications.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129346404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988896
H. Fujii, S. Tokumitsu, T. Mori, T. Yamashita, T. Maruyama, T. Maruyama, Y. Maruyama, Shigeki Nishimoto, Hiroyuki Arie, Shunji Kubo, T. Ipposhi
This paper proposes a 90nm bulk BiCDMOS platform for automotive applications. In this platform, two types of characteristic deep trench isolations are introduced. One has a top-to-bottom air-gap which serves as a stable isolator against high voltage. Another has a tungsten plug which not only minimizes area and resistance for substrate grounding but also slims down a noise-blocking active barrier guard-ring. For an Neh LD-MOSFET, a resurf-enforcing p-type region is inserted to cancel the electric field intensification brought by little thermal treatment. The advanced 90nm rule is mainly applied to a logic area for chip-size reduction. This platform also provides analog-friendly devices such as HV BJTs, full-isolation diode and eFlash.
{"title":"A 90nm bulk BiCDMOS platform technology with 15–80V LD-MOSFETs for automotive applications","authors":"H. Fujii, S. Tokumitsu, T. Mori, T. Yamashita, T. Maruyama, T. Maruyama, Y. Maruyama, Shigeki Nishimoto, Hiroyuki Arie, Shunji Kubo, T. Ipposhi","doi":"10.23919/ISPSD.2017.7988896","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988896","url":null,"abstract":"This paper proposes a 90nm bulk BiCDMOS platform for automotive applications. In this platform, two types of characteristic deep trench isolations are introduced. One has a top-to-bottom air-gap which serves as a stable isolator against high voltage. Another has a tungsten plug which not only minimizes area and resistance for substrate grounding but also slims down a noise-blocking active barrier guard-ring. For an Neh LD-MOSFET, a resurf-enforcing p-type region is inserted to cancel the electric field intensification brought by little thermal treatment. The advanced 90nm rule is mainly applied to a logic area for chip-size reduction. This platform also provides analog-friendly devices such as HV BJTs, full-isolation diode and eFlash.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1799 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129644846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988876
Songbek Che, S. Nagai, N. Negoro, Yasufumi Kawai, O. Tabata, S. Enomoto, Y. Anda, T. Hatsuda
Fast switching operation of power electronics systems is significantly advantageous for reducing volume of passive components and increasing power density in the systems. Next generation power devices, such as GaN gate-injection transistor (GIT), are promising for high frequency operations and isolated gate driving is also highly recommended owing to its noise robustness. In this paper, we propose a GaN Hetero Junction Field-Effect Transistor (HFET)-based isolated gate driver for GaN power devices with Drive-by-Microwave (DBM) technology, which can provide very compact GaN-GIT power systems owing to a gate driving by a wireless power transfer without an additional isolated voltage source. The proposed DBM gate driver can drive GaN-GIT power devices at a high switching frequency of 3 MHz with relatively low power consumption (∼1 W) and provides a short propagation delay less than 20 nsec.
{"title":"A1W power consumption GaN-based isolated gate driver for a 1.0 MHz GaN power system","authors":"Songbek Che, S. Nagai, N. Negoro, Yasufumi Kawai, O. Tabata, S. Enomoto, Y. Anda, T. Hatsuda","doi":"10.23919/ISPSD.2017.7988876","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988876","url":null,"abstract":"Fast switching operation of power electronics systems is significantly advantageous for reducing volume of passive components and increasing power density in the systems. Next generation power devices, such as GaN gate-injection transistor (GIT), are promising for high frequency operations and isolated gate driving is also highly recommended owing to its noise robustness. In this paper, we propose a GaN Hetero Junction Field-Effect Transistor (HFET)-based isolated gate driver for GaN power devices with Drive-by-Microwave (DBM) technology, which can provide very compact GaN-GIT power systems owing to a gate driving by a wireless power transfer without an additional isolated voltage source. The proposed DBM gate driver can drive GaN-GIT power devices at a high switching frequency of 3 MHz with relatively low power consumption (∼1 W) and provides a short propagation delay less than 20 nsec.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124109186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988889
F. Hsu, C. Yen, C. Hung, Hsiang-Ting Hung, Chwan-Ying Lee, L. Lee, Y. Huang, Tzong-Liang Chen, Pei-Ju Chuang
A junction barrier controlled Schottky rectifier integrated silicon carbide MOSFET (SiC JMOS) is proposed in this paper, which merged a double implanted MOSFET (DMOS) and junction barrier controlled Schottky diode (JBS) in a monolithic SiC device without any additional process and area penalty. JMOS device in this work exhibits a lower reverse conduction voltage drop than conventional SiC DMOS. There is a 47% improvement on VSD. There's also superior in dynamic performances such like lower reverse recovery charge (Qrr) and maximum reverse recovery current (IRMax) due to characteristics of unipolar devices. As a result, JMOS is 54% lower in Qrr and 40% lower in IRMax. The integrated JBS could also prevent the potential failure caused by the transformation of dislocation defects into stacking faults due to the recombination of injected minority carriers when parasitic body diode in SiC MOSFET was turned on. In this work, we make characteristics comparison and build a testing platform to verify the efficiency and reliability improvement of SiC JMOS from conventional SiC DMOS. The experiment result shows that we could gain better system performance and reliability with less cost and higher power density.
{"title":"High efficiency high reliability SiC MOSFET with monolithically integrated Schottky rectifier","authors":"F. Hsu, C. Yen, C. Hung, Hsiang-Ting Hung, Chwan-Ying Lee, L. Lee, Y. Huang, Tzong-Liang Chen, Pei-Ju Chuang","doi":"10.23919/ISPSD.2017.7988889","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988889","url":null,"abstract":"A junction barrier controlled Schottky rectifier integrated silicon carbide MOSFET (SiC JMOS) is proposed in this paper, which merged a double implanted MOSFET (DMOS) and junction barrier controlled Schottky diode (JBS) in a monolithic SiC device without any additional process and area penalty. JMOS device in this work exhibits a lower reverse conduction voltage drop than conventional SiC DMOS. There is a 47% improvement on VSD. There's also superior in dynamic performances such like lower reverse recovery charge (Qrr) and maximum reverse recovery current (IRMax) due to characteristics of unipolar devices. As a result, JMOS is 54% lower in Qrr and 40% lower in IRMax. The integrated JBS could also prevent the potential failure caused by the transformation of dislocation defects into stacking faults due to the recombination of injected minority carriers when parasitic body diode in SiC MOSFET was turned on. In this work, we make characteristics comparison and build a testing platform to verify the efficiency and reliability improvement of SiC JMOS from conventional SiC DMOS. The experiment result shows that we could gain better system performance and reliability with less cost and higher power density.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124116339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988995
I. Ji, Amaury Gendron-Hansen, Ming-Zhen Lee, E. Maxwell, B. Odekirk, D. Sdrulla, Changsoo Hong, A. Kashyap, F. Faheem
A novel 1200 V, 80 mΩ 4-H SiC power MOSFET with a shallow step p-body has been proposed for applications with highly rugged requirements. The innovative p-body design mitigates the problems arising due to the electric-field concentration at the corners that trigger the parasitic bipolar structure in conventional planar DMOS devices. TCAD simulations of the proposed device clearly demonstrate this improvement, along with significantly lower impact ionization rates at the corner of the p-body. The shallow step p-body approach, combined with a robust gate oxide and layout design, contributed to an industry-leading UIS capability of 2900 mJ of single pulse avalanche energy, and 5.8 μs of short circuit withstand time.
{"title":"Highly rugged 1200 V 80 mQ 4-H SiC power MOSFET","authors":"I. Ji, Amaury Gendron-Hansen, Ming-Zhen Lee, E. Maxwell, B. Odekirk, D. Sdrulla, Changsoo Hong, A. Kashyap, F. Faheem","doi":"10.23919/ISPSD.2017.7988995","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988995","url":null,"abstract":"A novel 1200 V, 80 mΩ 4-H SiC power MOSFET with a shallow step p-body has been proposed for applications with highly rugged requirements. The innovative p-body design mitigates the problems arising due to the electric-field concentration at the corners that trigger the parasitic bipolar structure in conventional planar DMOS devices. TCAD simulations of the proposed device clearly demonstrate this improvement, along with significantly lower impact ionization rates at the corner of the p-body. The shallow step p-body approach, combined with a robust gate oxide and layout design, contributed to an industry-leading UIS capability of 2900 mJ of single pulse avalanche energy, and 5.8 μs of short circuit withstand time.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124118291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988881
Fumio Takeuchi, Hirofumi Nagano, Toshihiro Sakamoto, K. Kimura, F. Matsuoka
To overcome the trade-off between breakdown voltage to negative bias and HBM robustness in fully isolated Nch-LDMOS, we found and utilized a new unique parameter for HBM robustness estimation, which focused on the electric field under the drain region when TLP pulse was applied. By using this unique index parameter, we successfully achieved the optimized Nch-LDMOS with keeping high breakdown voltage of 35.9 V to negative bias as well as high HBM robustness of 4700 V.
{"title":"HBM robustness optimization of fully isolated Nch-LDMOS for negative input voltage using unique index parameter","authors":"Fumio Takeuchi, Hirofumi Nagano, Toshihiro Sakamoto, K. Kimura, F. Matsuoka","doi":"10.23919/ISPSD.2017.7988881","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988881","url":null,"abstract":"To overcome the trade-off between breakdown voltage to negative bias and HBM robustness in fully isolated Nch-LDMOS, we found and utilized a new unique parameter for HBM robustness estimation, which focused on the electric field under the drain region when TLP pulse was applied. By using this unique index parameter, we successfully achieved the optimized Nch-LDMOS with keeping high breakdown voltage of 35.9 V to negative bias as well as high HBM robustness of 4700 V.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114321291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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