Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988946
Michael Kollmitzer, M. Olbrich, E. Barke
This paper proposes a point-to-point modeling scheme for Spice-based circuit simulation of parasitic coupling effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. Since minority carriers can diffuse over large distances in the common substrate and disturb circuits in their normal operation, a quantitative approach is necessary to address this parasitic effect early during design. An equivalent circuit based on the chip's design is extracted and the coupling effect between the perturbing devices and the susceptible nodes is represented by Verilog-AMS models. An automated layout extraction identifies the perturbators and the sensitive devices and determines the parameters for the models. The equations of the models are derived from calibrated TCAD simulations based on measurements of a dedicated test chip. Finally, the entire simulation flow is evaluated and the simulation results are compared to measurements of the chip.
{"title":"A circuit simulation flow for substrate minority carrier injection in smart power ICs","authors":"Michael Kollmitzer, M. Olbrich, E. Barke","doi":"10.23919/ISPSD.2017.7988946","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988946","url":null,"abstract":"This paper proposes a point-to-point modeling scheme for Spice-based circuit simulation of parasitic coupling effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. Since minority carriers can diffuse over large distances in the common substrate and disturb circuits in their normal operation, a quantitative approach is necessary to address this parasitic effect early during design. An equivalent circuit based on the chip's design is extracted and the coupling effect between the perturbing devices and the susceptible nodes is represented by Verilog-AMS models. An automated layout extraction identifies the perturbators and the sensitive devices and determines the parameters for the models. The equations of the models are derived from calibrated TCAD simulations based on measurements of a dedicated test chip. Finally, the entire simulation flow is evaluated and the simulation results are compared to measurements of the chip.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116295720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988981
D. Kinzer
Gallium Nitride is an emerging technology that is enabling major advances in power electronics. Power integrated circuits are now emerging in the market and showing unprecedented efficiency, density, and system cost advantages. This paper reviews the beginnings of power integrated circuit techniques, leading to present implementations in advanced IC products, and forecasts future directions for the new technology.
{"title":"GaN power IC technology: Past, present, and future","authors":"D. Kinzer","doi":"10.23919/ISPSD.2017.7988981","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988981","url":null,"abstract":"Gallium Nitride is an emerging technology that is enabling major advances in power electronics. Power integrated circuits are now emerging in the market and showing unprecedented efficiency, density, and system cost advantages. This paper reviews the beginnings of power integrated circuit techniques, leading to present implementations in advanced IC products, and forecasts future directions for the new technology.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127614932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988897
S. Wada, Katsumi Ikegaya, T. Oshima, Y. Kobayashi
A novel high/low-side hybrid output transistor with high thermal safe operating area (SOA) performance was developed. The output transistor was designed by alternatively arranging high- and low-side transistors to enhance the thermal diffusion from self-heated transistors. A 42% increase in the failure energy of the conventional transistor was obtained at 300-μs short-circuit duration, and a further 10–15% improvement was obtained by introducing a Cu redistribution layer (Cu-RDL) of power metal. A 3D-thermal simulation demonstrated that the peak junction temperature was reduced by around 100°C in the hybrid output transistor during clamp inductive switching. The energy capability of the hybrid output transistor also improved from 18 to 31 mJ in the solenoid driver circuit.
{"title":"High/low-side hybrid output transistor with high thermal-SOA","authors":"S. Wada, Katsumi Ikegaya, T. Oshima, Y. Kobayashi","doi":"10.23919/ISPSD.2017.7988897","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988897","url":null,"abstract":"A novel high/low-side hybrid output transistor with high thermal safe operating area (SOA) performance was developed. The output transistor was designed by alternatively arranging high- and low-side transistors to enhance the thermal diffusion from self-heated transistors. A 42% increase in the failure energy of the conventional transistor was obtained at 300-μs short-circuit duration, and a further 10–15% improvement was obtained by introducing a Cu redistribution layer (Cu-RDL) of power metal. A 3D-thermal simulation demonstrated that the peak junction temperature was reduced by around 100°C in the hybrid output transistor during clamp inductive switching. The energy capability of the hybrid output transistor also improved from 18 to 31 mJ in the solenoid driver circuit.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126480901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988984
Ivana Kovačević-Badstübner, T. Ziemann, Bhagyalakshmi Kakarla, U. Grossner
Optimized low-inductive layouting of the package interconnections and external PCBs and bus-bars are necessary to benefit from Silicon Carbide (SiC) power devices, which allow inherently very fast switching transitions. In this paper, a comprehensive modeling procedure for highly accurate virtual dynamic characterization of discrete SiC power devices is described taking into account the 3D geometry of the internal and external interconnections of package as input. The modeling requirements are discussed on an example of a commercial 1.2 kV, 80 mΩ SiC Power MOSFET in a standard TO-247 package (Cree C2M0080120D). The software tools, Simplorer, Saber, Q3D and LTSpice, commonly used for modeling and simulation of power modules, are evaluated with respect to their modeling capabilities for SiC devices.
{"title":"Highly accurate virtual dynamic characterization of discrete SiC power devices","authors":"Ivana Kovačević-Badstübner, T. Ziemann, Bhagyalakshmi Kakarla, U. Grossner","doi":"10.23919/ISPSD.2017.7988984","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988984","url":null,"abstract":"Optimized low-inductive layouting of the package interconnections and external PCBs and bus-bars are necessary to benefit from Silicon Carbide (SiC) power devices, which allow inherently very fast switching transitions. In this paper, a comprehensive modeling procedure for highly accurate virtual dynamic characterization of discrete SiC power devices is described taking into account the 3D geometry of the internal and external interconnections of package as input. The modeling requirements are discussed on an example of a commercial 1.2 kV, 80 mΩ SiC Power MOSFET in a standard TO-247 package (Cree C2M0080120D). The software tools, Simplorer, Saber, Q3D and LTSpice, commonly used for modeling and simulation of power modules, are evaluated with respect to their modeling capabilities for SiC devices.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126386707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988967
Tianjiao Liu, Runtao Ning, T.T.Y. Wong, Z. Shen
This paper discusses a new technique to accurately characterize parasitic inductances of discrete fast switching MOSFETs based on S-parameters measurement using two-port vector network analyzer. The method is validated through case studies of 1200V SiC MOSFET in TO-247 and 30V silicon trench MOSFET in SO-8 package.
本文讨论了一种基于双端口矢量网络分析仪s参数测量的精确表征离散型快速开关mosfet寄生电感的新技术。通过对TO-247封装的1200V SiC MOSFET和SO-8封装的30V硅沟槽MOSFET的案例研究，验证了该方法的有效性。
{"title":"A new characterization technique for extracting parasitic inductances of fast switching power MOSFETs using two-port vector network analyzer","authors":"Tianjiao Liu, Runtao Ning, T.T.Y. Wong, Z. Shen","doi":"10.23919/ISPSD.2017.7988967","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988967","url":null,"abstract":"This paper discusses a new technique to accurately characterize parasitic inductances of discrete fast switching MOSFETs based on S-parameters measurement using two-port vector network analyzer. The method is validated through case studies of 1200V SiC MOSFET in TO-247 and 30V silicon trench MOSFET in SO-8 package.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133049874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988885
Daisuke Arai, S. Hisada, Mizue Yamaji, S. Kunori
The switching waveform of superjunction (SJ) Si-MOSFETs used in inductive load circuit was investigated. At the turn-off phase, a hump appears in the drain current. Both experiment and simulation indicated that the amplitude of the current hump drastically depends on the charge imbalance (CIB). On the other hand, at the turn-on phase, calculation showed that the dependence of di/dt on CIB is opposite in the cases of planar or trench gate structure. These changes of switching waveform are caused by the electrostatic potential distribution around the gate structure. Based on the analysis we propose non-sensitive to CIB device structures in this paper.
{"title":"Dependence of switching waveform on charge imbalance in superjunction MOSFET used in inductive load circuit","authors":"Daisuke Arai, S. Hisada, Mizue Yamaji, S. Kunori","doi":"10.23919/ISPSD.2017.7988885","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988885","url":null,"abstract":"The switching waveform of superjunction (SJ) Si-MOSFETs used in inductive load circuit was investigated. At the turn-off phase, a hump appears in the drain current. Both experiment and simulation indicated that the amplitude of the current hump drastically depends on the charge imbalance (CIB). On the other hand, at the turn-on phase, calculation showed that the dependence of di/dt on CIB is opposite in the cases of planar or trench gate structure. These changes of switching waveform are caused by the electrostatic potential distribution around the gate structure. Based on the analysis we propose non-sensitive to CIB device structures in this paper.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127800475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988956
Jin Wei, Yuru Wang, Meng Zhang, Huaping Jiang, K. J. Chen
A trench/planar MOSFET (TP-MOS) is proposed in this work as a high speed switching device. The device is comprehensively studied with numerical simulations, and comparisons are made with the conventional MOSFET (C-MOS) and the split-gate MOSFET (SG-MOS). Compared to the C-MOS, the removal of the MOS-structure above the JFET region results in a dramatic reduction of the reverse transfer capacitance (Crss) in the SG-MOS and TP-MOS. The top p-base in the TP-MOS expedites the depletion in the JFET region, which helps further reduce the Crss and alleviates the electric field crowding. The additional trench channels in the TP-MOS lowers the total channel resistance, which compensates the increase of JFET resistance caused by the absence of the electron accumulation layer under the MOS-structure. Therefore, the TP-MOS achieves the best RON-Crss trade-off.
{"title":"High-speed power MOSFET with low reverse transfer capacitance using a trench/planar gate architecture","authors":"Jin Wei, Yuru Wang, Meng Zhang, Huaping Jiang, K. J. Chen","doi":"10.23919/ISPSD.2017.7988956","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988956","url":null,"abstract":"A trench/planar MOSFET (TP-MOS) is proposed in this work as a high speed switching device. The device is comprehensively studied with numerical simulations, and comparisons are made with the conventional MOSFET (C-MOS) and the split-gate MOSFET (SG-MOS). Compared to the C-MOS, the removal of the MOS-structure above the JFET region results in a dramatic reduction of the reverse transfer capacitance (Crss) in the SG-MOS and TP-MOS. The top p-base in the TP-MOS expedites the depletion in the JFET region, which helps further reduce the Crss and alleviates the electric field crowding. The additional trench channels in the TP-MOS lowers the total channel resistance, which compensates the increase of JFET resistance caused by the absence of the electron accumulation layer under the MOS-structure. Therefore, the TP-MOS achieves the best RON-Crss trade-off.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127243721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988877
D. Colin, N. Rouger
The paper presents an integrated digital communication technique for sending gate signal and gate driver configuration data. As an application example, the developed CMOS gate driver carries the digital data through an optical isolation, in the context of wide bandgap power transistors. The receiver chip integrates all the required functions from the optical receiver to the signal processing circuit (SPC) and the logic control units. The standard AMS HV 0.18 μm CMOS technology is selected for proof of concept and prototyping. A variable frame length serial communication protocol is implemented with an integrated clock to transfer a 4 bit commutation order within 56 ns and an 8 bit configuration data within 84 ns (140 Mbps). Hence, a segmented output stage buffer can be configured by light, thus dynamically changing the gate resistor value through the isolation barrier.
{"title":"High speed digital optical signal transferforpower transistor gate driver applications","authors":"D. Colin, N. Rouger","doi":"10.23919/ISPSD.2017.7988877","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988877","url":null,"abstract":"The paper presents an integrated digital communication technique for sending gate signal and gate driver configuration data. As an application example, the developed CMOS gate driver carries the digital data through an optical isolation, in the context of wide bandgap power transistors. The receiver chip integrates all the required functions from the optical receiver to the signal processing circuit (SPC) and the logic control units. The standard AMS HV 0.18 μm CMOS technology is selected for proof of concept and prototyping. A variable frame length serial communication protocol is implemented with an integrated clock to transfer a 4 bit commutation order within 56 ns and an 8 bit configuration data within 84 ns (140 Mbps). Hence, a segmented output stage buffer can be configured by light, thus dynamically changing the gate resistor value through the isolation barrier.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132385257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988951
Song Yuan, B. Duan, H. Cai, Zhen Cao, Yintang Yang
A novel lateral double-diffused MOSFET (LDMOS) is proposed with the assisted deplete-substrate layer (ADSL) under the drain electrode for the first time in this letter. Since the introduced layer could assist deplete the substrate, both the lateral and the vertical electric field distributions would be improved resulting from the electric field modulation effect, the breakdown characteristic is significantly improved. The results show that the breakdown voltage (BV) of the proposed ADSL LDMOS is increased from 464 V of the conventional LDMOS to 812 V with the same 70 μm drift region length. Furthermore, the figure-of-merit (FOM) for ADSL LDMOS and the conventional LDMOS are 1.397MW/cm2 and 0.645 MW/cm2, respectively. The ADSL LDMOS has a much better performance than the conventional LDMOS.
{"title":"Novel LDMOS with assisted deplete-substrate layer consist of super junction under the drain","authors":"Song Yuan, B. Duan, H. Cai, Zhen Cao, Yintang Yang","doi":"10.23919/ISPSD.2017.7988951","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988951","url":null,"abstract":"A novel lateral double-diffused MOSFET (LDMOS) is proposed with the assisted deplete-substrate layer (ADSL) under the drain electrode for the first time in this letter. Since the introduced layer could assist deplete the substrate, both the lateral and the vertical electric field distributions would be improved resulting from the electric field modulation effect, the breakdown characteristic is significantly improved. The results show that the breakdown voltage (BV) of the proposed ADSL LDMOS is increased from 464 V of the conventional LDMOS to 812 V with the same 70 μm drift region length. Furthermore, the figure-of-merit (FOM) for ADSL LDMOS and the conventional LDMOS are 1.397MW/cm2 and 0.645 MW/cm2, respectively. The ADSL LDMOS has a much better performance than the conventional LDMOS.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132266570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988948
V. Sodan, S. Stoffels, H. Oprins, M. Baelmans, S. Decoutere, I. De Wolf
In this work, we present a novel concept of electro-thermal modelling of GaN lateral power devices. Based on a distributed modelling approach, where a thermal model and electrical compact model are coupled, a new distributed electro-thermal model has been developed. The model provides a detailed insight in the distributed electro-thermal behaviour during steady-state and transient (power switching) regime with a significant reduction of computational time compared to alternative models existing in literature. The model has been validated with experiments where p-GaN devices are tested under standard switching conditions. The waveforms and temperature readings predicted by the model show an excellent agreement with the experiments.
{"title":"Distributed electro-thermal model based on fast and scalable algorithm for GaN power devices and circuit simulations","authors":"V. Sodan, S. Stoffels, H. Oprins, M. Baelmans, S. Decoutere, I. De Wolf","doi":"10.23919/ISPSD.2017.7988948","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988948","url":null,"abstract":"In this work, we present a novel concept of electro-thermal modelling of GaN lateral power devices. Based on a distributed modelling approach, where a thermal model and electrical compact model are coupled, a new distributed electro-thermal model has been developed. The model provides a detailed insight in the distributed electro-thermal behaviour during steady-state and transient (power switching) regime with a significant reduction of computational time compared to alternative models existing in literature. The model has been validated with experiments where p-GaN devices are tested under standard switching conditions. The waveforms and temperature readings predicted by the model show an excellent agreement with the experiments.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126603327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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