Pub Date : 2020-10-01DOI: 10.1109/ICCCN.2005.1523784
L. Dasilva
Welcome to the 7th International Conference on Information Technology—New Generations (ITNG 2010). It is a pleasure to report that we have another successful year for the ITNG 2010. Gaining popularity and recognition in the IT community around the globe, the conference was able to attract 753 papers from authors worldwide. The papers were reviewed for their technical soundness, originality, clarity, and relevance to the conference. A total of 166 scientists participated in the review process, and each paper was reviewed by at least two independent reviewers. The overall acceptance rate was 28%. The articles in this proceedings address the most recent advances in such areas as E-Learning and Education, Software Engineering, Information Security, High Performance Computing Architectures, Internet, Wireless Communications, Security, Data Mining, Informatics, E-Commerce, Digital Circuit Design, and Image Processing. The conference features two keynote speakers on Monday and Tuesday. The first conference keynote is presented by Dr. Tom Malzbender from Hewlett Packard Labs and is entitled “Reflectance Imaging: A Simple Approach to Seeing Surface Detail.” The other keynote is given by Dr. Eugene Schultz, the Chief Technology Officer of Emagined Security. His talk is entitled “Data Security Breaches: An Unstoppable Epidemic?” As customary, the presentations for Monday and Tuesday are organized in three meeting rooms simultaneously, covering a total of 12 sessions on each day. Poster presentations are scheduled for the morning and afternoon of these days. The award ceremony, conference reception, and dinner are scheduled for Tuesday evening. Two parallel sessions will continue on Wednesday. Many people contributed to the success of this year’s conference by organizing symposia or technical tracks for the ITNG. My sincere thanks go to symposium and major track organizers and associate editors, namely, Drs. Jameela Al-Jaroodi, Azita Bahrami, Buket Barkana, Alain Bretto, Narayan Debnath, Luiz Alberto Vieira Dias, Mohammad Eyadat, Wenying Feng, Moses Garuba, Dion Goh, Ray Hashemi, James McCaffrey, Nader Mohamed, Yenumula Reddy, Inci Saricicek, Elhadi Shakshuki, and Xiaolong Wu. Others who were responsible for soliciting, reviewing, and handling the papers submitted to their respective sessions include Drs. Wei-Lung Chang, Jagadeesh Nandigam, Jesús Ubaldo Quevedo, Mehrdad S. Sharbaf, Jarrod Trevathan, Kurschl Werner, and Mei Yang. The help and support of the IEEE Computer Society in preparing the ITNG proceedings is specially appreciated. Many thanks are due to Andrea L. Thibault-Sanchez, who was responsible for Quotes and Acquisitions, issues related to the proceedings. I gratefully acknowledge the gracious assistance of the IEEE Computer Society and Bob Werner, editor, who did an excellent job in publishing the proceedings in a timely manner. He was patient with our last-minute changes to the program. Furthermore, we acknowledge the great efforts of the conf
{"title":"Message from the general chair","authors":"L. Dasilva","doi":"10.1109/ICCCN.2005.1523784","DOIUrl":"https://doi.org/10.1109/ICCCN.2005.1523784","url":null,"abstract":"Welcome to the 7th International Conference on Information Technology—New Generations (ITNG 2010). It is a pleasure to report that we have another successful year for the ITNG 2010. Gaining popularity and recognition in the IT community around the globe, the conference was able to attract 753 papers from authors worldwide. The papers were reviewed for their technical soundness, originality, clarity, and relevance to the conference. A total of 166 scientists participated in the review process, and each paper was reviewed by at least two independent reviewers. The overall acceptance rate was 28%. The articles in this proceedings address the most recent advances in such areas as E-Learning and Education, Software Engineering, Information Security, High Performance Computing Architectures, Internet, Wireless Communications, Security, Data Mining, Informatics, E-Commerce, Digital Circuit Design, and Image Processing. The conference features two keynote speakers on Monday and Tuesday. The first conference keynote is presented by Dr. Tom Malzbender from Hewlett Packard Labs and is entitled “Reflectance Imaging: A Simple Approach to Seeing Surface Detail.” The other keynote is given by Dr. Eugene Schultz, the Chief Technology Officer of Emagined Security. His talk is entitled “Data Security Breaches: An Unstoppable Epidemic?” As customary, the presentations for Monday and Tuesday are organized in three meeting rooms simultaneously, covering a total of 12 sessions on each day. Poster presentations are scheduled for the morning and afternoon of these days. The award ceremony, conference reception, and dinner are scheduled for Tuesday evening. Two parallel sessions will continue on Wednesday. Many people contributed to the success of this year’s conference by organizing symposia or technical tracks for the ITNG. My sincere thanks go to symposium and major track organizers and associate editors, namely, Drs. Jameela Al-Jaroodi, Azita Bahrami, Buket Barkana, Alain Bretto, Narayan Debnath, Luiz Alberto Vieira Dias, Mohammad Eyadat, Wenying Feng, Moses Garuba, Dion Goh, Ray Hashemi, James McCaffrey, Nader Mohamed, Yenumula Reddy, Inci Saricicek, Elhadi Shakshuki, and Xiaolong Wu. Others who were responsible for soliciting, reviewing, and handling the papers submitted to their respective sessions include Drs. Wei-Lung Chang, Jagadeesh Nandigam, Jesús Ubaldo Quevedo, Mehrdad S. Sharbaf, Jarrod Trevathan, Kurschl Werner, and Mei Yang. The help and support of the IEEE Computer Society in preparing the ITNG proceedings is specially appreciated. Many thanks are due to Andrea L. Thibault-Sanchez, who was responsible for Quotes and Acquisitions, issues related to the proceedings. I gratefully acknowledge the gracious assistance of the IEEE Computer Society and Bob Werner, editor, who did an excellent job in publishing the proceedings in a timely manner. He was patient with our last-minute changes to the program. Furthermore, we acknowledge the great efforts of the conf","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126335693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.23919/ISPSD.2017.7988925
T. Oeder, A. Castellazzi, M. Pfost
In this paper, the short-circuit robustness of a normally-off GaN HEMT is investigated in relation to applied bias conditions and pulse duration. The results align with previous studies on normally-on devices in highlighting an electrical type of failure. Here, however, the relevance of the specific gate-drive circuit design and corresponding device operational conditions is demonstrated. A gate-bias dependence (GBD) of the failure, correlated to the applied drain-source voltage, is introduced as a novel specific feature for the p-Gate type device.
{"title":"Experimental study of the short-circuit performance for a 600V normally-off p-gate GaN HEMT","authors":"T. Oeder, A. Castellazzi, M. Pfost","doi":"10.23919/ISPSD.2017.7988925","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988925","url":null,"abstract":"In this paper, the short-circuit robustness of a normally-off GaN HEMT is investigated in relation to applied bias conditions and pulse duration. The results align with previous studies on normally-on devices in highlighting an electrical type of failure. Here, however, the relevance of the specific gate-drive circuit design and corresponding device operational conditions is demonstrated. A gate-bias dependence (GBD) of the failure, correlated to the applied drain-source voltage, is introduced as a novel specific feature for the p-Gate type device.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123178881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.23919/ISPSD.2017.7988977
J. González, O. Alatise, P. Mawby, A. M. Aliyu, A. Castellazzi
Pressure contact packages have demonstrated an improved reliability for silicon devices due to the elimination of the weak elements of the packaging, namely wirebonds and solder. This packaging approach has not yet been widely studied for SiC devices, however, it is of high interest for applications like HVDC or rail traction, where the wide bandgap properties of SiC devices can be fully exploited and high reliability is critical. Current IGBT press-pack modules use Si PIN diodes for enabling reverse conduction, however, the use of SiC Schottky diodes would be beneficial given their better characteristics including low switching losses and lower zero temperature coefficient (ZTC) for electrothermal stability of diodes in parallel. A prototype for the evaluation of SiC Schottky diodes using pressure contacts has been designed, built and tested for both single die and multiple die.
{"title":"Pressure contact multi-chip packaging of SiC Schottky diodes","authors":"J. González, O. Alatise, P. Mawby, A. M. Aliyu, A. Castellazzi","doi":"10.23919/ISPSD.2017.7988977","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988977","url":null,"abstract":"Pressure contact packages have demonstrated an improved reliability for silicon devices due to the elimination of the weak elements of the packaging, namely wirebonds and solder. This packaging approach has not yet been widely studied for SiC devices, however, it is of high interest for applications like HVDC or rail traction, where the wide bandgap properties of SiC devices can be fully exploited and high reliability is critical. Current IGBT press-pack modules use Si PIN diodes for enabling reverse conduction, however, the use of SiC Schottky diodes would be beneficial given their better characteristics including low switching losses and lower zero temperature coefficient (ZTC) for electrothermal stability of diodes in parallel. A prototype for the evaluation of SiC Schottky diodes using pressure contacts has been designed, built and tested for both single die and multiple die.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115976171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.23919/ISPSD.2017.7988917
G. Sabui, V. Zubialevich, M. White, P. Pampili, P. Parbrook, M. McLaren, M. Arredondo-Arechavala, Z. Shen
Design considerations for vertical Gallium Nitride (GaN) nanowire Schottky barrier diodes (NWSBDs) for high voltage applications is discussed in this paper. Preliminary quasi-vertical NWSBDs fabricated on a Sapphire substrate show rectifying properties with breakdown voltage of 100 V. The principle of dielectric Reduced SURface Field (RESURF) which is naturally compatible with the NW structure, is utilized to block high voltages (> 600 V) within the fabrication constraints of nano-pillar height and drift doping concentration. Design considerations for the NWSBD is explored through 3D TCAD simulations. TCAD simulations show the NWSBDs can block voltages upward of 700 V with very low on-resistance with optimal design. The measured and simulated results are compared with state of the art GaN devices to provide an understanding of the true potential of the GaN NW architecture as power devices offering high breakdown voltages and low on-state resistance and a reliable device operation, all on a vertical architecture and a non-native substrate.
{"title":"Design considerations of vertical GaN nanowire Schottky barrier diodes","authors":"G. Sabui, V. Zubialevich, M. White, P. Pampili, P. Parbrook, M. McLaren, M. Arredondo-Arechavala, Z. Shen","doi":"10.23919/ISPSD.2017.7988917","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988917","url":null,"abstract":"Design considerations for vertical Gallium Nitride (GaN) nanowire Schottky barrier diodes (NWSBDs) for high voltage applications is discussed in this paper. Preliminary quasi-vertical NWSBDs fabricated on a Sapphire substrate show rectifying properties with breakdown voltage of 100 V. The principle of dielectric Reduced SURface Field (RESURF) which is naturally compatible with the NW structure, is utilized to block high voltages (> 600 V) within the fabrication constraints of nano-pillar height and drift doping concentration. Design considerations for the NWSBD is explored through 3D TCAD simulations. TCAD simulations show the NWSBDs can block voltages upward of 700 V with very low on-resistance with optimal design. The measured and simulated results are compared with state of the art GaN devices to provide an understanding of the true potential of the GaN NW architecture as power devices offering high breakdown voltages and low on-state resistance and a reliable device operation, all on a vertical architecture and a non-native substrate.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125248999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.23919/ISPSD.2017.7988976
A. M. Aliyu, B. Mouawad, A. Castellazzi, P. Rajaguru, C. Bailey, V. Pathirana, N. Udugampola, T. Trajkovic, F. Udrea
This paper presents a novel chip on board assembly design for an integrated power switch, based on high power density 800V silicon lateral insulated gate bipolar transistor (Si LIGBT) technology. LIGBTs offer much higher current densities (5-lOX), significantly lower leakage currents, lower parasitic device capacitances and gate charge compared to conventional vertical MOSFETs commonly used in LED drivers. The higher voltage ratings offered (up to 1kV), the development of high voltage interconnection between parallel IGBTs, self-isolated nature and absence of termination region unlike in a vertical MOSFET makes these devices ideal for ultra-compact, low bill of materials (BOM) count LED drives. Chip on-board LIGBTs also offer significant advantages over MOSFETs due to high temperatures seen on most of the LED lamp enclosures as the LIGBT's on-state losses increase only marginally with temperature. The design is based on a built-in reliability approach which focuses on a compact LED driver as a case-study of a cost-sensitive large volume production item.
{"title":"Chip-on-board assembly of 800V Si L-IGBTs for high performance ultra-compact LED drivers","authors":"A. M. Aliyu, B. Mouawad, A. Castellazzi, P. Rajaguru, C. Bailey, V. Pathirana, N. Udugampola, T. Trajkovic, F. Udrea","doi":"10.23919/ISPSD.2017.7988976","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988976","url":null,"abstract":"This paper presents a novel chip on board assembly design for an integrated power switch, based on high power density 800V silicon lateral insulated gate bipolar transistor (Si LIGBT) technology. LIGBTs offer much higher current densities (5-lOX), significantly lower leakage currents, lower parasitic device capacitances and gate charge compared to conventional vertical MOSFETs commonly used in LED drivers. The higher voltage ratings offered (up to 1kV), the development of high voltage interconnection between parallel IGBTs, self-isolated nature and absence of termination region unlike in a vertical MOSFET makes these devices ideal for ultra-compact, low bill of materials (BOM) count LED drives. Chip on-board LIGBTs also offer significant advantages over MOSFETs due to high temperatures seen on most of the LED lamp enclosures as the LIGBT's on-state losses increase only marginally with temperature. The design is based on a built-in reliability approach which focuses on a compact LED driver as a case-study of a cost-sensitive large volume production item.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126430092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-21DOI: 10.23919/ISPSD.2017.7988902
P. Moens, M. Uren, A. Banerjee, M. Meneghini, B. Padmanabhan, W. Jeon, S. Karboyan, M. Kuball, G. Meneghesso, E. Zanoni, M. Tack
Through optimization of the GaN buffer structure, 650V rated AlGaN/GaN power devices with negative dynamic Ron are obtained. By judicious tuning of the resistivity of the [C]-doped and unintentionally-doped (UID) layers (i.e. the charge transport properties in these layers), positive rather than the deleterious negative charged trapping can be achieved. Long term reliability testing shows that the positive charge can be retained for days.
{"title":"Negative dynamic Ron in AlGaN/GaN power devices","authors":"P. Moens, M. Uren, A. Banerjee, M. Meneghini, B. Padmanabhan, W. Jeon, S. Karboyan, M. Kuball, G. Meneghesso, E. Zanoni, M. Tack","doi":"10.23919/ISPSD.2017.7988902","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988902","url":null,"abstract":"Through optimization of the GaN buffer structure, 650V rated AlGaN/GaN power devices with negative dynamic Ron are obtained. By judicious tuning of the resistivity of the [C]-doped and unintentionally-doped (UID) layers (i.e. the charge transport properties in these layers), positive rather than the deleterious negative charged trapping can be achieved. Long term reliability testing shows that the positive charge can be retained for days.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130667193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-28DOI: 10.23919/ISPSD.2017.7988986
A. Fayyaz, A. Castellazzi, G. Romano, M. Riccio, A. Irace, J. Urresti, N. Wright
This paper investigates the effect of negative gate bias voltage (Vgs) on the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs. The device's ability to withstand energy dissipation during avalanche regime is a connoting figure of merit for all applications requiring load dumping and/or benefiting from snubber-less converter design. The superior material properties of SiC material means that SiC MOSFETs even at 1200V exhibit significant intrinsic avalanche robustness.
{"title":"Influence of gate bias on the avalanche ruggedness of SiC power MOSFETs","authors":"A. Fayyaz, A. Castellazzi, G. Romano, M. Riccio, A. Irace, J. Urresti, N. Wright","doi":"10.23919/ISPSD.2017.7988986","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988986","url":null,"abstract":"This paper investigates the effect of negative gate bias voltage (Vgs) on the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs. The device's ability to withstand energy dissipation during avalanche regime is a connoting figure of merit for all applications requiring load dumping and/or benefiting from snubber-less converter design. The superior material properties of SiC material means that SiC MOSFETs even at 1200V exhibit significant intrinsic avalanche robustness.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121686195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988966
Hsin-Liang Liu, Z. Jhou, Shih-Teng Huang, Shu‐Wha Lin, Ke-Feng Lin, Chiu-Te Lee, Chih-Chong Wang
This paper demonstrated a novel LDMOS with gate-connected shielding-contact structure, no extra mask or process is needed. TCAD simulation reveals lower electrical potential and impact ionization with the proposed structure. Ron-sp/BVD ratio reduction and significant HCl SOA improvement have been verified on real Silicon. Newly layout with Slot-Poly design has been investigated for better process control as well.
{"title":"A novel high-voltage LDMOS with shielding-contact structure for HCl SOA enhancement","authors":"Hsin-Liang Liu, Z. Jhou, Shih-Teng Huang, Shu‐Wha Lin, Ke-Feng Lin, Chiu-Te Lee, Chih-Chong Wang","doi":"10.23919/ISPSD.2017.7988966","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988966","url":null,"abstract":"This paper demonstrated a novel LDMOS with gate-connected shielding-contact structure, no extra mask or process is needed. TCAD simulation reveals lower electrical potential and impact ionization with the proposed structure. Ron-sp/BVD ratio reduction and significant HCl SOA improvement have been verified on real Silicon. Newly layout with Slot-Poly design has been investigated for better process control as well.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115608884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988963
Tsung-Yi Huang, Chien-Hao Huang, Chih-Fang Huang, Jing-Meng Liu, K. Lo, Chia-Hui Cheng, Jheng-Yi Jiang, T. Tsai, Ting-Wei Liao, J. Gong
The Ron sp of a DMOS operated at high side (Ron_sp_HS) in the power management ICs is usually underestimated by taking the measured value at low side operation (Ron_sp_LS). The Ron_sp_HS is increased drastically when a revise voltage is applied between drift region and substrate because the drift-region is depleted and the current path is narrowed. In this paper, a novel structure with a varying-junction-depth profile in the drift region is proposed to suppress the increase of Ron_sp_HS by adding a partial n-type buried layer (NBL) under the drain region. The drift region of HS-DMOS will generate a gradual pinch-off region from channel to drain when it is operated at 80V under high side operations, and the increased percentage in Ron_sp_HS is suppressed from 128% to 79% because it allows a wider electron current flow through the neutral region of the drift region in the proposed structure.
{"title":"A novel 80 V HS-DMOS with gradual-RESURF profile to reduce Ron_sp for high-side operation","authors":"Tsung-Yi Huang, Chien-Hao Huang, Chih-Fang Huang, Jing-Meng Liu, K. Lo, Chia-Hui Cheng, Jheng-Yi Jiang, T. Tsai, Ting-Wei Liao, J. Gong","doi":"10.23919/ISPSD.2017.7988963","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988963","url":null,"abstract":"The Ron sp of a DMOS operated at high side (Ron_sp_HS) in the power management ICs is usually underestimated by taking the measured value at low side operation (Ron_sp_LS). The Ron_sp_HS is increased drastically when a revise voltage is applied between drift region and substrate because the drift-region is depleted and the current path is narrowed. In this paper, a novel structure with a varying-junction-depth profile in the drift region is proposed to suppress the increase of Ron_sp_HS by adding a partial n-type buried layer (NBL) under the drain region. The drift region of HS-DMOS will generate a gradual pinch-off region from channel to drain when it is operated at 80V under high side operations, and the increased percentage in Ron_sp_HS is suppressed from 128% to 79% because it allows a wider electron current flow through the neutral region of the drift region in the proposed structure.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127363206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988929
Jan Fuhrmann, David Hammes, H. Eckel
A harsh high-voltage diode commutation as a result of a short circuit can destroy the diode. The ruggedness of the diode is given by the cathode design which can suppress an cathode-side filament. Measurements on 3.3-kV and 6.5-kV diodes with and without improved cathode design show the diode behavior during the short. The results are compared and similarities are found. Without an improved cathode a failure in succession of a cathode-side filament can be observed. This behavior is simulated and confirms the destruction mechanism.
{"title":"High-voltage diode robustness during short-circuit type III","authors":"Jan Fuhrmann, David Hammes, H. Eckel","doi":"10.23919/ISPSD.2017.7988929","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988929","url":null,"abstract":"A harsh high-voltage diode commutation as a result of a short circuit can destroy the diode. The ruggedness of the diode is given by the cathode design which can suppress an cathode-side filament. Measurements on 3.3-kV and 6.5-kV diodes with and without improved cathode design show the diode behavior during the short. The results are compared and similarities are found. Without an improved cathode a failure in succession of a cathode-side filament can be observed. This behavior is simulated and confirms the destruction mechanism.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123245836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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