Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988921
Y. Eum, K. Oyama, N. Otake, Shinichi Hoshi
A new MOS-HFET structure of a GaN power device for highly reliable GaN MOS gates has been designed. A normally-on JFET structure is fabricated between the gate and drain of the GaN MOS-HFET. By using this technology, the reliability of the gate insulator is greatly improved under the high drain voltage of the blocking-state. The new GaN MOS-HFET also reduces saturation current in the short-circuit condition by about 30%. It is expected that this new device improves the tolerance characteristics in the short-circuit condition without the on-resistance penalty associated with conventional structures.
{"title":"Highly reliable GaN MOS-HFET with high short-circuit capability","authors":"Y. Eum, K. Oyama, N. Otake, Shinichi Hoshi","doi":"10.23919/ISPSD.2017.7988921","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988921","url":null,"abstract":"A new MOS-HFET structure of a GaN power device for highly reliable GaN MOS gates has been designed. A normally-on JFET structure is fabricated between the gate and drain of the GaN MOS-HFET. By using this technology, the reliability of the gate insulator is greatly improved under the high drain voltage of the blocking-state. The new GaN MOS-HFET also reduces saturation current in the short-circuit condition by about 30%. It is expected that this new device improves the tolerance characteristics in the short-circuit condition without the on-resistance penalty associated with conventional structures.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125159005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988931
H. Felsl, F.-J. Niedemostheide, H. Schulze
The doping profile of the field-stop zone influences the static characteristics (Vce, sat, Vbr) and the dynamic switching characteristics (dic/dt, dVCE/dt, softness) of IGBTs. Furthermore, the short-circuit ruggedness is strongly influenced by the rear side structure of the IGET. In this work, box-like field-stop profiles in combination with a constant p-emitter were analyzed by TCAD simulations. The findings were used to optimize and realize field-stop profiles by proton implantation with the focus to achieve an improved short-circuit ruggedness at the same softness.
{"title":"IGBT field-stop design for good short circuit ruggedness and a better trade-off with respect to static and dynamic switching characteristics","authors":"H. Felsl, F.-J. Niedemostheide, H. Schulze","doi":"10.23919/ISPSD.2017.7988931","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988931","url":null,"abstract":"The doping profile of the field-stop zone influences the static characteristics (Vce, sat, Vbr) and the dynamic switching characteristics (dic/dt, dVCE/dt, softness) of IGBTs. Furthermore, the short-circuit ruggedness is strongly influenced by the rear side structure of the IGET. In this work, box-like field-stop profiles in combination with a constant p-emitter were analyzed by TCAD simulations. The findings were used to optimize and realize field-stop profiles by proton implantation with the focus to achieve an improved short-circuit ruggedness at the same softness.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131109509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988904
D. Peters, R. Siemieniec, T. Aichinger, T. Basler, R. Esteve, W. Bergner, Daniel Kueck
This paper describes a novel SiC trench MOSFET concept. The device is designed to balance low conduction losses with Si-IGBT like reliability. Basic features of the static and dynamic performance as well as short circuit capability of the 45mΩ/1200 V CoolSiC™ MOSFET are presented. The favorable temperature behavior of the on-state resistance combined with a low sensitivity of the switching energies to temperature simplify the design-in. Long-term gate oxide tests reveal a very low extrinsic failure rate well matching the requirements of industrial applications.
本文提出了一种新颖的碳化硅沟槽MOSFET概念。该器件旨在平衡低导通损耗和Si-IGBT的可靠性。介绍了45mΩ/1200 V CoolSiC™MOSFET的静态和动态性能的基本特征以及短路能力。导通电阻良好的温度特性，加上开关能量对温度的低灵敏度，简化了设计。长期的栅极氧化物测试表明，其外部故障率非常低，符合工业应用的要求。
{"title":"Performance and ruggedness of 1200V SiC — Trench — MOSFET","authors":"D. Peters, R. Siemieniec, T. Aichinger, T. Basler, R. Esteve, W. Bergner, Daniel Kueck","doi":"10.23919/ISPSD.2017.7988904","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988904","url":null,"abstract":"This paper describes a novel SiC trench MOSFET concept. The device is designed to balance low conduction losses with Si-IGBT like reliability. Basic features of the static and dynamic performance as well as short circuit capability of the 45mΩ/1200 V CoolSiC™ MOSFET are presented. The favorable temperature behavior of the on-state resistance combined with a low sensitivity of the switching energies to temperature simplify the design-in. Long-term gate oxide tests reveal a very low extrinsic failure rate well matching the requirements of industrial applications.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131534604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988958
C. Schmidt, G. Spitzlsperger
A novel concept for a BCD technology is presented which comprises the processing of the wafer on the thinned backside and which offers — similar to SOI technology — a full dielectric isolation of power devices. Limitations of the breakdown voltage of p-LDMOS encountered in conventional BCD technologies are overcome by replacing the commonly applied deep n well layer by an n+ region formed on the wafer backside and by connecting the n+ region with a TSV to the source potential on the front side. The fabricated p-LDMOS with drift length 5.7μm has a breakdown voltage (BVdss) of −115 V and an on-resistance (Ron) of 320 mΩ mm. It is found by TCAD simulations that further optimization of the p-LDMOS with respect to BVdss, Ron and electrical SOA can be achieved by adding an n-type RESURF layer below STI.
{"title":"Increasing breakdown voltage of p-channel LDMOS in BCD technology with novel backside process","authors":"C. Schmidt, G. Spitzlsperger","doi":"10.23919/ISPSD.2017.7988958","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988958","url":null,"abstract":"A novel concept for a BCD technology is presented which comprises the processing of the wafer on the thinned backside and which offers — similar to SOI technology — a full dielectric isolation of power devices. Limitations of the breakdown voltage of p-LDMOS encountered in conventional BCD technologies are overcome by replacing the commonly applied deep n well layer by an n+ region formed on the wafer backside and by connecting the n+ region with a TSV to the source potential on the front side. The fabricated p-LDMOS with drift length 5.7μm has a breakdown voltage (BVdss) of −115 V and an on-resistance (Ron) of 320 mΩ mm. It is found by TCAD simulations that further optimization of the p-LDMOS with respect to BVdss, Ron and electrical SOA can be achieved by adding an n-type RESURF layer below STI.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127008248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988937
Y. Shiba, Erdenebaatar Dashdondog, Masaki Sudo, I. Omura
Single-Event Burnout (SEB) is a catastrophic failure in the high voltage devices that is initiated by the passage of particles during turn-off state. Previous papers reported that SEB failure rate increases sharply when applied voltage exceeds a certain threshold voltage. On the other hand, the high voltage devices for the artificial satellite have been increasing. In space, due to increase flux of particle, it is predicted that SEB failure rate will be higher. In this paper, we proposed the failure rate calculation method for high voltage devices based on SEB cross section and flux of particles. This formula can calculate the failure rate at space level and terrestrial level depending on the applied voltage of the high voltage devices.
{"title":"Formulation of single event burnout failure rate for high voltage devices in satellite electrical power system","authors":"Y. Shiba, Erdenebaatar Dashdondog, Masaki Sudo, I. Omura","doi":"10.23919/ISPSD.2017.7988937","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988937","url":null,"abstract":"Single-Event Burnout (SEB) is a catastrophic failure in the high voltage devices that is initiated by the passage of particles during turn-off state. Previous papers reported that SEB failure rate increases sharply when applied voltage exceeds a certain threshold voltage. On the other hand, the high voltage devices for the artificial satellite have been increasing. In space, due to increase flux of particle, it is predicted that SEB failure rate will be higher. In this paper, we proposed the failure rate calculation method for high voltage devices based on SEB cross section and flux of particles. This formula can calculate the failure rate at space level and terrestrial level depending on the applied voltage of the high voltage devices.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132771880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988964
Z. Hossain, G. Sabui, Z. Shen
Shielded-gate trench or “Shield RESURF (REduced SURface Field)” MOSFETs have been well known for its lower RDS(ON) ×Area, and lower Rds(on)×Qgd figure of merits (FoMs), and used widely in the low to medium voltage applications (25 V to 200 V). However, this improvement is achieved at the expense of higher output capacitance or output charge (Coss or Qoss), which has become an increasingly important factor contributing to the MOSFET's switching power loss. In this paper, we will investigate the conventional single gate trench MOSFET structure based on the “dielectric RESURF” principle to offer a simpler wafer processing and consequently cheaper die cost, along with reduced switching losses at the output capacitance (Qoss), without compromising much the other key figure of merits such as Rds(on)×Area, and Rds(on)×Qg.
{"title":"Dielectric RESURF as an alternative to shield RESURF for an improved and easy-to-manufacture low voltage trench MOSFETs","authors":"Z. Hossain, G. Sabui, Z. Shen","doi":"10.23919/ISPSD.2017.7988964","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988964","url":null,"abstract":"Shielded-gate trench or “Shield RESURF (REduced SURface Field)” MOSFETs have been well known for its lower R<inf>DS(ON) ×</inf>Area, and lower R<inf>ds(on)</inf>×Q<inf>gd</inf> figure of merits (FoMs), and used widely in the low to medium voltage applications (25 V to 200 V). However, this improvement is achieved at the expense of higher output capacitance or output charge (C<inf>oss</inf> or Q<inf>oss</inf>), which has become an increasingly important factor contributing to the MOSFET's switching power loss. In this paper, we will investigate the conventional single gate trench MOSFET structure based on the “dielectric RESURF” principle to offer a simpler wafer processing and consequently cheaper die cost, along with reduced switching losses at the output capacitance (Q<inf>oss</inf>), without compromising much the other key figure of merits such as R<inf>ds(on)</inf>×Area, and R<inf>ds(on)</inf>×Qg.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133929238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988989
H. Matsushima, R. Yamada, A. Shima
Passivation films on the termination area of 4H-SiC diodes were investigated to clarify the origin of a positive charge accumulation that induces instability of the breakdown voltage. A method to differentiate measured depletion layer capacitance is proposed as a way to analyze the positive charge density after applying voltage stress. Samples with different passivation films were fabricated to compare the effects of the passivation films. The results of analyzing three kinds of passivation film show that the charge density did not increase in the sample without SiO2 on the termination area. In addition, the breakdown voltage of the sample did not change after applying stress. The results suggest that the passivation film sample without SiO2 is effective for suppressing the accumulation of positive charge density.
{"title":"Suppression of charge accumulation on termination area of 4H-SiC power devices","authors":"H. Matsushima, R. Yamada, A. Shima","doi":"10.23919/ISPSD.2017.7988989","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988989","url":null,"abstract":"Passivation films on the termination area of 4H-SiC diodes were investigated to clarify the origin of a positive charge accumulation that induces instability of the breakdown voltage. A method to differentiate measured depletion layer capacitance is proposed as a way to analyze the positive charge density after applying voltage stress. Samples with different passivation films were fabricated to compare the effects of the passivation films. The results of analyzing three kinds of passivation film show that the charge density did not increase in the sample without SiO2 on the termination area. In addition, the breakdown voltage of the sample did not change after applying stress. The results suggest that the passivation film sample without SiO2 is effective for suppressing the accumulation of positive charge density.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134314194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988920
Gaofei Tang, Jin Wei, Zhaofu Zhang, Xi Tang, M. Hua, Hanxing Wang, K. J. Chen
Dynamic ON-resistance (äon) behaviors of 600-V GaN-on-Si lateral power devices with grounded and floating substrate termination are studied. It is found that the floating substrate termination not only enables higher OFF-state breakdown voltage, but also delivers the benefit of smaller dynamic Ron degradation under higher drain bias (> 400 V) switching operations. Under medium drain bias (< 300 V) switching, a moderately larger dynamic Ron degradation is resulted from a floating substrate. The underlying physical mechanisms are explained by charge storage in the Si substrate and electron trapping effect in the GaN buffer layer.
研究了接地和浮基端接的600 v GaN-on-Si横向功率器件的动态导通电阻(äon)行为。研究发现，浮基板端接不仅可以实现更高的off状态击穿电压，而且在更高的漏极偏置(> 400 V)开关操作下，还可以实现更小的动态Ron退化。在中等漏极偏置(< 300 V)开关下，浮动衬底会导致较大的动态Ron退化。硅衬底中的电荷存储和氮化镓缓冲层中的电子捕获效应解释了其潜在的物理机制。
{"title":"Impact of substrate termination on dynamic performance of GaN-on-Si lateral power devices","authors":"Gaofei Tang, Jin Wei, Zhaofu Zhang, Xi Tang, M. Hua, Hanxing Wang, K. J. Chen","doi":"10.23919/ISPSD.2017.7988920","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988920","url":null,"abstract":"Dynamic ON-resistance (äon) behaviors of 600-V GaN-on-Si lateral power devices with grounded and floating substrate termination are studied. It is found that the floating substrate termination not only enables higher OFF-state breakdown voltage, but also delivers the benefit of smaller dynamic Ron degradation under higher drain bias (> 400 V) switching operations. Under medium drain bias (< 300 V) switching, a moderately larger dynamic Ron degradation is resulted from a floating substrate. The underlying physical mechanisms are explained by charge storage in the Si substrate and electron trapping effect in the GaN buffer layer.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114396755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988992
Jiaxing Wei, Siyang Liu, Ran Ye, Xin Chen, Haiyang Song, Weifeng Sun, Wei Su, Shulang Ma, Yuwei Liu, Feng Lin, Bo Hou
In this work, a useful interfacial damage extraction method for SiC power MOSFETs based on the C-V characteristics is proposed. According to the five different interface situations of the channel region and the JFET region, the Cg-Vg curve can be divided into five relatively independent parts. It demonstrates that the charges injected into the oxide of channel region will lead to an opposite shift in part 11 while the charges injected into the JFET region will result in the shifts in part 111 and IV. Through this way, the location of the charges injected in to the SiO2/SiC interface can be distinguished. The correctness of the method is proved by a UIS-stressed SiC power MOSFET. Moreover, the density of the charges injected into the interface oxide can be calculated by the amplitude of the shift in the Cg-Vg characteristic.
{"title":"Interfacial damage extraction method for SiC power MOSFETs based on C-V characteristics","authors":"Jiaxing Wei, Siyang Liu, Ran Ye, Xin Chen, Haiyang Song, Weifeng Sun, Wei Su, Shulang Ma, Yuwei Liu, Feng Lin, Bo Hou","doi":"10.23919/ISPSD.2017.7988992","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988992","url":null,"abstract":"In this work, a useful interfacial damage extraction method for SiC power MOSFETs based on the C-V characteristics is proposed. According to the five different interface situations of the channel region and the JFET region, the Cg-Vg curve can be divided into five relatively independent parts. It demonstrates that the charges injected into the oxide of channel region will lead to an opposite shift in part 11 while the charges injected into the JFET region will result in the shifts in part 111 and IV. Through this way, the location of the charges injected in to the SiO2/SiC interface can be distinguished. The correctness of the method is proved by a UIS-stressed SiC power MOSFET. Moreover, the density of the charges injected into the interface oxide can be calculated by the amplitude of the shift in the Cg-Vg characteristic.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116959557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988947
Takahide Tanaka, M. Yamaji, A. Jonishi, H. Ohashi, H. Sumida
To achieve a downsized high voltage integrated circuit (HVIC) with high electrostatic discharge (ESD) tolerance, we have proposed the improved self-shielding technique in which a high voltage junction termination (HVJT) diode works as a protection diode of high voltage Neh MOSFETs. This new technique is more effective not only in improving ESD tolerance but also in downsizing.
{"title":"A new downsized HVIC with high ESD tolerance","authors":"Takahide Tanaka, M. Yamaji, A. Jonishi, H. Ohashi, H. Sumida","doi":"10.23919/ISPSD.2017.7988947","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988947","url":null,"abstract":"To achieve a downsized high voltage integrated circuit (HVIC) with high electrostatic discharge (ESD) tolerance, we have proposed the improved self-shielding technique in which a high voltage junction termination (HVJT) diode works as a protection diode of high voltage Neh MOSFETs. This new technique is more effective not only in improving ESD tolerance but also in downsizing.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117335709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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