Short circuit capability of a 1200V SiC MOSFET and a 1200V Si IGBT is compared and analyzed in this work, and the channel mobility in the SiC MOSFET over a broad temperature range from room temperature up to 2000 °C has been extracted for the first time. Experimental results show that SiC MOSFET exhibits shorter short circuit withstand time (SCWT) compared to Si IGBT. 1-D transient finite element thermal models of SiC MOSFETs and Si IGBTs have been implemented to simulate the dynamic temperature profiles in devices during short circuit tests. The junction temperature of SiC MOSFET rises much faster than that of Si IGBT and the heat spreading thickness of SiC MOSFET is much narrower, leading to shorter SCWT of the SiC MOSFET. Combining the experimental and thermal simulation results, the temperature-dependent saturation drain current in SiC MOSFETs is extracted. Based on this, the channel mobility over a wide temperature range is obtained.
本文对1200V SiC MOSFET和1200V Si IGBT的短路性能进行了比较和分析，并首次提取了SiC MOSFET在室温至2000°C的宽温度范围内的沟道迁移率。实验结果表明，SiC MOSFET比Si IGBT具有更短的耐短路时间(SCWT)。建立了SiC mosfet和Si igbt的一维瞬态有限元热模型，用于模拟器件在短路测试过程中的动态温度分布。SiC MOSFET的结温上升速度比Si IGBT快得多，且SiC MOSFET的散热厚度窄得多，导致SiC MOSFET的SCWT较短。结合实验和热仿真结果，提取了SiC mosfet中温度相关的饱和漏极电流。在此基础上，获得了宽温度范围内的通道迁移率。
{"title":"Short circuit capability and high temperature channel mobility of SiC MOSFETs","authors":"Jiahui Sun, Hongyi Xu, Xinke Wu, Shu Yang, Qing Guo, Kuang Sheng","doi":"10.23919/ISPSD.2017.7988988","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988988","url":null,"abstract":"Short circuit capability of a 1200V SiC MOSFET and a 1200V Si IGBT is compared and analyzed in this work, and the channel mobility in the SiC MOSFET over a broad temperature range from room temperature up to 2000 °C has been extracted for the first time. Experimental results show that SiC MOSFET exhibits shorter short circuit withstand time (SCWT) compared to Si IGBT. 1-D transient finite element thermal models of SiC MOSFETs and Si IGBTs have been implemented to simulate the dynamic temperature profiles in devices during short circuit tests. The junction temperature of SiC MOSFET rises much faster than that of Si IGBT and the heat spreading thickness of SiC MOSFET is much narrower, leading to shorter SCWT of the SiC MOSFET. Combining the experimental and thermal simulation results, the temperature-dependent saturation drain current in SiC MOSFETs is extracted. Based on this, the channel mobility over a wide temperature range is obtained.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122110351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988883
Takuya Yamaguchi, Hideki Okumura, T. Shiraishi, Tsuyoshi Fujita, Yoshifumi Ata, Kenya Kobayashi
In high voltage power devices, to improve an active device area efficiency, a new edge termination structure that applying high aspect ratio deep trench termination technique is presented. The narrow trench filled with dielectric material acts as not only an electric field relaxing layer but also a reliable hard passivation. By using this technique, the active device area efficiency is maximized up to 96% with high reliability and good dynamic characteristics for 500 to 600 V MOSFETs.
{"title":"High aspect ratio deep trench termination (HARDT2) technique surrounding die edge as dielectric wall to improve high voltage device area efficiency","authors":"Takuya Yamaguchi, Hideki Okumura, T. Shiraishi, Tsuyoshi Fujita, Yoshifumi Ata, Kenya Kobayashi","doi":"10.23919/ISPSD.2017.7988883","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988883","url":null,"abstract":"In high voltage power devices, to improve an active device area efficiency, a new edge termination structure that applying high aspect ratio deep trench termination technique is presented. The narrow trench filled with dielectric material acts as not only an electric field relaxing layer but also a reliable hard passivation. By using this technique, the active device area efficiency is maximized up to 96% with high reliability and good dynamic characteristics for 500 to 600 V MOSFETs.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129092373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988909
I. Kasko, S. Berberich, M. Gross, P. Beckedahl, S. Buetow
A holistic approach taking benefit from optimization of chip, assembly technology and module design was utilized to exploit the performance potential of SiC power modules. A novel MOSFET SiC module (1200V, 400A) with extremely low inductance (1.4nH) was designed and assembled using Semikron DPD (Direct Pressed Die) technology. The electrical measurements showed excellent switching performance (switching speed up to ∼53kV/μs for dv/dt and ∼67kA/μs for di/dt) and very low energy losses (80% lower than state of the art Si based IGBT module). The enhanced reliability was demonstrated by power cycling tests (8–10x life time improvement compared to conventional assembly of SiC devices).
{"title":"High efficient approach to utilize SiC MOSFET potential in power modules","authors":"I. Kasko, S. Berberich, M. Gross, P. Beckedahl, S. Buetow","doi":"10.23919/ISPSD.2017.7988909","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988909","url":null,"abstract":"A holistic approach taking benefit from optimization of chip, assembly technology and module design was utilized to exploit the performance potential of SiC power modules. A novel MOSFET SiC module (1200V, 400A) with extremely low inductance (1.4nH) was designed and assembled using Semikron DPD (Direct Pressed Die) technology. The electrical measurements showed excellent switching performance (switching speed up to ∼53kV/μs for dv/dt and ∼67kA/μs for di/dt) and very low energy losses (80% lower than state of the art Si based IGBT module). The enhanced reliability was demonstrated by power cycling tests (8–10x life time improvement compared to conventional assembly of SiC devices).","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117276494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988978
J. Driesen
This paper discusses the technology trends behind the energy transition happening in the energy system of modern cities, linked to electrification, decentralization and digitalization. The role of power electronics, with a focus on building-level technologies, and the derived future requirements for converters and components are discussed. It is demonstrated using relevant use cases that power electronics represents “the new blocks that keep the building upright”.
{"title":"Power electronics as the enabling technology for sustainable energy in the smart city","authors":"J. Driesen","doi":"10.23919/ISPSD.2017.7988978","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988978","url":null,"abstract":"This paper discusses the technology trends behind the energy transition happening in the energy system of modern cities, linked to electrification, decentralization and digitalization. The role of power electronics, with a focus on building-level technologies, and the derived future requirements for converters and components are discussed. It is demonstrated using relevant use cases that power electronics represents “the new blocks that keep the building upright”.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124586905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988928
Jie Ren, Chao Liu, C. Tang, K. Lau, J. Sin
In this paper, the switching performance of monolithically integrated Si-GaN cascoded rectifiers is presented. The reverse recovery charge of the cascoded rectifier is 86.2% less than that of a Si fast recovery diode (FRD), which reveals great potential of cascoded rectifiers for high-speed power switching applications. Moreover, the double pulse tests are carried out for the cascoded rectifiers formed by monolithic integration and wire-bonding. The resulting power spectral densities show that the monolithically integrated one does not have current oscillation compared to that of the wire-bonded one.
{"title":"Switching characteristics of monolithically integrated Si-GaN cascoded rectifiers","authors":"Jie Ren, Chao Liu, C. Tang, K. Lau, J. Sin","doi":"10.23919/ISPSD.2017.7988928","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988928","url":null,"abstract":"In this paper, the switching performance of monolithically integrated Si-GaN cascoded rectifiers is presented. The reverse recovery charge of the cascoded rectifier is 86.2% less than that of a Si fast recovery diode (FRD), which reveals great potential of cascoded rectifiers for high-speed power switching applications. Moreover, the double pulse tests are carried out for the cascoded rectifiers formed by monolithic integration and wire-bonding. The resulting power spectral densities show that the monolithically integrated one does not have current oscillation compared to that of the wire-bonded one.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127815243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988874
Paul Brohlin
GaN's properties of low Coss, Crss, and lack of reverse recovery make it a more efficient power switch versus silicon. These characteristics enable higher-frequency hard-switched topologies such as totem-pole bridgeless power factor converter (PFC) that cannot be realized by silicon MOSFETs and insulated-gate bipolar transistors (IGBTs) due to their high switching losses. To take advantages of these properties, GaN must be switched quickly and reliably. This paper examines requirements for the driver, package, and the GaN HEMT to enable efficient and reliable switching.
{"title":"Challenges in reliably driving GaN devices","authors":"Paul Brohlin","doi":"10.23919/ISPSD.2017.7988874","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988874","url":null,"abstract":"GaN's properties of low Coss, Crss, and lack of reverse recovery make it a more efficient power switch versus silicon. These characteristics enable higher-frequency hard-switched topologies such as totem-pole bridgeless power factor converter (PFC) that cannot be realized by silicon MOSFETs and insulated-gate bipolar transistors (IGBTs) due to their high switching losses. To take advantages of these properties, GaN must be switched quickly and reliably. This paper examines requirements for the driver, package, and the GaN HEMT to enable efficient and reliable switching.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127902823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.3929/ETHZ-B-000187520
D. Neumayr, M. Guacci, D. Bortis, J. Kolar
Modern GaN and SiC power semiconductors require new experimental methods for determining switching losses as the widely accepted double-pulse-test (DPT) fails to accurately capture the dissipated energy during a switching transition because of electrical measurement limitations imposed by the very fast switching of WBG devices. In this paper, a new calorimetric measurement principle which relies on temperature rise monitoring of an aluminum heat sink during continuous operation of the attached power semiconductor is presented. Unlike traditional calorimetric methods, a single measurement can be performed in minutes. Using the proposed measurement principle, a soft-switching performance evaluation of selected 600 V GaN, SiC and Si power transistors is provided.
现代GaN和SiC功率半导体需要新的实验方法来确定开关损耗，因为广泛接受的双脉冲测试(DPT)由于WBG器件的快速开关所施加的电测量限制而无法准确捕获开关转换期间的耗散能量。本文提出了一种新的量热测量原理，该原理依赖于所附功率半导体的铝散热器在连续工作时的温升监测。与传统的量热法不同，一次测量可以在几分钟内完成。利用所提出的测量原理，对选定的600 V GaN、SiC和Si功率晶体管的软开关性能进行了评价。
{"title":"New calorimetrie power transistor soft-switching loss measurement based on accurate temperature rise monitoring","authors":"D. Neumayr, M. Guacci, D. Bortis, J. Kolar","doi":"10.3929/ETHZ-B-000187520","DOIUrl":"https://doi.org/10.3929/ETHZ-B-000187520","url":null,"abstract":"Modern GaN and SiC power semiconductors require new experimental methods for determining switching losses as the widely accepted double-pulse-test (DPT) fails to accurately capture the dissipated energy during a switching transition because of electrical measurement limitations imposed by the very fast switching of WBG devices. In this paper, a new calorimetric measurement principle which relies on temperature rise monitoring of an aluminum heat sink during continuous operation of the attached power semiconductor is presented. Unlike traditional calorimetric methods, a single measurement can be performed in minutes. Using the proposed measurement principle, a soft-switching performance evaluation of selected 600 V GaN, SiC and Si power transistors is provided.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131757862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988940
Katsumi Nakamura, K. Shimizu
This paper reports for the first time that the freewheeling diode (FWD) with Relaxed Field of Cathode (RFC) technology can achieves excellent total performance by adopting a novel vertical structure. The proposed vertical structure consists of a “Light Punch-Through (LPT) II” and a “Controlling Carrier-Plasma Layer (CPL)”. The measured results of 1200 V diode show that the total loss and dynamic behavior such as the recovery softness and the dynamic ruggedness are greatly improved thanks to the proposed vertical concept. These improvements are the result of controlling the charge-carrier plasma layer and moderating the electric field gradient in CPL zone during the recovery operation. The advanced RFC diode clearly breaks through the trade-off triangle of the total loss, the recovery softness and the recovery SOA of the FWD.
{"title":"Advanced RFC diode utilizing a novel vertical structure for soilness and high dynamic ruggedness","authors":"Katsumi Nakamura, K. Shimizu","doi":"10.23919/ISPSD.2017.7988940","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988940","url":null,"abstract":"This paper reports for the first time that the freewheeling diode (FWD) with Relaxed Field of Cathode (RFC) technology can achieves excellent total performance by adopting a novel vertical structure. The proposed vertical structure consists of a “Light Punch-Through (LPT) II” and a “Controlling Carrier-Plasma Layer (CPL)”. The measured results of 1200 V diode show that the total loss and dynamic behavior such as the recovery softness and the dynamic ruggedness are greatly improved thanks to the proposed vertical concept. These improvements are the result of controlling the charge-carrier plasma layer and moderating the electric field gradient in CPL zone during the recovery operation. The advanced RFC diode clearly breaks through the trade-off triangle of the total loss, the recovery softness and the recovery SOA of the FWD.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134453135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988985
Jin Wei, Meng Zhang, Huaping Jiang, Hanxing Wang, K. J. Chen
A p-shield region under the gate trench is typically adopted in a SiC trench MOSFET for achieving lower oxide field and Crss. In this work, we comprehensively studied the impact of a floating termination at the p-shield region on device performance. The SiC trench MOSFET's internal dynamics is revealed with numerical simulations. It is found that a lloating p-shield can effectively reduce the OFF-state electric-field in the bottom gate oxide of a SiC trench MOSFET without degrading its static performance. However, during switching operation, holes would be emitted out of the floating p-shield which then becomes a region that stores negative charges. The charge storage effect could then dramatically elevate the ON-state oxide field after the device is switched from the OFF-state, and also result in slower switching speed. The stored negative charges would also narrow the ON-state current path, and consequently, the dynamic äon would be degraded.
{"title":"Charge storage effect in SiC trench MOSFET with a floating p-shield and its impact on dynamic performances","authors":"Jin Wei, Meng Zhang, Huaping Jiang, Hanxing Wang, K. J. Chen","doi":"10.23919/ISPSD.2017.7988985","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988985","url":null,"abstract":"A p-shield region under the gate trench is typically adopted in a SiC trench MOSFET for achieving lower oxide field and Crss. In this work, we comprehensively studied the impact of a floating termination at the p-shield region on device performance. The SiC trench MOSFET's internal dynamics is revealed with numerical simulations. It is found that a lloating p-shield can effectively reduce the OFF-state electric-field in the bottom gate oxide of a SiC trench MOSFET without degrading its static performance. However, during switching operation, holes would be emitted out of the floating p-shield which then becomes a region that stores negative charges. The charge storage effect could then dramatically elevate the ON-state oxide field after the device is switched from the OFF-state, and also result in slower switching speed. The stored negative charges would also narrow the ON-state current path, and consequently, the dynamic äon would be degraded.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"588 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115979036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988943
Gaoqiang Deng, X. Luo, K. Zhou, Qingyuan He, Xinliang Ruan, Qing Liu, T. Sun, Bo Zhang
A 1200V-class Reverse Conducting IGBT with Alternating N+/P Buffers (AB) is proposed and its mechanism is investigated for the first time. The AB RC-IGBT features a buffer layer with alternately doped N+ and P regions. The AB is separated from the collector by a part of N-drift region. The P buffer serves as the electron barrier during the unipolar mode and forces the electrons to flow through the high-resistance N-drift region between the buffer and the collector. Consequently, the snapback is suppressed with a fairly small cell pitch of 30μm. In the blocking state, the P buffer is fully depleted while the N+ buffer is not fully depleted yet. Therefore, the electric field terminates in the buffer layer and a high BV is ensured. The turn-off loss of the proposed AB RC-IGBT is reduced by 20% compared with that of the conventional RC-IGBT for the same forward on-state voltage drop.
{"title":"A snapback-free RC-IGBT with Alternating N/P buffers","authors":"Gaoqiang Deng, X. Luo, K. Zhou, Qingyuan He, Xinliang Ruan, Qing Liu, T. Sun, Bo Zhang","doi":"10.23919/ISPSD.2017.7988943","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988943","url":null,"abstract":"A 1200V-class Reverse Conducting IGBT with Alternating N+/P Buffers (AB) is proposed and its mechanism is investigated for the first time. The AB RC-IGBT features a buffer layer with alternately doped N+ and P regions. The AB is separated from the collector by a part of N-drift region. The P buffer serves as the electron barrier during the unipolar mode and forces the electrons to flow through the high-resistance N-drift region between the buffer and the collector. Consequently, the snapback is suppressed with a fairly small cell pitch of 30μm. In the blocking state, the P buffer is fully depleted while the N+ buffer is not fully depleted yet. Therefore, the electric field terminates in the buffer layer and a high BV is ensured. The turn-off loss of the proposed AB RC-IGBT is reduced by 20% compared with that of the conventional RC-IGBT for the same forward on-state voltage drop.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116682082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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