Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988928
Jie Ren, Chao Liu, C. Tang, K. Lau, J. Sin
In this paper, the switching performance of monolithically integrated Si-GaN cascoded rectifiers is presented. The reverse recovery charge of the cascoded rectifier is 86.2% less than that of a Si fast recovery diode (FRD), which reveals great potential of cascoded rectifiers for high-speed power switching applications. Moreover, the double pulse tests are carried out for the cascoded rectifiers formed by monolithic integration and wire-bonding. The resulting power spectral densities show that the monolithically integrated one does not have current oscillation compared to that of the wire-bonded one.
{"title":"Switching characteristics of monolithically integrated Si-GaN cascoded rectifiers","authors":"Jie Ren, Chao Liu, C. Tang, K. Lau, J. Sin","doi":"10.23919/ISPSD.2017.7988928","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988928","url":null,"abstract":"In this paper, the switching performance of monolithically integrated Si-GaN cascoded rectifiers is presented. The reverse recovery charge of the cascoded rectifier is 86.2% less than that of a Si fast recovery diode (FRD), which reveals great potential of cascoded rectifiers for high-speed power switching applications. Moreover, the double pulse tests are carried out for the cascoded rectifiers formed by monolithic integration and wire-bonding. The resulting power spectral densities show that the monolithically integrated one does not have current oscillation compared to that of the wire-bonded one.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127815243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988874
Paul Brohlin
GaN's properties of low Coss, Crss, and lack of reverse recovery make it a more efficient power switch versus silicon. These characteristics enable higher-frequency hard-switched topologies such as totem-pole bridgeless power factor converter (PFC) that cannot be realized by silicon MOSFETs and insulated-gate bipolar transistors (IGBTs) due to their high switching losses. To take advantages of these properties, GaN must be switched quickly and reliably. This paper examines requirements for the driver, package, and the GaN HEMT to enable efficient and reliable switching.
{"title":"Challenges in reliably driving GaN devices","authors":"Paul Brohlin","doi":"10.23919/ISPSD.2017.7988874","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988874","url":null,"abstract":"GaN's properties of low Coss, Crss, and lack of reverse recovery make it a more efficient power switch versus silicon. These characteristics enable higher-frequency hard-switched topologies such as totem-pole bridgeless power factor converter (PFC) that cannot be realized by silicon MOSFETs and insulated-gate bipolar transistors (IGBTs) due to their high switching losses. To take advantages of these properties, GaN must be switched quickly and reliably. This paper examines requirements for the driver, package, and the GaN HEMT to enable efficient and reliable switching.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127902823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988955
A. Sakai, K. Eikyu, H. Fujii, T. Mori, Y. Akiyama, Y. Yamaguchi
This paper proposes a simple and efficient method to improve hot carrier (HC) immunity of p-channel LDMOSFET without degrading typical figure of merits such as breakdown voltage BV and specific on-resistance Rsp. The superiority of a novel STI-based p-channel LDMOSFET with a hot electron cooling (HEC) layer against the conventional method to improve HC immunity (i.e. extending the p-drift length) is confirmed by TCAD simulation.
{"title":"Simple and efficient approach to improve hot carrier immunity of a p-LDMOSFET","authors":"A. Sakai, K. Eikyu, H. Fujii, T. Mori, Y. Akiyama, Y. Yamaguchi","doi":"10.23919/ISPSD.2017.7988955","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988955","url":null,"abstract":"This paper proposes a simple and efficient method to improve hot carrier (HC) immunity of p-channel LDMOSFET without degrading typical figure of merits such as breakdown voltage BV and specific on-resistance Rsp. The superiority of a novel STI-based p-channel LDMOSFET with a hot electron cooling (HEC) layer against the conventional method to improve HC immunity (i.e. extending the p-drift length) is confirmed by TCAD simulation.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"34 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114154547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988949
Zhao Qi, M. Qiao, Xin Zhou, Wen Yang, Dong Fang, Shikang Cheng, Sen Zhang, Zhaoji Li, Bo Zhang
A latch-up immune robust SCR with an N+ top layer and an additional Nwell region (Nwell2) is proposed in this paper. The N+ top layer and Nwell2 divide the original SCR into three new SCRs with sharing emitter, which provide the deeper ESD current (Iesd) path to improve the holding voltage (Vh) and failure current (It2). The relation between Vh and base-concentration (Nb) for LVTSCR is given to provide an in-depth insight into the mechanism for enhancing Vh by changing Nb. The N+ top layer and NWELL2 form three base regions (B1, B2 and B3) with different concentration to optimize the IESD distribution and Vh. The longer ESD current path improves the Vh by reducing the current gain. The deeper current distribution makes the total temperature is endured by inner lattice instead of surface lattice, which improves the It2. DC and dynamic TLP simulation results show the Vh = 5.3 V of proposed SCR is achieved with a higher failure current (It2) of 1.68e-2A/μm.
{"title":"Investigation of a latch-up immune silicon controlled rectifier for robust ESD application","authors":"Zhao Qi, M. Qiao, Xin Zhou, Wen Yang, Dong Fang, Shikang Cheng, Sen Zhang, Zhaoji Li, Bo Zhang","doi":"10.23919/ISPSD.2017.7988949","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988949","url":null,"abstract":"A latch-up immune robust SCR with an N+ top layer and an additional Nwell region (Nwell2) is proposed in this paper. The N+ top layer and Nwell2 divide the original SCR into three new SCRs with sharing emitter, which provide the deeper ESD current (I<inf>esd</inf>) path to improve the holding voltage (V<inf>h</inf>) and failure current (I<inf>t2</inf>). The relation between V<inf>h</inf> and base-concentration (N<inf>b</inf>) for LVTSCR is given to provide an in-depth insight into the mechanism for enhancing V<inf>h</inf> by changing N<inf>b</inf>. The N+ top layer and NWELL2 form three base regions (B1, B2 and B3) with different concentration to optimize the I<inf>ESD</inf> distribution and V<inf>h</inf>. The longer ESD current path improves the V<inf>h</inf> by reducing the current gain. The deeper current distribution makes the total temperature is endured by inner lattice instead of surface lattice, which improves the I<inf>t2</inf>. DC and dynamic TLP simulation results show the V<inf>h</inf> = 5.3 V of proposed SCR is achieved with a higher failure current (I<inf>t2</inf>) of 1.68e-2A/μm.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125253698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988940
Katsumi Nakamura, K. Shimizu
This paper reports for the first time that the freewheeling diode (FWD) with Relaxed Field of Cathode (RFC) technology can achieves excellent total performance by adopting a novel vertical structure. The proposed vertical structure consists of a “Light Punch-Through (LPT) II” and a “Controlling Carrier-Plasma Layer (CPL)”. The measured results of 1200 V diode show that the total loss and dynamic behavior such as the recovery softness and the dynamic ruggedness are greatly improved thanks to the proposed vertical concept. These improvements are the result of controlling the charge-carrier plasma layer and moderating the electric field gradient in CPL zone during the recovery operation. The advanced RFC diode clearly breaks through the trade-off triangle of the total loss, the recovery softness and the recovery SOA of the FWD.
{"title":"Advanced RFC diode utilizing a novel vertical structure for soilness and high dynamic ruggedness","authors":"Katsumi Nakamura, K. Shimizu","doi":"10.23919/ISPSD.2017.7988940","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988940","url":null,"abstract":"This paper reports for the first time that the freewheeling diode (FWD) with Relaxed Field of Cathode (RFC) technology can achieves excellent total performance by adopting a novel vertical structure. The proposed vertical structure consists of a “Light Punch-Through (LPT) II” and a “Controlling Carrier-Plasma Layer (CPL)”. The measured results of 1200 V diode show that the total loss and dynamic behavior such as the recovery softness and the dynamic ruggedness are greatly improved thanks to the proposed vertical concept. These improvements are the result of controlling the charge-carrier plasma layer and moderating the electric field gradient in CPL zone during the recovery operation. The advanced RFC diode clearly breaks through the trade-off triangle of the total loss, the recovery softness and the recovery SOA of the FWD.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134453135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988982
H. Kitai, Y. Hozumi, H. Shiomi, K. Fukuda, Masaki Furumai
In this paper, a 13-kV SiC MOSFET with a retrograde doping profile in junction field-effect transistor (JFET) regions, which were implanted by nitrogen ions with multiple energies, has been developed for power supplies of X-ray generators and electron guns with an accelerating voltage greater than 10 kV. A JFET region was optimized with device simulation to reduce on-resistance. A SiC MOSFET with an optimized JFET region was fabricated with a 5 mm × 5 mm die size. The specific on-resistance (RonA) was estimated to be 169 mΩ·cm2. The blocking voltage (BVDSS) of 13.1 kV was obtained at 10 μA/cm2. Owing to a low electric field in the gate oxide (Eox), a threshold voltage (Vth) shift within ± 0.06 V was achieved at the gate voltage of −15 V (equal to an electric field of −3 MV/cm) and 200 °C for 1000 hours. The dynamic test with inductive load resulted in turn-off and turn-on switching speeds of 75 kV/μs and 114 kV/μs, respectively, for the DC bus voltage of 10 kV at room temperature.
本文研制了一种在结场效应晶体管(JFET)区域逆行掺杂的13kv SiC MOSFET，该MOSFET由多能态氮离子注入，用于x射线发生器和加速电压大于10kv的电子枪的电源。通过器件仿真对JFET区域进行优化，降低导通电阻。采用5 mm × 5 mm的晶片尺寸制备了具有优化JFET区域的SiC MOSFET。比导通电阻(RonA)估计为169 mΩ·cm2。在10 μA/cm2下获得了13.1 kV的阻断电压(BVDSS)。由于栅极氧化物(Eox)中的电场较低，在−15 V的栅极电压(等于−3 MV/cm的电场)和200℃下，在1000小时内实现了阈值电压(Vth)的±0.06 V的位移。在感应负载下的动态试验结果表明，在室温下，直流母线电压为10 kV时，关断和导通速度分别为75 kV/μs和114 kV/μs。
{"title":"Low on-resistance and fast switching of 13-kV SiC MOSFETs with optimized junction field-effect transistor region","authors":"H. Kitai, Y. Hozumi, H. Shiomi, K. Fukuda, Masaki Furumai","doi":"10.23919/ISPSD.2017.7988982","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988982","url":null,"abstract":"In this paper, a 13-kV SiC MOSFET with a retrograde doping profile in junction field-effect transistor (JFET) regions, which were implanted by nitrogen ions with multiple energies, has been developed for power supplies of X-ray generators and electron guns with an accelerating voltage greater than 10 kV. A JFET region was optimized with device simulation to reduce on-resistance. A SiC MOSFET with an optimized JFET region was fabricated with a 5 mm × 5 mm die size. The specific on-resistance (R<inf>onA</inf>) was estimated to be 169 mΩ·cm<sup>2</sup>. The blocking voltage (BV<inf>DSS</inf>) of 13.1 kV was obtained at 10 μA/cm<sup>2</sup>. Owing to a low electric field in the gate oxide (E<inf>ox</inf>), a threshold voltage (V<inf>th</inf>) shift within ± 0.06 V was achieved at the gate voltage of −15 V (equal to an electric field of −3 MV/cm) and 200 °C for 1000 hours. The dynamic test with inductive load resulted in turn-off and turn-on switching speeds of 75 kV/μs and 114 kV/μs, respectively, for the DC bus voltage of 10 kV at room temperature.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128271781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988883
Takuya Yamaguchi, Hideki Okumura, T. Shiraishi, Tsuyoshi Fujita, Yoshifumi Ata, Kenya Kobayashi
In high voltage power devices, to improve an active device area efficiency, a new edge termination structure that applying high aspect ratio deep trench termination technique is presented. The narrow trench filled with dielectric material acts as not only an electric field relaxing layer but also a reliable hard passivation. By using this technique, the active device area efficiency is maximized up to 96% with high reliability and good dynamic characteristics for 500 to 600 V MOSFETs.
{"title":"High aspect ratio deep trench termination (HARDT2) technique surrounding die edge as dielectric wall to improve high voltage device area efficiency","authors":"Takuya Yamaguchi, Hideki Okumura, T. Shiraishi, Tsuyoshi Fujita, Yoshifumi Ata, Kenya Kobayashi","doi":"10.23919/ISPSD.2017.7988883","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988883","url":null,"abstract":"In high voltage power devices, to improve an active device area efficiency, a new edge termination structure that applying high aspect ratio deep trench termination technique is presented. The narrow trench filled with dielectric material acts as not only an electric field relaxing layer but also a reliable hard passivation. By using this technique, the active device area efficiency is maximized up to 96% with high reliability and good dynamic characteristics for 500 to 600 V MOSFETs.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129092373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.3929/ETHZ-B-000187520
D. Neumayr, M. Guacci, D. Bortis, J. Kolar
Modern GaN and SiC power semiconductors require new experimental methods for determining switching losses as the widely accepted double-pulse-test (DPT) fails to accurately capture the dissipated energy during a switching transition because of electrical measurement limitations imposed by the very fast switching of WBG devices. In this paper, a new calorimetric measurement principle which relies on temperature rise monitoring of an aluminum heat sink during continuous operation of the attached power semiconductor is presented. Unlike traditional calorimetric methods, a single measurement can be performed in minutes. Using the proposed measurement principle, a soft-switching performance evaluation of selected 600 V GaN, SiC and Si power transistors is provided.
现代GaN和SiC功率半导体需要新的实验方法来确定开关损耗，因为广泛接受的双脉冲测试(DPT)由于WBG器件的快速开关所施加的电测量限制而无法准确捕获开关转换期间的耗散能量。本文提出了一种新的量热测量原理，该原理依赖于所附功率半导体的铝散热器在连续工作时的温升监测。与传统的量热法不同，一次测量可以在几分钟内完成。利用所提出的测量原理，对选定的600 V GaN、SiC和Si功率晶体管的软开关性能进行了评价。
{"title":"New calorimetrie power transistor soft-switching loss measurement based on accurate temperature rise monitoring","authors":"D. Neumayr, M. Guacci, D. Bortis, J. Kolar","doi":"10.3929/ETHZ-B-000187520","DOIUrl":"https://doi.org/10.3929/ETHZ-B-000187520","url":null,"abstract":"Modern GaN and SiC power semiconductors require new experimental methods for determining switching losses as the widely accepted double-pulse-test (DPT) fails to accurately capture the dissipated energy during a switching transition because of electrical measurement limitations imposed by the very fast switching of WBG devices. In this paper, a new calorimetric measurement principle which relies on temperature rise monitoring of an aluminum heat sink during continuous operation of the attached power semiconductor is presented. Unlike traditional calorimetric methods, a single measurement can be performed in minutes. Using the proposed measurement principle, a soft-switching performance evaluation of selected 600 V GaN, SiC and Si power transistors is provided.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131757862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988943
Gaoqiang Deng, X. Luo, K. Zhou, Qingyuan He, Xinliang Ruan, Qing Liu, T. Sun, Bo Zhang
A 1200V-class Reverse Conducting IGBT with Alternating N+/P Buffers (AB) is proposed and its mechanism is investigated for the first time. The AB RC-IGBT features a buffer layer with alternately doped N+ and P regions. The AB is separated from the collector by a part of N-drift region. The P buffer serves as the electron barrier during the unipolar mode and forces the electrons to flow through the high-resistance N-drift region between the buffer and the collector. Consequently, the snapback is suppressed with a fairly small cell pitch of 30μm. In the blocking state, the P buffer is fully depleted while the N+ buffer is not fully depleted yet. Therefore, the electric field terminates in the buffer layer and a high BV is ensured. The turn-off loss of the proposed AB RC-IGBT is reduced by 20% compared with that of the conventional RC-IGBT for the same forward on-state voltage drop.
{"title":"A snapback-free RC-IGBT with Alternating N/P buffers","authors":"Gaoqiang Deng, X. Luo, K. Zhou, Qingyuan He, Xinliang Ruan, Qing Liu, T. Sun, Bo Zhang","doi":"10.23919/ISPSD.2017.7988943","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988943","url":null,"abstract":"A 1200V-class Reverse Conducting IGBT with Alternating N+/P Buffers (AB) is proposed and its mechanism is investigated for the first time. The AB RC-IGBT features a buffer layer with alternately doped N+ and P regions. The AB is separated from the collector by a part of N-drift region. The P buffer serves as the electron barrier during the unipolar mode and forces the electrons to flow through the high-resistance N-drift region between the buffer and the collector. Consequently, the snapback is suppressed with a fairly small cell pitch of 30μm. In the blocking state, the P buffer is fully depleted while the N+ buffer is not fully depleted yet. Therefore, the electric field terminates in the buffer layer and a high BV is ensured. The turn-off loss of the proposed AB RC-IGBT is reduced by 20% compared with that of the conventional RC-IGBT for the same forward on-state voltage drop.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116682082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988972
H. Miyazaki, You Zhou, K. Hirao, S. Fukuda, N. Izu, Hideki Hyuga, Shoji Iwakiri, H. Hirotsuru
Thermal fatigue of active metal brazing (AMB) substrates was investigated under severe heat cycle condition from −40°C to 250°C using developed silicon nitride ceramics (Si3N4) with high thermal conductivity and excellent fracture toughness as well as conventional Si3N4 and aluminum nitrides (AIN). No peeling off of copper layer was observed even after 1000 cycles for the AMB substrates with various Si3N4, whereas the AIN-AMB substrates exhibited copper delamination only after 50 cycles. Bending strengths of the AMB substrates with conventional Si3N4 decreased gradually with thermal cycles. By contrast, degradation in the bending strength of the AMB substrates with developed Si3N4 was negligible. It was found that the developed Si3N4-AMB substrate with superior mechanical and thermal performance could endure harsh thermal environments.
{"title":"Highly thermal-fatigue resistant Si3N4 substrates with excellent mechanical and thermal properties","authors":"H. Miyazaki, You Zhou, K. Hirao, S. Fukuda, N. Izu, Hideki Hyuga, Shoji Iwakiri, H. Hirotsuru","doi":"10.23919/ISPSD.2017.7988972","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988972","url":null,"abstract":"Thermal fatigue of active metal brazing (AMB) substrates was investigated under severe heat cycle condition from −40°C to 250°C using developed silicon nitride ceramics (Si<inf>3</inf>N<inf>4</inf>) with high thermal conductivity and excellent fracture toughness as well as conventional Si<inf>3</inf>N<inf>4</inf> and aluminum nitrides (AIN). No peeling off of copper layer was observed even after 1000 cycles for the AMB substrates with various Si<inf>3</inf>N<inf>4</inf>, whereas the AIN-AMB substrates exhibited copper delamination only after 50 cycles. Bending strengths of the AMB substrates with conventional Si<inf>3</inf>N<inf>4</inf> decreased gradually with thermal cycles. By contrast, degradation in the bending strength of the AMB substrates with developed Si<inf>3</inf>N<inf>4</inf> was negligible. It was found that the developed Si<inf>3</inf>N<inf>4</inf>-AMB substrate with superior mechanical and thermal performance could endure harsh thermal environments.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129280187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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