Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010497
Jie Dai, C. Winstead, C. Myers, R. Harrison, C. Schlegel
This paper presents a cell library for automatic synthesis of analog error control decoders. By using some basic cells, analog error control decoders can be automatically synthesized. Also, using automatic synthesis based on this cell library, the circuit performance is not degraded and the circuit is smaller and lower power compared with corresponding canonical designs.
{"title":"Cell library for automatic synthesis of analog error control decoders","authors":"Jie Dai, C. Winstead, C. Myers, R. Harrison, C. Schlegel","doi":"10.1109/ISCAS.2002.1010497","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010497","url":null,"abstract":"This paper presents a cell library for automatic synthesis of analog error control decoders. By using some basic cells, analog error control decoders can be automatically synthesized. Also, using automatic synthesis based on this cell library, the circuit performance is not degraded and the circuit is smaller and lower power compared with corresponding canonical designs.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129418446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a novel timing-driven global routing algorithm for standard cell (SC) layout design based on a critical network concept. The essence of this algorithm is different from that of the typical existing methods, such as the nets-based method and the critical-path-based method. The timing optimization strategy presented in this algorithm is more optimal than the typical existing ones, which makes it possible to reduce the delay in an overall survey. This algorithm has been implemented and tested by MCNC benchmark circuits in this paper. We compared the experimental results between our algorithm and the existing ones. The experimental results show that this algorithm is able to control the delay of the circuit efficiently, and causes little negative effect on other optimizing objectives.
{"title":"A novel and efficient timing-driven global router for standard cell layout design based on critical network concept","authors":"Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu","doi":"10.1109/ISCAS.2002.1009803","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009803","url":null,"abstract":"This paper presents a novel timing-driven global routing algorithm for standard cell (SC) layout design based on a critical network concept. The essence of this algorithm is different from that of the typical existing methods, such as the nets-based method and the critical-path-based method. The timing optimization strategy presented in this algorithm is more optimal than the typical existing ones, which makes it possible to reduce the delay in an overall survey. This algorithm has been implemented and tested by MCNC benchmark circuits in this paper. We compared the experimental results between our algorithm and the existing ones. The experimental results show that this algorithm is able to control the delay of the circuit efficiently, and causes little negative effect on other optimizing objectives.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129610050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010499
A. Anttonen, T. Rautio
Adaptive sample rate converters (SRC) for the multi-standard mobile transceiver have been designed. GSM, UMTS and HIPERLAN2 standards have been chosen to establish the requirements for the SRCs. In the transmitter, the output signal of the data modulator is sampled at the symbol or chip frequency specified by the standards and needs to be converted into a common updating frequency of the D/A-converter. Pulse shaping and emission mask requirements are taken into account. In the receiver, A/D-conversion is also performed at a common fixed clock rate. Thus the SRC is needed to convert the A/D-converter sampling rate into a symbol or chip frequency that will be applied for further baseband signal processing. Channelization requirements defined by the standards are used as criteria for the performance analysis in the receiver. Based on the performance analysis, the complexity analysis is covered. It includes computational complexity, gate count, area and power consumption estimation for the chosen platform.
{"title":"Performance and complexity analysis for adaptive sample rate converters in GSM/UMTS/HIPERLAN2 mobile transceiver","authors":"A. Anttonen, T. Rautio","doi":"10.1109/ISCAS.2002.1010499","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010499","url":null,"abstract":"Adaptive sample rate converters (SRC) for the multi-standard mobile transceiver have been designed. GSM, UMTS and HIPERLAN2 standards have been chosen to establish the requirements for the SRCs. In the transmitter, the output signal of the data modulator is sampled at the symbol or chip frequency specified by the standards and needs to be converted into a common updating frequency of the D/A-converter. Pulse shaping and emission mask requirements are taken into account. In the receiver, A/D-conversion is also performed at a common fixed clock rate. Thus the SRC is needed to convert the A/D-converter sampling rate into a symbol or chip frequency that will be applied for further baseband signal processing. Channelization requirements defined by the standards are used as criteria for the performance analysis in the receiver. Based on the performance analysis, the complexity analysis is covered. It includes computational complexity, gate count, area and power consumption estimation for the chosen platform.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128376257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010515
L. Koskinen, A. Paasio, M. Laiho, K. Halonen
The effect of the cellular nonlinear network (CNN) shape segmentation algorithm on the shape bit-rate of a context-based arithmetic encoder has been simulated. Also, the correlation of shape boundary block and opaque block motion vectors and shape motion vectors and texture motion vectors has been simulated. It is found that, along with content-based MPEG-4 encoding, the intermediate results of the CNN algorithm can be used for power consumption reduction in the encoder.
{"title":"Effect of CNN shape segmentation on MPEG-4 shape bit-rate","authors":"L. Koskinen, A. Paasio, M. Laiho, K. Halonen","doi":"10.1109/ISCAS.2002.1010515","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010515","url":null,"abstract":"The effect of the cellular nonlinear network (CNN) shape segmentation algorithm on the shape bit-rate of a context-based arithmetic encoder has been simulated. Also, the correlation of shape boundary block and opaque block motion vectors and shape motion vectors and texture motion vectors has been simulated. It is found that, along with content-based MPEG-4 encoding, the intermediate results of the CNN algorithm can be used for power consumption reduction in the encoder.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128448252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009918
E. Saatci, V. Tavsanoglu
In image processing with CNN, it is impossible to have a one-to-one mapping between the CNN hardware processors and all the pixels of the image due to hardware limitations. A raster simulator provides a solution to this problem and is capable of performing single-layer CNN simulations for any size of input image. This approach is very useful for CNN researchers to simulate hardware models, test hardware implementations of CNN, develop new templates and improve existing ones. A key issue in the raster simulation of CNN is the determination of equilibrium points whose calculation is usually carried out using complex and computationally expensive numerical integration methods. We show that the simple explicit Euler integration method, together with the optimum choice of time-step size, yields the exact equilibrium points. This leads to a drastic acceleration in the simulation allowing minimal computational effort.
{"title":"On the optimal choice of integration time-step for raster simulation of a CNN for gray level image processing","authors":"E. Saatci, V. Tavsanoglu","doi":"10.1109/ISCAS.2002.1009918","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009918","url":null,"abstract":"In image processing with CNN, it is impossible to have a one-to-one mapping between the CNN hardware processors and all the pixels of the image due to hardware limitations. A raster simulator provides a solution to this problem and is capable of performing single-layer CNN simulations for any size of input image. This approach is very useful for CNN researchers to simulate hardware models, test hardware implementations of CNN, develop new templates and improve existing ones. A key issue in the raster simulation of CNN is the determination of equilibrium points whose calculation is usually carried out using complex and computationally expensive numerical integration methods. We show that the simple explicit Euler integration method, together with the optimum choice of time-step size, yields the exact equilibrium points. This leads to a drastic acceleration in the simulation allowing minimal computational effort.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128452572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010447
D. Fogliatti
A brief review of the operation of vibratory gyroscopes and the status of commercial micromachined gyroscopes is presented in the introduction. Following the introduction, an alternative design approach employing multiple, coupled gyroscopes per angular axis is examined as a method to improve performance and redundancy in angular rate sensors. The results are from simulations and explore the effects of non-identical gyroscopes, variations in the driving frequency, and coupling on synchronization in the array. A novel operating approach is presented that requires the array of gyroscopes to be synchronized in phase and frequency to improve the detection of sense axis displacement and to utilize one amplitude demodulator for the entire array of gyroscopes.
{"title":"Interconnected resonant gyros for improved performance","authors":"D. Fogliatti","doi":"10.1109/ISCAS.2002.1010447","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010447","url":null,"abstract":"A brief review of the operation of vibratory gyroscopes and the status of commercial micromachined gyroscopes is presented in the introduction. Following the introduction, an alternative design approach employing multiple, coupled gyroscopes per angular axis is examined as a method to improve performance and redundancy in angular rate sensors. The results are from simulations and explore the effects of non-identical gyroscopes, variations in the driving frequency, and coupling on synchronization in the array. A novel operating approach is presented that requires the array of gyroscopes to be synchronized in phase and frequency to improve the detection of sense axis displacement and to utilize one amplitude demodulator for the entire array of gyroscopes.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128530049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1011444
A. Zaccarin, B. Yeo
In today's streaming servers, video sequences are offered to users at different fixed bit rates. This paper presents an efficient approach for simultaneous encoding of a video sequence at multiple bit rates. In this encoder, motion estimation is performed only once for the reference stream. We also take the DCT out of the encoding loop so that it is only computed once per frame. As a result, no iDCT has to be computed at the encoder. However, motion compensation is performed in the DCT domain, and drift error can be introduced adaptively to reduce the computational cost of the DCT-domain motion compensation. Results show that significant computational reduction can be achieved with less than 0.3 dB loss in PSNR when compared to independently encoding the video sequence at multiple rates.
{"title":"Multi-rate encoding of a video sequence in the DCT domain","authors":"A. Zaccarin, B. Yeo","doi":"10.1109/ISCAS.2002.1011444","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1011444","url":null,"abstract":"In today's streaming servers, video sequences are offered to users at different fixed bit rates. This paper presents an efficient approach for simultaneous encoding of a video sequence at multiple bit rates. In this encoder, motion estimation is performed only once for the reference stream. We also take the DCT out of the encoding loop so that it is only computed once per frame. As a result, no iDCT has to be computed at the encoder. However, motion compensation is performed in the DCT domain, and drift error can be introduced adaptively to reduce the computational cost of the DCT-domain motion compensation. Results show that significant computational reduction can be achieved with less than 0.3 dB loss in PSNR when compared to independently encoding the video sequence at multiple rates.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129424997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009900
A. Sommariva
The maximum power transfer theorem for DC linear two-ports terminated by uncoupled passive resistors is stated and proved. Unlike all previous works, non-reciprocal two-ports (i.e. two-ports whose resistance matrix is non-symmetrical) are allowed, and power is maximized with respect to the load resistances rather than the load currents. Further, the approach developed is variational instead of direct (i.e. based on the theory of quadratic forms), and thus yields considerable side information on the global behaviour of the circuit. Although calculations are more involved than in the case of one-ports, final results are relatively simple.
{"title":"A maximum power transfer theorem for DC linear two-ports","authors":"A. Sommariva","doi":"10.1109/ISCAS.2002.1009900","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009900","url":null,"abstract":"The maximum power transfer theorem for DC linear two-ports terminated by uncoupled passive resistors is stated and proved. Unlike all previous works, non-reciprocal two-ports (i.e. two-ports whose resistance matrix is non-symmetrical) are allowed, and power is maximized with respect to the load resistances rather than the load currents. Further, the approach developed is variational instead of direct (i.e. based on the theory of quadratic forms), and thus yields considerable side information on the global behaviour of the circuit. Although calculations are more involved than in the case of one-ports, final results are relatively simple.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129472718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010593
Seraphim Poriazis
The behavior of the two-phase twisted-ring counter (2P-TRC) circuit is analyzed. The circuit produces two individual phased clock signals that exercise a phase difference equal to the half period of the clock. A tree-like structure is built by applying the phased outputs of the circuit to the clock inputs of two replicas of the circuit in order to extend its behavior. The EXOR gate is used to define a mirroring structure attached to the 2P-TRC structure such that a primitive/expanded counter configuration is formed. A fundamental concept being described by the transposition mechanism of the EXOR operator is incorporated to the above configuration such that the phase association of interconnecting signals is preserved.
{"title":"The two-phase twisted-ring counter circuit","authors":"Seraphim Poriazis","doi":"10.1109/ISCAS.2002.1010593","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010593","url":null,"abstract":"The behavior of the two-phase twisted-ring counter (2P-TRC) circuit is analyzed. The circuit produces two individual phased clock signals that exercise a phase difference equal to the half period of the clock. A tree-like structure is built by applying the phased outputs of the circuit to the clock inputs of two replicas of the circuit in order to extend its behavior. The EXOR gate is used to define a mirroring structure attached to the 2P-TRC structure such that a primitive/expanded counter configuration is formed. A fundamental concept being described by the transposition mechanism of the EXOR operator is incorporated to the above configuration such that the phase association of interconnecting signals is preserved.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129645561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009806
Xin Li, Xuan Zeng, Dian Zhou, X. Ling
In this paper, we propose a fast wavelet collocation algorithm for high-speed clock tree simulation. Taking advantage of the specific structure of clock trees and the superior computational property of wavelets, the proposed algorithm presents the following merits. (1) It can perform both transient simulation and steady-state analysis with arbitrary input. (2) It employs nonlinear buffer model and nonuniform interconnect wire model. (3) It has a low computational complexity O(N) and can deal with considerably large circuits. (4) The proposed wavelet method works in time domain so that the simulation error in time domain can be well-controlled. Numerical experiment results demonstrate the promising features of the proposed algorithm in high-speed clock tree simulations.
{"title":"Wavelet method for high-speed clock tree simulation","authors":"Xin Li, Xuan Zeng, Dian Zhou, X. Ling","doi":"10.1109/ISCAS.2002.1009806","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009806","url":null,"abstract":"In this paper, we propose a fast wavelet collocation algorithm for high-speed clock tree simulation. Taking advantage of the specific structure of clock trees and the superior computational property of wavelets, the proposed algorithm presents the following merits. (1) It can perform both transient simulation and steady-state analysis with arbitrary input. (2) It employs nonlinear buffer model and nonuniform interconnect wire model. (3) It has a low computational complexity O(N) and can deal with considerably large circuits. (4) The proposed wavelet method works in time domain so that the simulation error in time domain can be well-controlled. Numerical experiment results demonstrate the promising features of the proposed algorithm in high-speed clock tree simulations.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129928615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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