Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010680
M. Lee, R. Anna, Jui-Chu Lee, S. Parker, K. Newton
We propose a scalable RF subcircuit FET model using BSIM3v3 by adding one of BSIM4's Intrinsic Input Resistance (IIR) models (rgateMod=3) for S/sub 11/ scalability as well as a simple RC substrate network with well defined intrinsic FET's parasitic estimation including partitioned junction diodes for S/sub 22/ scalability. Using this simple model, we could achieve a reasonable scalability with variations of L, W, V/sub GS/, and V/sub DS/ for S/sub 11/ up to 25 GHz. We also suggest new S-parameter test structure for FETs with Ring Substrate Contact (RSC). This new layout scheme allows for improved S/sub 22/ scalability up to about 10 GHz; as well as reduces the punch through effect in DC I-V characteristic of large width NFETs. In addition, comparing to NFETs without RSC, we also report substantial R/sub sub/ lowering, FT and NF/sub min/ worsening, and C/sub sub/ influence on S/sub 22/ contours for NFETs with RSC in detail.
{"title":"A scalable BSIM3v3 RF model for multi-finger NMOSFETs with ring substrate contact","authors":"M. Lee, R. Anna, Jui-Chu Lee, S. Parker, K. Newton","doi":"10.1109/ISCAS.2002.1010680","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010680","url":null,"abstract":"We propose a scalable RF subcircuit FET model using BSIM3v3 by adding one of BSIM4's Intrinsic Input Resistance (IIR) models (rgateMod=3) for S/sub 11/ scalability as well as a simple RC substrate network with well defined intrinsic FET's parasitic estimation including partitioned junction diodes for S/sub 22/ scalability. Using this simple model, we could achieve a reasonable scalability with variations of L, W, V/sub GS/, and V/sub DS/ for S/sub 11/ up to 25 GHz. We also suggest new S-parameter test structure for FETs with Ring Substrate Contact (RSC). This new layout scheme allows for improved S/sub 22/ scalability up to about 10 GHz; as well as reduces the punch through effect in DC I-V characteristic of large width NFETs. In addition, comparing to NFETs without RSC, we also report substantial R/sub sub/ lowering, FT and NF/sub min/ worsening, and C/sub sub/ influence on S/sub 22/ contours for NFETs with RSC in detail.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115068490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1011494
Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang
In this paper, we develop a new genetic algorithm that can efficiently solve the floorplan area optimization problem. The algorithm merges the properties of encoding schemes of slicing trees and the evolutional mechanism of genetic algorithms. A novel genetic operator, which always inherits good properties from ancestors in the algorithm, is proposed to effectively explore solution space. Experimental results show that the developed algorithm achieves comparable computation time and performance quality to the nonslicing state-of-the-art ones.
{"title":"An efficient genetic algorithm for slicing floorplan area optimization","authors":"Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang","doi":"10.1109/ISCAS.2002.1011494","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1011494","url":null,"abstract":"In this paper, we develop a new genetic algorithm that can efficiently solve the floorplan area optimization problem. The algorithm merges the properties of encoding schemes of slicing trees and the evolutional mechanism of genetic algorithms. A novel genetic operator, which always inherits good properties from ancestors in the algorithm, is proposed to effectively explore solution space. Experimental results show that the developed algorithm achieves comparable computation time and performance quality to the nonslicing state-of-the-art ones.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"383 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122351994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1011001
M. Caldari, M. Conti, P. Crippa, S. Orcioni, M. Sbrega, C. Turchetti
Important changes are taking place in the EDA world as System-on-Chip (SoC) IC products create new market segments. These ICs have multiple complex cores that need to be integrated in order to allow the chip to perform the complete system function. At the moment chip-processing equipment is capable of producing technology that is far more advanced than what the design tools can do. This design gap can be reduced by the use of new tools and methodologies based on high levels of electronic systems abstraction. Object-oriented techniques and languages have been proven to significantly increase engineering efficiency in hardware development. Many benefits are expected from their introduction into electronic modeling. Among them are better support for model reusability and flexibility, more efficient system modeling, and more possibilities in design space exploration and prototyping. In this paper we present an object-oriented methodology used to create the models of USB device and bus interface protocol layers.
{"title":"Object-oriented design methodology applied to the modeling of USB device and bus interface layers","authors":"M. Caldari, M. Conti, P. Crippa, S. Orcioni, M. Sbrega, C. Turchetti","doi":"10.1109/ISCAS.2002.1011001","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1011001","url":null,"abstract":"Important changes are taking place in the EDA world as System-on-Chip (SoC) IC products create new market segments. These ICs have multiple complex cores that need to be integrated in order to allow the chip to perform the complete system function. At the moment chip-processing equipment is capable of producing technology that is far more advanced than what the design tools can do. This design gap can be reduced by the use of new tools and methodologies based on high levels of electronic systems abstraction. Object-oriented techniques and languages have been proven to significantly increase engineering efficiency in hardware development. Many benefits are expected from their introduction into electronic modeling. Among them are better support for model reusability and flexibility, more efficient system modeling, and more possibilities in design space exploration and prototyping. In this paper we present an object-oriented methodology used to create the models of USB device and bus interface protocol layers.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122404937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010791
I. C. Baykal, R. Muscedere, G. Jullien
Hash functions are one way functions which are used in cryptography to ensure integrity of files by creating a binary signature specific to that file. A family of special hash functions are developed, which are simple enough to fit into a small FPGA and can generate one dimensional signatures of repeating texture images. While these hash functions are sensitive enough to detect small changes and defects in texture, they are immune to change in illumination and contrast. Analyses of these signatures and determination of the parameters of the hash functions are presented.
{"title":"On the use of hash functions for defect detection in textures for in-camera web inspection systems","authors":"I. C. Baykal, R. Muscedere, G. Jullien","doi":"10.1109/ISCAS.2002.1010791","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010791","url":null,"abstract":"Hash functions are one way functions which are used in cryptography to ensure integrity of files by creating a binary signature specific to that file. A family of special hash functions are developed, which are simple enough to fit into a small FPGA and can generate one dimensional signatures of repeating texture images. While these hash functions are sensitive enough to detect small changes and defects in texture, they are immune to change in illumination and contrast. Analyses of these signatures and determination of the parameters of the hash functions are presented.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122570850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1011003
K. L. Parthasarathy, Le Jin, Degang Chen, R. Geiger
A new approach for measuring the INL and DNL of an A/D converter that uses histogram information is introduced. Unlike most existing algorithms, this method does not require the generation of accurate input signals so offers potential for use in a Built-in Self-Test (BIST) environment. Multiple inputs are presented to the device under test and the histograms obtained at the output are analyzed to characterize both the device and the nonlinear input. Preliminary simulation results for a 10-bit flash ADC suggest this approach can measure INL to the 0.5LSB level with a low spectral purity input signal that is linear to less than the 4-bit level.
{"title":"A modified histogram approach for accurate self-characterization of analog-to-digital converters","authors":"K. L. Parthasarathy, Le Jin, Degang Chen, R. Geiger","doi":"10.1109/ISCAS.2002.1011003","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1011003","url":null,"abstract":"A new approach for measuring the INL and DNL of an A/D converter that uses histogram information is introduced. Unlike most existing algorithms, this method does not require the generation of accurate input signals so offers potential for use in a Built-in Self-Test (BIST) environment. Multiple inputs are presented to the device under test and the histograms obtained at the output are analyzed to characterize both the device and the nonlinear input. Preliminary simulation results for a 10-bit flash ADC suggest this approach can measure INL to the 0.5LSB level with a low spectral purity input signal that is linear to less than the 4-bit level.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122680673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010237
D. Shang, F. Xia, A. Yakovlev
In asynchronous circuit synthesis, the direct translation method, whereby circuits are derived from Petri net (PN) specifications directly, has not evolved any automatic tools. This paper describes a design method based on direct translation techniques, incorporating refinement, optimization and an automatic tool.
{"title":"Asynchronous circuit synthesis via direct translation","authors":"D. Shang, F. Xia, A. Yakovlev","doi":"10.1109/ISCAS.2002.1010237","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010237","url":null,"abstract":"In asynchronous circuit synthesis, the direct translation method, whereby circuits are derived from Petri net (PN) specifications directly, has not evolved any automatic tools. This paper describes a design method based on direct translation techniques, incorporating refinement, optimization and an automatic tool.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114274965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010722
E. Rodríguez-Villegas, J. Quintana, M. Avedillo, A. Rueda
Low power consumption is attractive because of portability and reliability considerations. One way to reduce this power consumption is lowering the supply voltage. However, low supply voltages leads to reduced time performance if the transistor threshold voltage is not scaled accordingly. To solve this, technologies with reduced threshold voltage devices have emerged. Instead, in this paper we resort to a circuit technique based on floating gate devices in order to lower the threshold voltage. It allows fast operation of logic gates at a low supply voltage in standard technologies. The feasibility of the proposed technique is shown experimentally by a fabricated test chip working at a supply voltage of 0.4 V.
{"title":"High-speed low-power logic gates using floating gates","authors":"E. Rodríguez-Villegas, J. Quintana, M. Avedillo, A. Rueda","doi":"10.1109/ISCAS.2002.1010722","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010722","url":null,"abstract":"Low power consumption is attractive because of portability and reliability considerations. One way to reduce this power consumption is lowering the supply voltage. However, low supply voltages leads to reduced time performance if the transistor threshold voltage is not scaled accordingly. To solve this, technologies with reduced threshold voltage devices have emerged. Instead, in this paper we resort to a circuit technique based on floating gate devices in order to lower the threshold voltage. It allows fast operation of logic gates at a low supply voltage in standard technologies. The feasibility of the proposed technique is shown experimentally by a fabricated test chip working at a supply voltage of 0.4 V.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114603546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010256
Yan Wang, H. Lam, C. Tsui, R. Cheng, W. Mow
In this paper, we describe a low complexity orthogonal frequency-division multiplexing (OFDM) receiver using Log-FFT for coded OFDM system. The complexity of the Log-FFT depends on the size of the look-up table, which is determined by the bit width of logarithmic number systems (LNS) representation. In coded OFDM system, simulation results show that there is no degradation in bit error rate performance when only two fractional bits are used for the LNS. As the bit width is so small, the look-up table can be easily implemented using a few combinational logic gates. Comparing the complexity and power consumption of the Log-FFT butterfly module with those of fixed point FFT butterfly module, about 60% reduction can be achieved.
{"title":"Low complexity OFDM receiver using Log-FFT for coded OFDM system","authors":"Yan Wang, H. Lam, C. Tsui, R. Cheng, W. Mow","doi":"10.1109/ISCAS.2002.1010256","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010256","url":null,"abstract":"In this paper, we describe a low complexity orthogonal frequency-division multiplexing (OFDM) receiver using Log-FFT for coded OFDM system. The complexity of the Log-FFT depends on the size of the look-up table, which is determined by the bit width of logarithmic number systems (LNS) representation. In coded OFDM system, simulation results show that there is no degradation in bit error rate performance when only two fractional bits are used for the LNS. As the bit width is so small, the look-up table can be easily implemented using a few combinational logic gates. Comparing the complexity and power consumption of the Log-FFT butterfly module with those of fixed point FFT butterfly module, about 60% reduction can be achieved.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121997886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010591
M. Hasan, T. Arslan
A novel scheme is presented for coefficient address generation in VLSI implementation of FFT processors. The scheme involves manipulation of address lines taking into consideration coefficient addresses required at various FFT stages. We show with the aid of examples that the scheme can lead to more efficient hardware realisations, with significant reduction in hardware for all FFT lengths. This leads to faster, more power and area efficient realisation of FFT processors than approaches published to date. The paper describes the scheme, its implementation in hardware, and presents results showing more than 80% reduction in area and power for almost all FFT lengths.
{"title":"A coefficient memory addressing scheme for VLSI implementation of FFT processors","authors":"M. Hasan, T. Arslan","doi":"10.1109/ISCAS.2002.1010591","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010591","url":null,"abstract":"A novel scheme is presented for coefficient address generation in VLSI implementation of FFT processors. The scheme involves manipulation of address lines taking into consideration coefficient addresses required at various FFT stages. We show with the aid of examples that the scheme can lead to more efficient hardware realisations, with significant reduction in hardware for all FFT lengths. This leads to faster, more power and area efficient realisation of FFT processors than approaches published to date. The paper describes the scheme, its implementation in hardware, and presents results showing more than 80% reduction in area and power for almost all FFT lengths.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116622702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010658
Y. Hsiao, Hung-Der Lin, Kun-Bin Lee, C. Jen
This paper presents a high-speed, memory-saving architecture for the embedded block coding algorithm in JPEG2000. The architecture is based on the proposed memory-saving algorithm that can achieve 4 K bits reduction in the memory requirement (20% less than conventional approaches) without degrading the delay of the critical path. By exploiting the characteristic that the input symbols of the arithmetic coder in JPEG200 have a highly skewed distribution, a simple renormalization strategy is adopted for the code-string register in our pipelined MQ coder design to enhance the clock rate. The overall design is fully implemented in a chip using TSMC 0.35 /spl mu/m CMOS technology. The chip can operate up to 142 MHz at post-layout simulation and is capable of many applications.
本文提出了一种高速、节省内存的JPEG2000嵌入式分组编码算法体系结构。该架构基于所提出的内存节省算法，该算法可以在不降低关键路径延迟的情况下将内存需求减少4 K位(比传统方法减少20%)。利用JPEG200中算术编码器输入符号高度偏斜分布的特点，在流水线MQ编码器设计中对码串寄存器采用简单的重整化策略来提高时钟速率。整体设计完全采用台积电0.35 /spl μ m CMOS技术在芯片上实现。该芯片可在布局后仿真时工作高达142兆赫，可用于许多应用。
{"title":"High-speed memory-saving architecture for the embedded block coding in JPEG2000","authors":"Y. Hsiao, Hung-Der Lin, Kun-Bin Lee, C. Jen","doi":"10.1109/ISCAS.2002.1010658","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010658","url":null,"abstract":"This paper presents a high-speed, memory-saving architecture for the embedded block coding algorithm in JPEG2000. The architecture is based on the proposed memory-saving algorithm that can achieve 4 K bits reduction in the memory requirement (20% less than conventional approaches) without degrading the delay of the critical path. By exploiting the characteristic that the input symbols of the arithmetic coder in JPEG200 have a highly skewed distribution, a simple renormalization strategy is adopted for the code-string register in our pipelined MQ coder design to enhance the clock rate. The overall design is fully implemented in a chip using TSMC 0.35 /spl mu/m CMOS technology. The chip can operate up to 142 MHz at post-layout simulation and is capable of many applications.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116832948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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