Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010188
Ye-Ming Li, J. Connelly
This paper reveals the frequency-dependent behavior of the effective positive conductance in a passive LC tank circuit embedded in a voltage-controlled oscillator, (VCO). This frequency-dependent behavior of the effective positive conductance makes the signal level of the. VCO also frequency dependent. Moreover, this effective positive conductance is dominated by the series resistance of the inductor and sets the criteria for minimizing the tank current to provide a desired output signal level.
{"title":"Modeling a resonant LC tank circuit embedded in a VCO","authors":"Ye-Ming Li, J. Connelly","doi":"10.1109/ISCAS.2002.1010188","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010188","url":null,"abstract":"This paper reveals the frequency-dependent behavior of the effective positive conductance in a passive LC tank circuit embedded in a voltage-controlled oscillator, (VCO). This frequency-dependent behavior of the effective positive conductance makes the signal level of the. VCO also frequency dependent. Moreover, this effective positive conductance is dominated by the series resistance of the inductor and sets the criteria for minimizing the tank current to provide a desired output signal level.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117192074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010199
Shiwei Zhang, P. Rajan
In this paper independent component analysis (ICA) is used to test the robustness of watermarked image. By applying suitable ICA forward transformation, the distributions of the cover image and the watermark are modified. The cover image and the watermark are estimated by using a nonlinear filter and the inverse transform matrix. The preliminary experiments show that ICA attack not only influences the hidden information but also improves the image quality for reasonable embedding strengths.
{"title":"Independent component analysis of digital image watermarking","authors":"Shiwei Zhang, P. Rajan","doi":"10.1109/ISCAS.2002.1010199","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010199","url":null,"abstract":"In this paper independent component analysis (ICA) is used to test the robustness of watermarked image. By applying suitable ICA forward transformation, the distributions of the cover image and the watermark are modified. The cover image and the watermark are estimated by using a nonlinear filter and the inverse transform matrix. The preliminary experiments show that ICA attack not only influences the hidden information but also improves the image quality for reasonable embedding strengths.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117198919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010420
F. Mendoza-Hernandez, M. L. Aranda, V. Champac, A. Díaz-Sánchez
Noise issues are becoming a main concern in digital systems due to the aggressive scaling trends in devices and interconnections. To address this problem, we present a new noise-tolerant dynamic circuit technique suitable for pipelined dynamic digital circuits. Simulation results for a CMOS AND gate show that the proposed technique has an improvement in the ANTE of 3.4/spl times/ over conventional dynamic logic. The improvement in the delay-ANTE quotient is 2.8/spl times/ over conventional dynamic logic, 2.0/spl times/ over the twin-transistor technique and 1.7/spl times/ over Bobba's technique. A 4-bit full-adder simulated using the proposed technique improves ANTE by 2.1/spl times/ over the conventional dynamic circuit.
{"title":"A new technique for noise-tolerant pipelined dynamic digital circuits","authors":"F. Mendoza-Hernandez, M. L. Aranda, V. Champac, A. Díaz-Sánchez","doi":"10.1109/ISCAS.2002.1010420","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010420","url":null,"abstract":"Noise issues are becoming a main concern in digital systems due to the aggressive scaling trends in devices and interconnections. To address this problem, we present a new noise-tolerant dynamic circuit technique suitable for pipelined dynamic digital circuits. Simulation results for a CMOS AND gate show that the proposed technique has an improvement in the ANTE of 3.4/spl times/ over conventional dynamic logic. The improvement in the delay-ANTE quotient is 2.8/spl times/ over conventional dynamic logic, 2.0/spl times/ over the twin-transistor technique and 1.7/spl times/ over Bobba's technique. A 4-bit full-adder simulated using the proposed technique improves ANTE by 2.1/spl times/ over the conventional dynamic circuit.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117287023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009770
R. Srivatsa, W. Jenkins
Adaptive digital filters can be designed with hardware redundancy so they can continue operating effectively after the occurrence of certain types of hardware failures, thereby achieving reliability through a mechanism known as adaptive fault tolerance. It is known that the extra degrees of freedom provided by properly added hardware redundancy gives many equivalent optimal solutions within the coefficient parameter space. This paper investigates the convergence properties of an adaptive fault tolerant FIR filter when temporary noise-induced errors occur.
{"title":"Learning characteristics of adaptive fault tolerant filters in the presence of transient errors","authors":"R. Srivatsa, W. Jenkins","doi":"10.1109/ISCAS.2002.1009770","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009770","url":null,"abstract":"Adaptive digital filters can be designed with hardware redundancy so they can continue operating effectively after the occurrence of certain types of hardware failures, thereby achieving reliability through a mechanism known as adaptive fault tolerance. It is known that the extra degrees of freedom provided by properly added hardware redundancy gives many equivalent optimal solutions within the coefficient parameter space. This paper investigates the convergence properties of an adaptive fault tolerant FIR filter when temporary noise-induced errors occur.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121120495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009842
W. Aloisi, G. Giustolisi, G. Palumbo
A thorough analysis of the behavior of a simple gain-boosted telescopic amplifier in terms of both the frequency and time domain is performed. The well-known slow-settling component is analyzed and a constraint for eliminating its effect is also given. Moreover, a procedure for designing the amplifier, based on the comparison of its time response to the time response of a two-pole system is reported, too.
{"title":"Analysis and optimization of gain-boosted telescopic amplifiers","authors":"W. Aloisi, G. Giustolisi, G. Palumbo","doi":"10.1109/ISCAS.2002.1009842","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009842","url":null,"abstract":"A thorough analysis of the behavior of a simple gain-boosted telescopic amplifier in terms of both the frequency and time domain is performed. The well-known slow-settling component is analyzed and a constraint for eliminating its effect is also given. Moreover, a procedure for designing the amplifier, based on the comparison of its time response to the time response of a two-pole system is reported, too.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127085603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010521
J. Shor, Y. Sofer, Y. Polansky, E. Maayan
A new regulator concept is described which is based on stacked diode-connected transistors rather that resistor based voltage dividers. The circuit provides an accurate voltage which is driven to a capacitive load by a class AB driver. The regulator has a significantly lower power consumption than conventional regulators, and is suitable for providing regulated boosted wordline voltages for EPROM devices.
{"title":"Low power voltage regulator for EPROM applications","authors":"J. Shor, Y. Sofer, Y. Polansky, E. Maayan","doi":"10.1109/ISCAS.2002.1010521","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010521","url":null,"abstract":"A new regulator concept is described which is based on stacked diode-connected transistors rather that resistor based voltage dividers. The circuit provides an accurate voltage which is driven to a capacitive load by a class AB driver. The regulator has a significantly lower power consumption than conventional regulators, and is suitable for providing regulated boosted wordline voltages for EPROM devices.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127185910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010365
T. Schimming, M. Hasler, F. Bizzarri, M. Storace
The recent proposal of ergodic chaos shift keying (ECSK) has been able to provide a viable compromise between chaos shift keying (CSK) schemes - using optimal detectors on the upper (performance) boundary - and schemes using synchronization - on the lower (performance) boundary. This compromise is interesting for applications due to the computational complexity of the optimal method, which in practice prohibits its implementation. Previously, the design of an ECSK scheme had been based on a simplistic criterion, i.e. the maximization of the decision variable's mean. This paper provides a systematic approach to optimizing the receiver of an amplitude modulated implementation of ECSK (AM-ECSK) based on the assumption of a Gaussian decision variable.
{"title":"Optimal receiver for ergodic chaos shift keying","authors":"T. Schimming, M. Hasler, F. Bizzarri, M. Storace","doi":"10.1109/ISCAS.2002.1010365","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010365","url":null,"abstract":"The recent proposal of ergodic chaos shift keying (ECSK) has been able to provide a viable compromise between chaos shift keying (CSK) schemes - using optimal detectors on the upper (performance) boundary - and schemes using synchronization - on the lower (performance) boundary. This compromise is interesting for applications due to the computational complexity of the optimal method, which in practice prohibits its implementation. Previously, the design of an ECSK scheme had been based on a simplistic criterion, i.e. the maximization of the decision variable's mean. This paper provides a systematic approach to optimizing the receiver of an amplitude modulated implementation of ECSK (AM-ECSK) based on the assumption of a Gaussian decision variable.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127200366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010277
B. Yarman, A. Aksen, A. Kilinc
With the advancement of the manufacturing technologies to produce new generation analog/digital communication systems, immitance data modelling has gained renewed importance in the literature. Specifically, models are utilised for behaviour characterisation, simulation of physical devices or to design sub-systems with active and passive solid-state components. Therefore, in this paper, new computer aided tools are presented to model one port immitance data by means of linear interpolation techniques. It is remarkable to observe that complex electrical behaviour of physical devices can be simulated with the models built utilising the linear interpolation of a few properly selected measured immitance data. An antenna example is presented to exhibit the implementation of the proposed techniques. It is expected that the new modelling tools will be employed to provide initial circuit topologies to the commercially available analysis/simulation and design packages.
{"title":"Immitance data modelling via linear interpolation techniques","authors":"B. Yarman, A. Aksen, A. Kilinc","doi":"10.1109/ISCAS.2002.1010277","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010277","url":null,"abstract":"With the advancement of the manufacturing technologies to produce new generation analog/digital communication systems, immitance data modelling has gained renewed importance in the literature. Specifically, models are utilised for behaviour characterisation, simulation of physical devices or to design sub-systems with active and passive solid-state components. Therefore, in this paper, new computer aided tools are presented to model one port immitance data by means of linear interpolation techniques. It is remarkable to observe that complex electrical behaviour of physical devices can be simulated with the models built utilising the linear interpolation of a few properly selected measured immitance data. An antenna example is presented to exhibit the implementation of the proposed techniques. It is expected that the new modelling tools will be employed to provide initial circuit topologies to the commercially available analysis/simulation and design packages.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127350721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009835
A. Bellini, E. Carpanoni, G. Frassi, Monica Tesauri, E. Ugolotti
The project deals with the design and realization of a dedicated board DSP-based for the processing of audio signals for automotive applications (DIGIcar). The I/O interface of the board is composed of two stereo inputs and two stereo outputs. The prototype was realized in a four layer PCB with SMD components. The layers were designed in order to reduce high frequency effects of digital signals on analog audio signals. The DIGIcar board was tested stand-alone with an Audio Precision System 2022. Experiments were performed inside a car too, where the DIGIcar board was interfaced with a four channel power amplifier and connected between audio source and car loudspeakers. A development tool in MATLAB was exploited to synthesize the suitable equalizing filters given standard car acoustic measurements. Then the filters are stored in the board flash EEPROM. A few options are available to tailor the equalizer for different cars. Listening tests and acoustic measurements show the effectiveness and the functionality of the designed board.
{"title":"Design of a DSP-based 24 bit digital audio equalizer for automotive applications","authors":"A. Bellini, E. Carpanoni, G. Frassi, Monica Tesauri, E. Ugolotti","doi":"10.1109/ISCAS.2002.1009835","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009835","url":null,"abstract":"The project deals with the design and realization of a dedicated board DSP-based for the processing of audio signals for automotive applications (DIGIcar). The I/O interface of the board is composed of two stereo inputs and two stereo outputs. The prototype was realized in a four layer PCB with SMD components. The layers were designed in order to reduce high frequency effects of digital signals on analog audio signals. The DIGIcar board was tested stand-alone with an Audio Precision System 2022. Experiments were performed inside a car too, where the DIGIcar board was interfaced with a four channel power amplifier and connected between audio source and car loudspeakers. A development tool in MATLAB was exploited to synthesize the suitable equalizing filters given standard car acoustic measurements. Then the filters are stored in the board flash EEPROM. A few options are available to tailor the equalizer for different cars. Listening tests and acoustic measurements show the effectiveness and the functionality of the designed board.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125806064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010925
G. Alpaydin
An automatic analog integrated circuit synthesis system driven by an evolutionary approach is presented. One of the novel features of this system is a high performance optimization algorithm based on the combination of evolutionary strategies and simulated annealing. Modeling of DC parameters is done via a fast DC simulator developed for this purpose whereas modeling of AC parameters is done either with user-defined equations or with neural-fuzzy performance models trained from SPICE simulations. Another novel feature of the system is the incorporation of matching properties of devices. The synthesis system has been tested on several independent examples. A prototype chip containing a synthesized circuit has been manufactured and measurement results have demonstrated the validity of the synthesis system also on silicon.
{"title":"Evolution based automatic synthesis of analog integrated circuits","authors":"G. Alpaydin","doi":"10.1109/ISCAS.2002.1010925","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010925","url":null,"abstract":"An automatic analog integrated circuit synthesis system driven by an evolutionary approach is presented. One of the novel features of this system is a high performance optimization algorithm based on the combination of evolutionary strategies and simulated annealing. Modeling of DC parameters is done via a fast DC simulator developed for this purpose whereas modeling of AC parameters is done either with user-defined equations or with neural-fuzzy performance models trained from SPICE simulations. Another novel feature of the system is the incorporation of matching properties of devices. The synthesis system has been tested on several independent examples. A prototype chip containing a synthesized circuit has been manufactured and measurement results have demonstrated the validity of the synthesis system also on silicon.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125823464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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