Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010212
Y. Uchida, M. Ise, T. Onoye, I. Shirakawa, I. Arungsrisangchai
A VLSI architecture dedicated to W-CDMA (Wideband Code Division Multiple Access) baseband modem is described, with the main theme focused on the cell searcher and PIL (Prime InterLeaver). A search algorithm is refined for the cell searcher to minimize the circuit size, maintaining the operating throughput. In addition, a time-shared scheme is adopted for the turbo encoding/decoding, aiming at the maximization of the hardware sharing in the encoding/decoding process. Finally, implementation results are shown to demonstrate that the proposed architecture can contribute much toward the practical low-power implementation of W-CDMA baseband modem LSI.
{"title":"VLSI architecture of digital matched filter and prime interleaver for W-CDMA","authors":"Y. Uchida, M. Ise, T. Onoye, I. Shirakawa, I. Arungsrisangchai","doi":"10.1109/ISCAS.2002.1010212","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010212","url":null,"abstract":"A VLSI architecture dedicated to W-CDMA (Wideband Code Division Multiple Access) baseband modem is described, with the main theme focused on the cell searcher and PIL (Prime InterLeaver). A search algorithm is refined for the cell searcher to minimize the circuit size, maintaining the operating throughput. In addition, a time-shared scheme is adopted for the turbo encoding/decoding, aiming at the maximization of the hardware sharing in the encoding/decoding process. Finally, implementation results are shown to demonstrate that the proposed architecture can contribute much toward the practical low-power implementation of W-CDMA baseband modem LSI.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126787224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009820
S. Itakura, Y. Tanji, T. Otake, Mamoru Tanaka
The progressive image reconstruction via CNN is presented, where the CNN template mapping an image to a domain concerned with the coefficients of the radial basis function network for image interpolation is provided. The analog CNN dynamics achieves massively parallel computing, thus, the proposed procedure would create a new paradigm of CNN at the point of very high-speed image decoding and encoding. The simulation results shows good performance of the proposed CNN for image reconstruction.
{"title":"Progressive image reconstruction via cellular neural networks","authors":"S. Itakura, Y. Tanji, T. Otake, Mamoru Tanaka","doi":"10.1109/ISCAS.2002.1009820","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009820","url":null,"abstract":"The progressive image reconstruction via CNN is presented, where the CNN template mapping an image to a domain concerned with the coefficients of the radial basis function network for image interpolation is provided. The analog CNN dynamics achieves massively parallel computing, thus, the proposed procedure would create a new paradigm of CNN at the point of very high-speed image decoding and encoding. The simulation results shows good performance of the proposed CNN for image reconstruction.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130635196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009885
Mika Kontiala, Aarne Heinonen, J. Nurmi
Two circuit implementations were considered. First, the VHDL description of a matched filter was synthesized, and the design was completed with a place&route tool. Second, a full-custom circuit was designed with the same structure to compare the power dissipation of the circuits. A low-power flip-flop is introduced. Both circuits were extensively simulated with several 0.35 /spl mu/m transistor models, different supply voltages, netlists including parasitic data, and temperature range of -55 to +125 degrees. The full-custom circuit consumed 25% of the power of the standard-cell circuit.
{"title":"Low-power methodology issues in digital circuit design","authors":"Mika Kontiala, Aarne Heinonen, J. Nurmi","doi":"10.1109/ISCAS.2002.1009885","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009885","url":null,"abstract":"Two circuit implementations were considered. First, the VHDL description of a matched filter was synthesized, and the design was completed with a place&route tool. Second, a full-custom circuit was designed with the same structure to compare the power dissipation of the circuits. A low-power flip-flop is introduced. Both circuits were extensively simulated with several 0.35 /spl mu/m transistor models, different supply voltages, netlists including parasitic data, and temperature range of -55 to +125 degrees. The full-custom circuit consumed 25% of the power of the standard-cell circuit.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123350132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010354
B. Lin, Tsung-Liang Hung
A unity power factor converter using neutral point diode clamped scheme is proposed. Four power switches are used in the proposed single-phase half-bridge converter. The voltage stress of each power switch in the proposed converter is equal to half of DC bus voltage instead of full DC link voltage in the conventional switching mode rectifier. A hysteresis current comparator is used to track the line current command. The DC bus voltage is controlled by a voltage controller to maintain a constant reference value. The applications of the proposed control algorithm also cover the active power filter (APF) and uninterruptible power supply (UPS). The system model and control algorithm are described and analyzed. The experimental results based on a laboratory prototype were performed to verify the effectiveness of the proposed control strategies.
{"title":"Development of a single-phase half-bridge neutral point clamped converter and its applications","authors":"B. Lin, Tsung-Liang Hung","doi":"10.1109/ISCAS.2002.1010354","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010354","url":null,"abstract":"A unity power factor converter using neutral point diode clamped scheme is proposed. Four power switches are used in the proposed single-phase half-bridge converter. The voltage stress of each power switch in the proposed converter is equal to half of DC bus voltage instead of full DC link voltage in the conventional switching mode rectifier. A hysteresis current comparator is used to track the line current command. The DC bus voltage is controlled by a voltage controller to maintain a constant reference value. The applications of the proposed control algorithm also cover the active power filter (APF) and uninterruptible power supply (UPS). The system model and control algorithm are described and analyzed. The experimental results based on a laboratory prototype were performed to verify the effectiveness of the proposed control strategies.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"2 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123669171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010661
A. Chrisanthopoulos, Y. Tsiatouhas, A. Arapoyanni, T. Haniotakis
In this paper a new two-stage sensing scheme suitable for current sensing in SRAM read operation is presented. The proposed scheme provides fast response with low silicon area requirements, since it incorporates only three transistors in the pitch of the bit lines for the sensing of the stored data in the selected memory cell. Process and temperature variation related simulations are provided in order to explore the operating range of the sensors in various conditions. In addition, comparison results are given with respect to a conventional sensing scheme. Finally, a compact layout design is presented to illustrate the area efficiency of the proposed sensing architecture.
{"title":"SRAM oriented memory sense amplifier design in 0.18 /spl mu/m CMOS technology","authors":"A. Chrisanthopoulos, Y. Tsiatouhas, A. Arapoyanni, T. Haniotakis","doi":"10.1109/ISCAS.2002.1010661","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010661","url":null,"abstract":"In this paper a new two-stage sensing scheme suitable for current sensing in SRAM read operation is presented. The proposed scheme provides fast response with low silicon area requirements, since it incorporates only three transistors in the pitch of the bit lines for the sensing of the stored data in the selected memory cell. Process and temperature variation related simulations are provided in order to explore the operating range of the sensors in various conditions. In addition, comparison results are given with respect to a conventional sensing scheme. Finally, a compact layout design is presented to illustrate the area efficiency of the proposed sensing architecture.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121432268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010842
T. Uemura, P. Mazumder
Recently, high-speed circuit applications using resonant tunnel diodes (RTDs) have attracted much attention due to their fast switching speed and increased Boolean functionality. For example, high-speed operation up to 35 Gb/s of a flip-flop circuit has been demonstrated using a pair of series connected RTDs, called a mono-stable bistable transition logic element (MOBILE) (K. Maezawa et al, IEEE Electron Dev. Lett., vol. 19, no. 3, pp. 80-82, 1998). It has been noted, however, that the MOBILE-type circuit has a critical value for the rise time of the supplied clock pulse, T/sub R//sup C/, which limits the operation speed (T.C.L.G. Sollner et al, Proc. Int. Semicond. Dev. Res. Symp., pp. 307-310, 1993). Several switching time analyses have been performed based on numerical simulation (K. Maezawa, Jpn. J. Appl. Phys. vol. 34, no. 213, pp. 1213-1217, 1995; Y. Ohno et al, IEICE Trans. Electron., vol. E79-C, no. 11, pp. 1530-1536, 1996). From the circuit design point of view, however, a closed form of an analytical expression of T/sub R//sup C/ is necessary. In this paper, analytical expressions of T/sub R//sup C/ as well as a minimum total transition time are derived. The circuit parameter dependence of the operating speed is also analyzed.
{"title":"Rise time analysis of MOBILE circuit","authors":"T. Uemura, P. Mazumder","doi":"10.1109/ISCAS.2002.1010842","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010842","url":null,"abstract":"Recently, high-speed circuit applications using resonant tunnel diodes (RTDs) have attracted much attention due to their fast switching speed and increased Boolean functionality. For example, high-speed operation up to 35 Gb/s of a flip-flop circuit has been demonstrated using a pair of series connected RTDs, called a mono-stable bistable transition logic element (MOBILE) (K. Maezawa et al, IEEE Electron Dev. Lett., vol. 19, no. 3, pp. 80-82, 1998). It has been noted, however, that the MOBILE-type circuit has a critical value for the rise time of the supplied clock pulse, T/sub R//sup C/, which limits the operation speed (T.C.L.G. Sollner et al, Proc. Int. Semicond. Dev. Res. Symp., pp. 307-310, 1993). Several switching time analyses have been performed based on numerical simulation (K. Maezawa, Jpn. J. Appl. Phys. vol. 34, no. 213, pp. 1213-1217, 1995; Y. Ohno et al, IEICE Trans. Electron., vol. E79-C, no. 11, pp. 1530-1536, 1996). From the circuit design point of view, however, a closed form of an analytical expression of T/sub R//sup C/ is necessary. In this paper, analytical expressions of T/sub R//sup C/ as well as a minimum total transition time are derived. The circuit parameter dependence of the operating speed is also analyzed.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116492640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010694
C. Dafis, C. Nwankpa
Traditionally, a nonlinear algebraic model of the power system is used to determine the system observability. In particular, the sensitivity of the system measurements (real and reactive power for example) to the change in the system states (bus voltages and angles) is used as a measure of observability, derived from the power system state-estimation problem. It ignores, however, the nonlinear dynamics of the system related to generator performance, nonlinear components, etc. The proposed observability formulation accounts for these nonlinearities and provides a more comprehensive observability determination. The formulation is derived from a DAE model of the power system, and incorporates the dynamics of the generators present in the system.
{"title":"A nonlinear observability formulation for power systems incorporating generator dynamics","authors":"C. Dafis, C. Nwankpa","doi":"10.1109/ISCAS.2002.1010694","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010694","url":null,"abstract":"Traditionally, a nonlinear algebraic model of the power system is used to determine the system observability. In particular, the sensitivity of the system measurements (real and reactive power for example) to the change in the system states (bus voltages and angles) is used as a measure of observability, derived from the power system state-estimation problem. It ignores, however, the nonlinear dynamics of the system related to generator performance, nonlinear components, etc. The proposed observability formulation accounts for these nonlinearities and provides a more comprehensive observability determination. The formulation is derived from a DAE model of the power system, and incorporates the dynamics of the generators present in the system.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121559412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010306
Ruey-Wen Liu, Hui Luo, Liang Song, Bo Hu, X. Ling
Existing multiple access methods, such as TDMA, CSMA/CA, FDMA, and CDMA, require transmitters be coordinated in order to assure multiple access signals to be separable based on the difference in time domain, frequency domain, or code domain, respectively. These coordinative multiple access methods may suffer co-channel interferences badly from non-coordinative transmitters. In this paper, a new differentiating domain, the autocorrelation of the transmitted signals, is exploited, and a new random multiple access method, based on the principle of Autocorrelation Matching (AM), is developed on top of it. The advantages of having autocorrelation as the differentiation factor for multiple access communications systems include, among others, (1) one FIR vector filter automatically does both the equalization of the designated FIR channel for the purpose of detecting the desired signal and the suppression of all other signals; (2) no training signal is needed for equalization; and (3) the equalization and suppression performance is independent of the noise level.
{"title":"Autocorrelation - a new differentiating domain for multiple access wireless communications","authors":"Ruey-Wen Liu, Hui Luo, Liang Song, Bo Hu, X. Ling","doi":"10.1109/ISCAS.2002.1010306","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010306","url":null,"abstract":"Existing multiple access methods, such as TDMA, CSMA/CA, FDMA, and CDMA, require transmitters be coordinated in order to assure multiple access signals to be separable based on the difference in time domain, frequency domain, or code domain, respectively. These coordinative multiple access methods may suffer co-channel interferences badly from non-coordinative transmitters. In this paper, a new differentiating domain, the autocorrelation of the transmitted signals, is exploited, and a new random multiple access method, based on the principle of Autocorrelation Matching (AM), is developed on top of it. The advantages of having autocorrelation as the differentiation factor for multiple access communications systems include, among others, (1) one FIR vector filter automatically does both the equalization of the designated FIR channel for the purpose of detecting the desired signal and the suppression of all other signals; (2) no training signal is needed for equalization; and (3) the equalization and suppression performance is independent of the noise level.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124347245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010738
Cheng-Shing Wu, A. Wu
In this paper, a multi-path adaptive interpolated FIR (AIFIR)-based echo canceller is presented to perform the echo cancellation in full-duplex digital transmission over DSL. The proposed multi-path approach inherits the concept of the AIFIR-based echo canceller, where the long tail portion is modelled by an adaptive sparse FIR filter. A multi-path structure is addressed to break the inherent design tradeoffs in the conventional AIFIR-based echo canceller. More than one adaptive IFIR filter, modelling the corresponding tail portions of echo path, are employed. Also, an efficient implementation of the Image Compress Filter (ICF) is provided to reduce the complexity in performing the function of multi-ICFs. In addition, we apply the proposed scheme to the design of an echo canceller in an SHDSL transceiver. Computer simulations show that the flexible multi-path AIFIR-based echo canceller can reduce computational complexity 20% compared with previous works. About 60% complexity saving is obtained compared with the direct transversal implementation of an echo canceller.
{"title":"A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller","authors":"Cheng-Shing Wu, A. Wu","doi":"10.1109/ISCAS.2002.1010738","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010738","url":null,"abstract":"In this paper, a multi-path adaptive interpolated FIR (AIFIR)-based echo canceller is presented to perform the echo cancellation in full-duplex digital transmission over DSL. The proposed multi-path approach inherits the concept of the AIFIR-based echo canceller, where the long tail portion is modelled by an adaptive sparse FIR filter. A multi-path structure is addressed to break the inherent design tradeoffs in the conventional AIFIR-based echo canceller. More than one adaptive IFIR filter, modelling the corresponding tail portions of echo path, are employed. Also, an efficient implementation of the Image Compress Filter (ICF) is provided to reduce the complexity in performing the function of multi-ICFs. In addition, we apply the proposed scheme to the design of an echo canceller in an SHDSL transceiver. Computer simulations show that the flexible multi-path AIFIR-based echo canceller can reduce computational complexity 20% compared with previous works. About 60% complexity saving is obtained compared with the direct transversal implementation of an echo canceller.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126314157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1011027
Chih-Yang Hsu, W. Shen
We propose a high efficiency and high accuracy power estimation method for CMOS combinational circuits with grouping and consecutive sampling techniques. We separate input pattern pairs into several groups according to their power characteristics. The consecutive sampling skill is applied to find a shorter subsequence from the original input sequence. Our experimental results demonstrate that the compaction ratios are 1,250(min) and 154(min) with power estimation errors of 3.31 %(avg) and 3.32%(avg) for two sampling strategies.
{"title":"Vector compaction for power estimation with grouping and consecutive sampling techniques","authors":"Chih-Yang Hsu, W. Shen","doi":"10.1109/ISCAS.2002.1011027","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1011027","url":null,"abstract":"We propose a high efficiency and high accuracy power estimation method for CMOS combinational circuits with grouping and consecutive sampling techniques. We separate input pattern pairs into several groups according to their power characteristics. The consecutive sampling skill is applied to find a shorter subsequence from the original input sequence. Our experimental results demonstrate that the compaction ratios are 1,250(min) and 154(min) with power estimation errors of 3.31 %(avg) and 3.32%(avg) for two sampling strategies.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126547290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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