Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1011452
Guijin Wang, Qian Zhang, Wenwu Zhu
Video communication over channels with both bit errors and packet erasures is becoming increasingly important due to the emerging of wireless Internet. To have QoS provision at application level, product code is suited to correct the transmission errors occurring in such channels. In this paper, we presented a novel layered product code for scalable video streaming over the channels with both bit errors and packet losses. An end-to-end architecture is proposed to simultaneously address the error control, packetization and rate-distortion based bit allocation. Once the available network conditions are estimated, the unequal product codes are applied to different layers of scalable video. Specifically, each layer is first divided into blocks with unequal row channel code and unequal column channel code added. Then rate-distortion based bit allocation is proposed to determine the channel rates and the source rate so as to minimize the expected end-to-end distortion. The simulations demonstrated effectiveness of our proposed error protection scheme.
{"title":"Channel-adaptive error protection for scalable video over channels with bit errors and packet erasures","authors":"Guijin Wang, Qian Zhang, Wenwu Zhu","doi":"10.1109/ISCAS.2002.1011452","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1011452","url":null,"abstract":"Video communication over channels with both bit errors and packet erasures is becoming increasingly important due to the emerging of wireless Internet. To have QoS provision at application level, product code is suited to correct the transmission errors occurring in such channels. In this paper, we presented a novel layered product code for scalable video streaming over the channels with both bit errors and packet losses. An end-to-end architecture is proposed to simultaneously address the error control, packetization and rate-distortion based bit allocation. Once the available network conditions are estimated, the unequal product codes are applied to different layers of scalable video. Specifically, each layer is first divided into blocks with unequal row channel code and unequal column channel code added. Then rate-distortion based bit allocation is proposed to determine the channel rates and the source rate so as to minimize the expected end-to-end distortion. The simulations demonstrated effectiveness of our proposed error protection scheme.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"35 139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125939188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010843
R. V. D. Haar, J. Hoekstra, Roelof H. Klunder
With single-electron tunneling (SET) technology it is possible to build electronic circuits with extreme low power properties. These SET circuits must therefore operate in the single electronics (current) regime. To simulate SET circuits in this regime, a SPICE model has been written. In contrast to the prescriptions in the so-called orthodox theory of single-electronics, the SPICE model explores the discrete character of the tunnel current and the tunnel condition. In this paper, a brief description of this SPICE model is given. Several known SET circuits are simulated using this SPICE model and are verified with a well known SET device simulator called SIMON, which is based on the orthodox theory of single-electronics.
{"title":"A SPICE model for single electronics","authors":"R. V. D. Haar, J. Hoekstra, Roelof H. Klunder","doi":"10.1109/ISCAS.2002.1010843","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010843","url":null,"abstract":"With single-electron tunneling (SET) technology it is possible to build electronic circuits with extreme low power properties. These SET circuits must therefore operate in the single electronics (current) regime. To simulate SET circuits in this regime, a SPICE model has been written. In contrast to the prescriptions in the so-called orthodox theory of single-electronics, the SPICE model explores the discrete character of the tunnel current and the tunnel condition. In this paper, a brief description of this SPICE model is given. Several known SET circuits are simulated using this SPICE model and are verified with a well known SET device simulator called SIMON, which is based on the orthodox theory of single-electronics.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123282521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010479
G. Ritzberger, J. Böck, H. Knapp, L. Treitinger, A. Scholtz
A low-power static frequency divider manufactured in 0.4 /spl mu/m/85 GHz-f/sub T/ SiGe bipolar technology with division ratios of 16 and 256 is presented. The circuit is optimized for low power consumption and operates up to 38.9 GHz maximum input frequency consuming only 174 mW from the 3 V supply.
{"title":"38 GHz low-power static frequency divider in SiGe bipolar technology","authors":"G. Ritzberger, J. Böck, H. Knapp, L. Treitinger, A. Scholtz","doi":"10.1109/ISCAS.2002.1010479","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010479","url":null,"abstract":"A low-power static frequency divider manufactured in 0.4 /spl mu/m/85 GHz-f/sub T/ SiGe bipolar technology with division ratios of 16 and 256 is presented. The circuit is optimized for low power consumption and operates up to 38.9 GHz maximum input frequency consuming only 174 mW from the 3 V supply.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123779002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010556
P. Coussy, A. Baganne, E. Martin
Successful integration of IP/VC blocks requires a set of view that provides the appropriate information for each IP block through the design flow for an IP-integration system. In this paper, we present a methodology of IP integration in a System-on a chip (SOC) design, that exploits both IP designer and SOC integrator constraints. First, we describe a method to extract and specify IP functional and timing constraints (I/O sequence transfer constraints) from the IP core. Second, we propose a modeling style of the integration constraints and a technique for merging them with IP constraints. This technique allows the specification and design of an optimized IP interface unit required for IP-socketization. The synthesis output is synthesizable VHDL RT of the interface, a detailed bus-functional model of the IP core towards cosimulation.
{"title":"A design methodology for IP integration","authors":"P. Coussy, A. Baganne, E. Martin","doi":"10.1109/ISCAS.2002.1010556","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010556","url":null,"abstract":"Successful integration of IP/VC blocks requires a set of view that provides the appropriate information for each IP block through the design flow for an IP-integration system. In this paper, we present a methodology of IP integration in a System-on a chip (SOC) design, that exploits both IP designer and SOC integrator constraints. First, we describe a method to extract and specify IP functional and timing constraints (I/O sequence transfer constraints) from the IP core. Second, we propose a modeling style of the integration constraints and a technique for merging them with IP constraints. This technique allows the specification and design of an optimized IP interface unit required for IP-socketization. The synthesis output is synthesizable VHDL RT of the interface, a detailed bus-functional model of the IP core towards cosimulation.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125283149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010444
Xiaohong Sun, K. Laker
This paper analyzes the tonal behavior of an adaptive second-order sigma-delta modulator, which was developed and published by the same authors. Idle channel tones, caused by non-white quantization error, is not desirable in applications where the human ear is the end receiver. Besides their relatively small magnitude tones in the baseband, most sigma-delta modulators produce high-powered tones near f/sub s//2. It is a more serious problem because the clock noise near f/sub s//2 can couple these tones down into the baseband. Various simulations show that the more randomized nature of the aforementioned adaptive architecture makes it more advantageous in tonal behavior, particularly attractive in that it significantly reduces the dominant tone near f/sub s//2, which can not be reduced by dithering in a standard second order single-bit modulator. With comparison to the standard second-order sigma-delta modulators, the results are illustrated in both frequency and time domains.
{"title":"Tonal behavior analysis of an adaptive second-order sigma-delta modulator","authors":"Xiaohong Sun, K. Laker","doi":"10.1109/ISCAS.2002.1010444","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010444","url":null,"abstract":"This paper analyzes the tonal behavior of an adaptive second-order sigma-delta modulator, which was developed and published by the same authors. Idle channel tones, caused by non-white quantization error, is not desirable in applications where the human ear is the end receiver. Besides their relatively small magnitude tones in the baseband, most sigma-delta modulators produce high-powered tones near f/sub s//2. It is a more serious problem because the clock noise near f/sub s//2 can couple these tones down into the baseband. Various simulations show that the more randomized nature of the aforementioned adaptive architecture makes it more advantageous in tonal behavior, particularly attractive in that it significantly reduces the dominant tone near f/sub s//2, which can not be reduced by dithering in a standard second order single-bit modulator. With comparison to the standard second-order sigma-delta modulators, the results are illustrated in both frequency and time domains.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125321591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010226
Q. Luo, J.G. Harris
A novel integration of image compression and sensing is proposed to enhance the performance of a CMOS image sensor. By integrating a compression function onto the sensor focal plane, the image signal to be read out can be significantly reduced and consequently the pixel rate can be increased. This can be applied to overcome the communication bottleneck for high-resolution image sensing and high frame-rate image sensing or for power- and bandwidth-constrained devices such as cell phones. A modified Haar wavelet transform is implemented as the compression scheme. A simple but efficient computation design is developed to implement the transform on-chip.
{"title":"A novel integration of on-sensor wavelet compression for a CMOS imager","authors":"Q. Luo, J.G. Harris","doi":"10.1109/ISCAS.2002.1010226","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010226","url":null,"abstract":"A novel integration of image compression and sensing is proposed to enhance the performance of a CMOS image sensor. By integrating a compression function onto the sensor focal plane, the image signal to be read out can be significantly reduced and consequently the pixel rate can be increased. This can be applied to overcome the communication bottleneck for high-resolution image sensing and high frame-rate image sensing or for power- and bandwidth-constrained devices such as cell phones. A modified Haar wavelet transform is implemented as the compression scheme. A simple but efficient computation design is developed to implement the transform on-chip.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125348831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010628
Yu-Nan Lin, D. Lin
Parallel interference cancellation (PIC) is a widely considered approach to multiuser detection in CDMA communication. While PIC receivers normally involve nonlinear functions, previous performance analyses mainly addressed linear PIC. We find that the performance of purely hardlimiting PIC may not improve after the second stage. In addition, for the two-user case, one stage usually suffices. Further, the performance of hardlimiting PIC does not approach the single-user limit. We also develop approximate expressions for numerical evaluation of the hardlimiting PIC performance. Simulation results agree well with the analysis.
{"title":"Analysis of hardlimiting parallel interference cancellation (PIC) for synchronous CDMA communication","authors":"Yu-Nan Lin, D. Lin","doi":"10.1109/ISCAS.2002.1010628","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010628","url":null,"abstract":"Parallel interference cancellation (PIC) is a widely considered approach to multiuser detection in CDMA communication. While PIC receivers normally involve nonlinear functions, previous performance analyses mainly addressed linear PIC. We find that the performance of purely hardlimiting PIC may not improve after the second stage. In addition, for the two-user case, one stage usually suffices. Further, the performance of hardlimiting PIC does not approach the single-user limit. We also develop approximate expressions for numerical evaluation of the hardlimiting PIC performance. Simulation results agree well with the analysis.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125539680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1011490
M.E. Lee, M.J.T. Smith
Many models for computer generated singing voices have been proposed in the past and have been shown to produce a wide variety of synthesized voices. While many of these models are capable of synthesizing a particular singing voice with high musical quality, they typically are challenged with respect to naturalness, range, the ability to synthesize both male and female voices, as well as the ability to capture the identity of the singer. The analysis-by-synthesis/overlap-add (ABS/OLA) sinusoidal model has proven to be effective in producing high quality voices with manageable computational cost. It is based on the combination of a block overlap-add sinusoidal representation and an analysis-by-synthesis parameter estimation technique. ABS/OLA is flexible enough to allow for modifications such as time and pitch scaling; however, it can suffer from quality degradation under such conditions. This paper presents an analysis/synthesis model that incorporates new methods to improve synthesis. These improvements add to the naturalness and flexibility in controlling perceptually important musical characteristics.
{"title":"Digital singing voice synthesis using a new alternating reflection model","authors":"M.E. Lee, M.J.T. Smith","doi":"10.1109/ISCAS.2002.1011490","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1011490","url":null,"abstract":"Many models for computer generated singing voices have been proposed in the past and have been shown to produce a wide variety of synthesized voices. While many of these models are capable of synthesizing a particular singing voice with high musical quality, they typically are challenged with respect to naturalness, range, the ability to synthesize both male and female voices, as well as the ability to capture the identity of the singer. The analysis-by-synthesis/overlap-add (ABS/OLA) sinusoidal model has proven to be effective in producing high quality voices with manageable computational cost. It is based on the combination of a block overlap-add sinusoidal representation and an analysis-by-synthesis parameter estimation technique. ABS/OLA is flexible enough to allow for modifications such as time and pitch scaling; however, it can suffer from quality degradation under such conditions. This paper presents an analysis/synthesis model that incorporates new methods to improve synthesis. These improvements add to the naturalness and flexibility in controlling perceptually important musical characteristics.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125584897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010214
A. Pérez-Pascual, T. Sansaloni, J. Valls-Coquillat
This paper presents two different FPGA-implementation of radix-4 butterflies suitable for HIPERLAN 2. The two approaches lead to an efficient use of the hardware resources available in the target device and reduces the area with respect to the direct implementation of the radix-4 butterfly. Both methods reduce the area required storing the coefficients. The first one uses the symmetries of coefficients for reducing the number of functions to store; the second one takes advantage of the dual-port capability of the embedded block-RAM.
{"title":"FPGA-based radix-4 butterflies for HIPERLAN/2","authors":"A. Pérez-Pascual, T. Sansaloni, J. Valls-Coquillat","doi":"10.1109/ISCAS.2002.1010214","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010214","url":null,"abstract":"This paper presents two different FPGA-implementation of radix-4 butterflies suitable for HIPERLAN 2. The two approaches lead to an efficient use of the hardware resources available in the target device and reduces the area with respect to the direct implementation of the radix-4 butterfly. Both methods reduce the area required storing the coefficients. The first one uses the symmetries of coefficients for reducing the number of functions to store; the second one takes advantage of the dual-port capability of the embedded block-RAM.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125589941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010803
C. Tseng
In this paper, a weighted least squares method is presented to design a variable fractional delay allpass filter. First, each coefficient of the variable allpass filter is expressed as the polynomial of the fractional delay parameter. Then, by minimizing the phase approximation error, the optimal polynomial coefficients can be obtained by solving a set of linear simultaneous equations. Finally, the design examples are demonstrated to illustrate the effectiveness of the proposed approach.
{"title":"Design of variable fractional delay allpass filter using weighted least squares method","authors":"C. Tseng","doi":"10.1109/ISCAS.2002.1010803","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010803","url":null,"abstract":"In this paper, a weighted least squares method is presented to design a variable fractional delay allpass filter. First, each coefficient of the variable allpass filter is expressed as the polynomial of the fractional delay parameter. Then, by minimizing the phase approximation error, the optimal polynomial coefficients can be obtained by solving a set of linear simultaneous equations. Finally, the design examples are demonstrated to illustrate the effectiveness of the proposed approach.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"382 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114894213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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