Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0291
Chae Soo Kim, Bohyeon Jeon, Chiheon Byeon, Seungchul Yew, Dong In Lee, SeGuen Park, Hyodong Ban
We propose an unbiased electrical fault isolation methodology for locating gate oxide breakdown failures in MOSFETs. The test vehicle involves a sub-15nm technology DRAM device which failed due to time-dependent dielectric breakdown (TDDB). This methodology introduces an implementation of Optical Beam Induced Resistance Change with no applied external bias (zero input voltage). From OBIRCH analysis, a change in current was achieved near failure site. This principle was explained based on Seebeck effect and equivalent circuit modeling of the MOSFET drain within Seebeck generator. A physical cross section using the Focused Ion Beam (FIB) revealed a gate oxide breakdown along the location of the OBIRCH spot, illustrating the benefit of an unbiased fault isolation to preserve the failure mechanism. This study proves that gate oxide breakdown site can still be located even with no external voltage applied, preserving the device condition of nanoscale DRAM, and eliminating the chances of altering the failure mechanism as a result of the applied external voltage stress.
{"title":"Voltage Free Failure Analysis of Sub-15nm DRAM Gate Insulator Breakdown based on Thermal Laser Stimulation","authors":"Chae Soo Kim, Bohyeon Jeon, Chiheon Byeon, Seungchul Yew, Dong In Lee, SeGuen Park, Hyodong Ban","doi":"10.31399/asm.cp.istfa2023p0291","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0291","url":null,"abstract":"We propose an unbiased electrical fault isolation methodology for locating gate oxide breakdown failures in MOSFETs. The test vehicle involves a sub-15nm technology DRAM device which failed due to time-dependent dielectric breakdown (TDDB). This methodology introduces an implementation of Optical Beam Induced Resistance Change with no applied external bias (zero input voltage). From OBIRCH analysis, a change in current was achieved near failure site. This principle was explained based on Seebeck effect and equivalent circuit modeling of the MOSFET drain within Seebeck generator. A physical cross section using the Focused Ion Beam (FIB) revealed a gate oxide breakdown along the location of the OBIRCH spot, illustrating the benefit of an unbiased fault isolation to preserve the failure mechanism. This study proves that gate oxide breakdown site can still be located even with no external voltage applied, preserving the device condition of nanoscale DRAM, and eliminating the chances of altering the failure mechanism as a result of the applied external voltage stress.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"100 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0205
Kees Schot, Aya Fukami
Abstract This paper presents an empirical investigation into the application of backside thinning techniques, while preserving the packaging integrity and mounting of the target system-on-a- chip (SoC) on a printed circuitboard (PCB) within a smartphone. Such thinning procedures are often indispensable in the domain of digital forensics, as they facilitate subsequent modifications to the SoC for in-depth analysis. Crucially, these modifications must be executed without compromising the core functionality of the target smartphone. By employing reactive ion etching, we effectively achieved comprehensive thinning of bulk side of a SoC with more than 100 mm2 surface area to a sub-10μm thickness.
{"title":"In-Situ Global Ultra Thinning of Live Chip Backside for Digital Forensic and Failure Analysis","authors":"Kees Schot, Aya Fukami","doi":"10.31399/asm.cp.istfa2023p0205","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0205","url":null,"abstract":"Abstract This paper presents an empirical investigation into the application of backside thinning techniques, while preserving the packaging integrity and mounting of the target system-on-a- chip (SoC) on a printed circuitboard (PCB) within a smartphone. Such thinning procedures are often indispensable in the domain of digital forensics, as they facilitate subsequent modifications to the SoC for in-depth analysis. Crucially, these modifications must be executed without compromising the core functionality of the target smartphone. By employing reactive ion etching, we effectively achieved comprehensive thinning of bulk side of a SoC with more than 100 mm2 surface area to a sub-10μm thickness.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"100 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0246
J.S. Tsai, C.H. Yen, D.Y. Tzou, K.T. Ho
Abstract As the semiconductor process node enters into advanced process era, it is more challenging to extract electrical behavior of devices and circuits by nanoprobing systems. Not only probing is getting difficult at smaller contact or via, but also the deprocess tricks would have large influence on probing conditions, which could cause incorrect electrical performance and hard to explain the reasons. This research develops the technique of sample preparation to extract correct transfer curve of inverter cell in FinFET process.
{"title":"Inverter Characterization in Advanced Process by Nanoprobing","authors":"J.S. Tsai, C.H. Yen, D.Y. Tzou, K.T. Ho","doi":"10.31399/asm.cp.istfa2023p0246","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0246","url":null,"abstract":"Abstract As the semiconductor process node enters into advanced process era, it is more challenging to extract electrical behavior of devices and circuits by nanoprobing systems. Not only probing is getting difficult at smaller contact or via, but also the deprocess tricks would have large influence on probing conditions, which could cause incorrect electrical performance and hard to explain the reasons. This research develops the technique of sample preparation to extract correct transfer curve of inverter cell in FinFET process.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"100 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0265
Norbert Herfurth, Awwal A. Adesunkanmi, Gerfried Zwicker, Christian Boit
Abstract When aiming for extreme thinning of the bulk silicon down to the shallow trench isolation (STI) level, endpoint determination is a challenging task. Here, we present a novel approach providing reliable access to the STI level of single dies. Therefore, we transfer the wafer-based CMP process to be applicable to single dies on a table-top machine. In a first step, the developed process is applied to the whole IC backside simultaneously. Using a highly selective slurry with a material removal ratio from Si to SiO of more than 500:1 ensures that the STI level remains intact. Two types of samples have been prepared for experiments performed for this paper. A 115mm x 80mm flip-chip bonded device with a bulk silicon thickness of 500μm has been prepared to STI level within less than 4 hours.
{"title":"Reliable Backside IC Preparation Down to STI Level Using Chemical Mechanical Polishing (CMP) with Highly Selective Slurry","authors":"Norbert Herfurth, Awwal A. Adesunkanmi, Gerfried Zwicker, Christian Boit","doi":"10.31399/asm.cp.istfa2023p0265","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0265","url":null,"abstract":"Abstract When aiming for extreme thinning of the bulk silicon down to the shallow trench isolation (STI) level, endpoint determination is a challenging task. Here, we present a novel approach providing reliable access to the STI level of single dies. Therefore, we transfer the wafer-based CMP process to be applicable to single dies on a table-top machine. In a first step, the developed process is applied to the whole IC backside simultaneously. Using a highly selective slurry with a material removal ratio from Si to SiO of more than 500:1 ensures that the STI level remains intact. Two types of samples have been prepared for experiments performed for this paper. A 115mm x 80mm flip-chip bonded device with a bulk silicon thickness of 500μm has been prepared to STI level within less than 4 hours.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0209
Kuan-Jui Tu, Frank Su, Wen-Fei Hsieh, Vincent Chen, Henry Lin, Y.S. Lou
Abstract Sulfur corrodes silver metal in a continuous reaction. This corrosion is also found in semiconductor industry processes for the application of silver into Backside Grinding & Backside Metal (BGBM). In this paper two experiments were conducted for the sulfide corrosion behavior in a Circuit Probing (CP) clean room environment. They were Mixed Flowing Gas (MFG) and clean room environment exposure test. The MFG test of this research was conducted in a testing chamber with temperature, relative humidity, and concentration of H2S were carefully controlled and monitored. The MFG test conditions included the test temperature of 25°C, relative humidity of 75 %, and H2S gas concentration of 10 ppb. And the MFG tests lasted for over 72 hours. The X-ray photoelectron spectroscopy (XPS) was used to analyze the elements composition and Ag2S film thickness of the MFG test samples. The second test of this research was the direct exposure experiment. The silicon samples deposited with appropriate silver layer thickness were exposed in CP fab clean room environment with H2S concentration well monitored. The XPS analysis results of the corresponding exposure test samples indicated that the Ag2S contamination would continue to develop and wouldn't saturate. This would be indicative for the management of Ag2S contamination control. The results of MFG and Exposure test were help for Ardentec to setup Ag2S corrosion methodology. All the managements were applied into daily operation of the BGBM semiconductor products.
{"title":"The Sulfide Contamination Management in Circuit Probing FAB Clean Room Environment","authors":"Kuan-Jui Tu, Frank Su, Wen-Fei Hsieh, Vincent Chen, Henry Lin, Y.S. Lou","doi":"10.31399/asm.cp.istfa2023p0209","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0209","url":null,"abstract":"Abstract Sulfur corrodes silver metal in a continuous reaction. This corrosion is also found in semiconductor industry processes for the application of silver into Backside Grinding & Backside Metal (BGBM). In this paper two experiments were conducted for the sulfide corrosion behavior in a Circuit Probing (CP) clean room environment. They were Mixed Flowing Gas (MFG) and clean room environment exposure test. The MFG test of this research was conducted in a testing chamber with temperature, relative humidity, and concentration of H2S were carefully controlled and monitored. The MFG test conditions included the test temperature of 25°C, relative humidity of 75 %, and H2S gas concentration of 10 ppb. And the MFG tests lasted for over 72 hours. The X-ray photoelectron spectroscopy (XPS) was used to analyze the elements composition and Ag2S film thickness of the MFG test samples. The second test of this research was the direct exposure experiment. The silicon samples deposited with appropriate silver layer thickness were exposed in CP fab clean room environment with H2S concentration well monitored. The XPS analysis results of the corresponding exposure test samples indicated that the Ag2S contamination would continue to develop and wouldn't saturate. This would be indicative for the management of Ag2S contamination control. The results of MFG and Exposure test were help for Ardentec to setup Ag2S corrosion methodology. All the managements were applied into daily operation of the BGBM semiconductor products.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 26","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023tpk1
Sam Subramanian, Khiem Ly, Jacob Levenson, Tony Chrastecky
Abstract Presentation slides for the ISTFA 2023 Tutorial session “TEM Techniques for Semiconductor Failure Analysis.”
ISTFA 2023教程“半导体失效分析的透射电镜技术”的演示幻灯片。
{"title":"TEM Techniques for Semiconductor Failure Analysis","authors":"Sam Subramanian, Khiem Ly, Jacob Levenson, Tony Chrastecky","doi":"10.31399/asm.cp.istfa2023tpk1","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023tpk1","url":null,"abstract":"Abstract Presentation slides for the ISTFA 2023 Tutorial session “TEM Techniques for Semiconductor Failure Analysis.”","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"101 17","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136352526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0384
William A Hubbard
Abstract The operation of modern semiconductor components often relies on nanoscale electronic features emerging from complicated device architectures with finely tuned composition. While the physical structure of these devices may be straightforward to image, the resulting electronic characteristics are invisible to most high-resolution imaging techniques. Here we present electron beam-induced (EBIC) imaging in the scanning transmission electron microscope (STEM) as a high-resolution imaging technique with electronic-based contrast for characterizing complex semiconductor devices. Here, as an example case, we discuss the preparation and imaging of a STEM EBIC-compatible cross section extracted from a commercial AlGaAs high electron-mobility transistor (HEMT). The device exhibits low surface leakage, as measured via electrical testing and STEM EBIC conductivity contrast. The EBIC signal in the active layer of the device is mostly confined to the InGaAs channel, indicating that the electronic structure is largely preserved following sample preparation.
{"title":"Mapping Conductivity and Electric Field in an AlGaAs HEMT with STEM EBIC","authors":"William A Hubbard","doi":"10.31399/asm.cp.istfa2023p0384","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0384","url":null,"abstract":"Abstract The operation of modern semiconductor components often relies on nanoscale electronic features emerging from complicated device architectures with finely tuned composition. While the physical structure of these devices may be straightforward to image, the resulting electronic characteristics are invisible to most high-resolution imaging techniques. Here we present electron beam-induced (EBIC) imaging in the scanning transmission electron microscope (STEM) as a high-resolution imaging technique with electronic-based contrast for characterizing complex semiconductor devices. Here, as an example case, we discuss the preparation and imaging of a STEM EBIC-compatible cross section extracted from a commercial AlGaAs high electron-mobility transistor (HEMT). The device exhibits low surface leakage, as measured via electrical testing and STEM EBIC conductivity contrast. The EBIC signal in the active layer of the device is mostly confined to the InGaAs channel, indicating that the electronic structure is largely preserved following sample preparation.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"97 22","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0105
Yuyan Wang, Albert Gleason, James Fox, Usha Bhimavarapu, Juan Ortiz, Huan Dang
Abstract Static random-access memory (SRAM) is a type of device that requires the highest reliability demands for integration density and process variations. In this study, we focus on single bit cell SRAM failures. These failures can be categorized as Hard bit cell failure, where bit cells fail the read or write operation under both higher and lower supply voltages, and Soft Bit cell failure, where failures occur at either higher or lower voltage. The analysis on SRAM Soft failure is further divided as VBOX High and VBOX Low failure, which depends on the failure mode supply voltage. With transistor dimensions continuously shrinking, the analysis of SRAM errors imposes tremendous challenges due to their small footprint. In this paper, a thorough failure analysis procedure is described for solving an SRAM yield loss issue. Different analysis techniques were applied and compared to narrow down the failure to the final root cause, including nanoprobing, Focus Ion Beam (FIB) cross-section, Scanning Spreading Resistance Microscopy (SSRM), Transmission Electron Microscopy (TEM), Electron Energy Loss Spectroscopy (EELS), Scanning Capacitance Microscopy (SCM), and stain etch.
{"title":"Single Bit SRAM Failure Case Study","authors":"Yuyan Wang, Albert Gleason, James Fox, Usha Bhimavarapu, Juan Ortiz, Huan Dang","doi":"10.31399/asm.cp.istfa2023p0105","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0105","url":null,"abstract":"Abstract Static random-access memory (SRAM) is a type of device that requires the highest reliability demands for integration density and process variations. In this study, we focus on single bit cell SRAM failures. These failures can be categorized as Hard bit cell failure, where bit cells fail the read or write operation under both higher and lower supply voltages, and Soft Bit cell failure, where failures occur at either higher or lower voltage. The analysis on SRAM Soft failure is further divided as VBOX High and VBOX Low failure, which depends on the failure mode supply voltage. With transistor dimensions continuously shrinking, the analysis of SRAM errors imposes tremendous challenges due to their small footprint. In this paper, a thorough failure analysis procedure is described for solving an SRAM yield loss issue. Different analysis techniques were applied and compared to narrow down the failure to the final root cause, including nanoprobing, Focus Ion Beam (FIB) cross-section, Scanning Spreading Resistance Microscopy (SSRM), Transmission Electron Microscopy (TEM), Electron Energy Loss Spectroscopy (EELS), Scanning Capacitance Microscopy (SCM), and stain etch.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"97 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0101
Yong Guo, Brian MacDonald, Yanan Guo, Nathan McEwen, Juheon Kim, Christopher Penley
Abstract The challenges keep rising for fault isolation and failure analysis (FIFA) for the advanced semiconductor devices fabricated via integrated processes. Perceiving that defects randomly occurred during IC manufacturing contribute primarily to the device failures in comparison to those caused by harsh service environmental, we focus our efforts on fixing the defect issues in the processes, expecting a significant portion of the device failures may be prevented. A case study here demonstrates the procedure for fixing an inline defect issue via improving tool maintenance for the chemical-mechanical polishing (CMP) process. Through a correlative physical and chemical analysis down to atomic scale, a 10 nm diamond particle and a 10 nm metallic debris damaging one of the metal interconnect layers were defined. The analysis led to pinpointing the issue to a metal CMP process. By examining the process operation and the tool configuration, we located the diamond-missing sites on a pad-conditioning disk made with embedded diamond grits in a metal matrix. Preventive countermeasure were implemented to avoid the same defect recurring via resetting the disk life and maintenance.
{"title":"Inline Defect Solution to Mitigate EOL Device Failure","authors":"Yong Guo, Brian MacDonald, Yanan Guo, Nathan McEwen, Juheon Kim, Christopher Penley","doi":"10.31399/asm.cp.istfa2023p0101","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0101","url":null,"abstract":"Abstract The challenges keep rising for fault isolation and failure analysis (FIFA) for the advanced semiconductor devices fabricated via integrated processes. Perceiving that defects randomly occurred during IC manufacturing contribute primarily to the device failures in comparison to those caused by harsh service environmental, we focus our efforts on fixing the defect issues in the processes, expecting a significant portion of the device failures may be prevented. A case study here demonstrates the procedure for fixing an inline defect issue via improving tool maintenance for the chemical-mechanical polishing (CMP) process. Through a correlative physical and chemical analysis down to atomic scale, a 10 nm diamond particle and a 10 nm metallic debris damaging one of the metal interconnect layers were defined. The analysis led to pinpointing the issue to a metal CMP process. By examining the process operation and the tool configuration, we located the diamond-missing sites on a pad-conditioning disk made with embedded diamond grits in a metal matrix. Preventive countermeasure were implemented to avoid the same defect recurring via resetting the disk life and maintenance.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"97 19","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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