Abstract 3D X-ray microscopy (XRM) is an effective highresolution and non-destructive tool for semiconductor package level failure analysis. One limitation with XRM is the ability to achieve high-resolution 3D images over large fields of view (FOVs) within acceptable scan times. As modern semiconductor packages become more complex, there are increasing demands for 3D X-ray instruments to image encapsulated structures and failures with high productivity and efficiency. With the challenge to precisely localize fault regions, it may require high-resolution imaging with a FOV of tens of millimeters. This may take over hundreds of hours of scans if many high-resolution but small-volume scans are performed and followed with the conventional 3D registration and stitches. In this work, a novel deep learning reconstruction method and workflow to address the issue of achieving highresolution imaging over a large FOV is reported. The AI powered technique and workflow can be used to restore the resolution over the large FOV scan with only a high-resolution and a large FOV scan. Additionally, the 3D registration and stitch workflow are automated to achieve the large FOV images with a recovered resolution comparable to the actual high-resolution scan.
{"title":"An Artificial Intelligence Powered Resolution Recovery Technique and Workflow to Accelerate Package Level Failure Analysis with 3D X-ray Microscopy","authors":"Syahirah Mohammad-Zulkifli, Bernice Zee, Qiu Wen, Maverique Ong, Yanjing Yang, Andriy Andreyev, Masako Terada, Allen Gu","doi":"10.31399/asm.cp.istfa2023p0443","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0443","url":null,"abstract":"Abstract 3D X-ray microscopy (XRM) is an effective highresolution and non-destructive tool for semiconductor package level failure analysis. One limitation with XRM is the ability to achieve high-resolution 3D images over large fields of view (FOVs) within acceptable scan times. As modern semiconductor packages become more complex, there are increasing demands for 3D X-ray instruments to image encapsulated structures and failures with high productivity and efficiency. With the challenge to precisely localize fault regions, it may require high-resolution imaging with a FOV of tens of millimeters. This may take over hundreds of hours of scans if many high-resolution but small-volume scans are performed and followed with the conventional 3D registration and stitches. In this work, a novel deep learning reconstruction method and workflow to address the issue of achieving highresolution imaging over a large FOV is reported. The AI powered technique and workflow can be used to restore the resolution over the large FOV scan with only a high-resolution and a large FOV scan. Additionally, the 3D registration and stitch workflow are automated to achieve the large FOV images with a recovered resolution comparable to the actual high-resolution scan.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"97 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0309
C.S. Bonifacio, M.L. Ray, P.E. Fischione, Y. Yu, M. Skowronski
Abstract Advanced memory technologies are in demand with phase change memory (PCM) devices as a forefront candidate. For successful characterization by transmission electron microscopy (TEM) for failure analysis and device development, an accurate and controllable thinning of TEM specimens is critical. In this work, TEM specimens from a GeTe-based PCM device at a partial SET state were prepared using a Xe plasma focused ion beam (pFIB) and polished to electron transparency using Ar ion beam milling. We will highlight the differences between Ga focused ion beam (FIB) and Xe pFIB TEM specimen preparation, the benefits of post-pFIB Ar ion beam milling, and show TEM results of the effects of partial SET programming of the GeTe PCM device.
{"title":"Precise Final Thinning by Concentrated Ar Ion Beam Milling of Plan View TEM Specimens from Phase Change Memory Device Prepared in Xe Plasma FIB","authors":"C.S. Bonifacio, M.L. Ray, P.E. Fischione, Y. Yu, M. Skowronski","doi":"10.31399/asm.cp.istfa2023p0309","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0309","url":null,"abstract":"Abstract Advanced memory technologies are in demand with phase change memory (PCM) devices as a forefront candidate. For successful characterization by transmission electron microscopy (TEM) for failure analysis and device development, an accurate and controllable thinning of TEM specimens is critical. In this work, TEM specimens from a GeTe-based PCM device at a partial SET state were prepared using a Xe plasma focused ion beam (pFIB) and polished to electron transparency using Ar ion beam milling. We will highlight the differences between Ga focused ion beam (FIB) and Xe pFIB TEM specimen preparation, the benefits of post-pFIB Ar ion beam milling, and show TEM results of the effects of partial SET programming of the GeTe PCM device.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"98 24","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0427
Grigore Moldovan, William Courbat, Jörg Jatzkowski
Abstract Key improvements to data acquisition, visualization and analysis are presented for Electrical Failure Analysis (EFA). Multi-channel image acquisition is introduced, where every nanoprobe is used for simultaneous imaging, in combination with color coding either by probe or by current. This new approach improves visualization of new device technologies with increasing three-dimensional complexity, in particular for overlapping structures and fields. Further, this new multichannel method opens opportunities for image mixing to improve data quality and signal interpretation.
{"title":"Advances in EFA with Color Coded Multi-Channel Nanoprobing","authors":"Grigore Moldovan, William Courbat, Jörg Jatzkowski","doi":"10.31399/asm.cp.istfa2023p0427","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0427","url":null,"abstract":"Abstract Key improvements to data acquisition, visualization and analysis are presented for Electrical Failure Analysis (EFA). Multi-channel image acquisition is introduced, where every nanoprobe is used for simultaneous imaging, in combination with color coding either by probe or by current. This new approach improves visualization of new device technologies with increasing three-dimensional complexity, in particular for overlapping structures and fields. Further, this new multichannel method opens opportunities for image mixing to improve data quality and signal interpretation.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"98 16","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0078
Arnulfo Evangelista, Janella Alfelor-Igtiben, John David Mangali, Khristopherson Cajucom
Abstract Analog Devices Inc. (ADI)’s Radar Receive Path Analog Front End Amplifier (AFE) with a 0.18um 6-metal Fab Process has failures related to Power-Down and Scan test parameters which were endorsed for Failure Analysis. Fault localization is quite challenging because it involves 6 metal layers. This has been resolved with the availability of Synopsis Avalon software with capability to convert the complete Cadence schematics and layout that is usable for Failure Analysis, through cross-mapping with the fault localized area-of-interest (AOI) on the actual reject part with the die schematics and layout, and identifying the failing component and circuit block. This leads to the creation of the failure model related to the reported failure mode and the determination of the appropriate failure mechanism related to fabrication defects between the adjacent metallization layers and defects on between the polysilicon and substrate layer. This helps speed up the FA Cycle Time and achieve an accurate failure mechanism, which later resolves the fab defect issue with the Fab process owner.
{"title":"Avalon-Aided Mapping of Fault-Localized Area of ADI’s RADAR Receive Path Analog Front-End (AFE) Amplifier with 0.18um 6-Metal CMOS Fab Process","authors":"Arnulfo Evangelista, Janella Alfelor-Igtiben, John David Mangali, Khristopherson Cajucom","doi":"10.31399/asm.cp.istfa2023p0078","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0078","url":null,"abstract":"Abstract Analog Devices Inc. (ADI)’s Radar Receive Path Analog Front End Amplifier (AFE) with a 0.18um 6-metal Fab Process has failures related to Power-Down and Scan test parameters which were endorsed for Failure Analysis. Fault localization is quite challenging because it involves 6 metal layers. This has been resolved with the availability of Synopsis Avalon software with capability to convert the complete Cadence schematics and layout that is usable for Failure Analysis, through cross-mapping with the fault localized area-of-interest (AOI) on the actual reject part with the die schematics and layout, and identifying the failing component and circuit block. This leads to the creation of the failure model related to the reported failure mode and the determination of the appropriate failure mechanism related to fabrication defects between the adjacent metallization layers and defects on between the polysilicon and substrate layer. This helps speed up the FA Cycle Time and achieve an accurate failure mechanism, which later resolves the fab defect issue with the Fab process owner.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"98 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0339
Elham Amini, Tuba Kiyan, Lars Renkes, Thilo Krachenfels, Christian Boit, Jean-Pierre Seifert, Jörg Jatzkowski, Frank Altmann, Sebastian Brand, Shahin Tajik
Abstract Contactless probing methods through the chip backside have been demonstrated to be powerful attack techniques in the field of electronic security. However, these attacks typically require the adversary to run the circuit under specific conditions, such as enforcing the switching of gates or registers with certain frequencies or repeating measurements over multiple executions to achieve an acceptable signal-to-noise ratio (SNR). Fulfilling such requirements may not always be feasible due to challenges such as low-frequency switching or inaccessibility of the control signals. In this work, we assess these requirements for contactless electron- and photon-based probing attacks by performing extensive experiments. Our findings demonstrate that E-beam probing, in particular, has the potential to outperform optical methods in scenarios involving static or low-frequency circuit activities.
{"title":"Electrons Vs. Photons: Assessment of Circuit’s Activity Requirements for E-Beam and Optical Probing Attacks","authors":"Elham Amini, Tuba Kiyan, Lars Renkes, Thilo Krachenfels, Christian Boit, Jean-Pierre Seifert, Jörg Jatzkowski, Frank Altmann, Sebastian Brand, Shahin Tajik","doi":"10.31399/asm.cp.istfa2023p0339","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0339","url":null,"abstract":"Abstract Contactless probing methods through the chip backside have been demonstrated to be powerful attack techniques in the field of electronic security. However, these attacks typically require the adversary to run the circuit under specific conditions, such as enforcing the switching of gates or registers with certain frequencies or repeating measurements over multiple executions to achieve an acceptable signal-to-noise ratio (SNR). Fulfilling such requirements may not always be feasible due to challenges such as low-frequency switching or inaccessibility of the control signals. In this work, we assess these requirements for contactless electron- and photon-based probing attacks by performing extensive experiments. Our findings demonstrate that E-beam probing, in particular, has the potential to outperform optical methods in scenarios involving static or low-frequency circuit activities.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"98 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0177
Tommaso Melis
Abstract The localization of defects that cause dynamic electrical behavior is a constant challenge for failure analysts. Such types of failures are often present in analog circuits, and standard fault isolation techniques are constrained and not always successful. In this paper, we demonstrate a method to exploit industrial fault simulators in conjunction with standard analysis methods to solve analyses in analog circuits. In addition, we will show methods to adapt fault simulation to these dynamic electrical failure modes. Successful fault isolation results from real-world failure analyses of oscillators, which are typical inside analog and mixed-signal circuits.
{"title":"Fault Simulation for Dynamic Failures in Analog and Mixed Signal Circuits","authors":"Tommaso Melis","doi":"10.31399/asm.cp.istfa2023p0177","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0177","url":null,"abstract":"Abstract The localization of defects that cause dynamic electrical behavior is a constant challenge for failure analysts. Such types of failures are often present in analog circuits, and standard fault isolation techniques are constrained and not always successful. In this paper, we demonstrate a method to exploit industrial fault simulators in conjunction with standard analysis methods to solve analyses in analog circuits. In addition, we will show methods to adapt fault simulation to these dynamic electrical failure modes. Successful fault isolation results from real-world failure analyses of oscillators, which are typical inside analog and mixed-signal circuits.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0117
Acer Jay Castillo, Mark Anthony Acedillo
Abstract Completion of failure analysis (FA) cases require a lot of expensive equipment and tools. Equipment Management System (EMS) is a must to safeguard the equipment from being down/damaged due to uncertified/untrained and high number of users and to avoid high repair cost of the FA laboratory equipment. The purpose of this paper is to present the RFID-based equipment management system for failure analysis laboratory equipment which has the capability to limit the equipment usage to authorized and certified users, locks and unlocks the equipment, and controls the real-time status of the equipment.
{"title":"Implementation of RFID-based Equipment Management System for Failure Analysis Laboratory Equipment","authors":"Acer Jay Castillo, Mark Anthony Acedillo","doi":"10.31399/asm.cp.istfa2023p0117","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0117","url":null,"abstract":"Abstract Completion of failure analysis (FA) cases require a lot of expensive equipment and tools. Equipment Management System (EMS) is a must to safeguard the equipment from being down/damaged due to uncertified/untrained and high number of users and to avoid high repair cost of the FA laboratory equipment. The purpose of this paper is to present the RFID-based equipment management system for failure analysis laboratory equipment which has the capability to limit the equipment usage to authorized and certified users, locks and unlocks the equipment, and controls the real-time status of the equipment.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0067
R. Estores, E. Barbian, L. Boukhanfra, K. Villareal, A. Sabate
Abstract This paper discusses a comprehensive failure analysis approach to digital failures. High-Resolution Targeted Patterns (HRTP) are highlighted along with their advantages in failure analysis by aiding in Automated Test Pattern Generation (ATPG) diagnoses resolution improvement, increasing the chance of detecting fault not detected by patterns implemented on Automated Test Equipment (ATE), determine a potential test screen, provide stimulus for further fault localization, and increase the analysis success rate. This comprehensive approach and the use of HRTP have proven very helpful in the analysis of internal requests and customer returns. Three cases will be discussed in this paper to highlight these advantages.
{"title":"A Comprehensive Failure Analysis Approach Utilizing High-Resolution Targeted Patterns (HRTP) for ATPG Diagnosis Resolution Improvement, Test Coverage Resolution, and Further Fault Localization","authors":"R. Estores, E. Barbian, L. Boukhanfra, K. Villareal, A. Sabate","doi":"10.31399/asm.cp.istfa2023p0067","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0067","url":null,"abstract":"Abstract This paper discusses a comprehensive failure analysis approach to digital failures. High-Resolution Targeted Patterns (HRTP) are highlighted along with their advantages in failure analysis by aiding in Automated Test Pattern Generation (ATPG) diagnoses resolution improvement, increasing the chance of detecting fault not detected by patterns implemented on Automated Test Equipment (ATE), determine a potential test screen, provide stimulus for further fault localization, and increase the analysis success rate. This comprehensive approach and the use of HRTP have proven very helpful in the analysis of internal requests and customer returns. Three cases will be discussed in this paper to highlight these advantages.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-12DOI: 10.31399/asm.cp.istfa2023p0034
Mack Marshall, Edward Huang, Arun Rajaraman, David Grosjean
Abstract Lead-free solder joints tend to be more susceptible to brittle fracture, and thus susceptible to drop-damage. Drop testing of handheld ultrasound devices revealed broken solder joints on a large inductor component. Analysis of the cracks showed a dual intermetallic compound (IMC) layer of Ni3Sn4 (closest to the nickel) and (Ni,Cu)6Sn5, with the crack occurring in between the two layers. The inductor had a tinned nickel lead finish; the solder was SAC305 (a common lead-free solder comprising Sn, Ag, and Cu); and the printed circuit board (PCB) had a standard copper finish. The failure occurred very soon after manufacture and had not been enhanced by temperature cycling or aging, but it was not a time-zero failure: mechanical shocks from drops were required to propagate the crack through the joint fully. Strain measurements did not find any large strains after reflow and assembly, and no other components on the board showed cracking. There was no cracking observed at the PCB (Cu) side of the solder joint. The solution ultimately was to redesign the board, replacing the large single component with several smaller ones.
{"title":"Evaluation of Inductor for Solderability and Drop Damage Susceptibility","authors":"Mack Marshall, Edward Huang, Arun Rajaraman, David Grosjean","doi":"10.31399/asm.cp.istfa2023p0034","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2023p0034","url":null,"abstract":"Abstract Lead-free solder joints tend to be more susceptible to brittle fracture, and thus susceptible to drop-damage. Drop testing of handheld ultrasound devices revealed broken solder joints on a large inductor component. Analysis of the cracks showed a dual intermetallic compound (IMC) layer of Ni3Sn4 (closest to the nickel) and (Ni,Cu)6Sn5, with the crack occurring in between the two layers. The inductor had a tinned nickel lead finish; the solder was SAC305 (a common lead-free solder comprising Sn, Ag, and Cu); and the printed circuit board (PCB) had a standard copper finish. The failure occurred very soon after manufacture and had not been enhanced by temperature cycling or aging, but it was not a time-zero failure: mechanical shocks from drops were required to propagate the crack through the joint fully. Strain measurements did not find any large strains after reflow and assembly, and no other components on the board showed cracking. There was no cracking observed at the PCB (Cu) side of the solder joint. The solution ultimately was to redesign the board, replacing the large single component with several smaller ones.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136353501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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