Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207943
B. Korte, H. J. PrOmel, A. Steger
The authors report on a design system for the physical layout of ASIC's with macrocells, which has been developed during the last three years in the framework of a research contact with IBM Germany and used successfully in practice. The main idea is to apply a hierarchical placement procedure together with global routing and timing analysis. This technique enables one to guarantee at each step of the placement the routability of the chip as well as the desired timing. The authors sketch some ideas of the design system roughly and report on some practical experience.<>
{"title":"A design-system for ASIC's with macrocells","authors":"B. Korte, H. J. PrOmel, A. Steger","doi":"10.1109/EASIC.1990.207943","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207943","url":null,"abstract":"The authors report on a design system for the physical layout of ASIC's with macrocells, which has been developed during the last three years in the framework of a research contact with IBM Germany and used successfully in practice. The main idea is to apply a hierarchical placement procedure together with global routing and timing analysis. This technique enables one to guarantee at each step of the placement the routability of the chip as well as the desired timing. The authors sketch some ideas of the design system roughly and report on some practical experience.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123956204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207958
P. Valdenaire, C. Gauthron
Typical examples of analog functions and their testing are described. It is shown, that these tests can be performed on digital testers. A test strategy for mixed ASICs is proposed, as an extension of techniques applicable to digital ASICs.<>
{"title":"A test strategy for mixed analog/digital ASICS","authors":"P. Valdenaire, C. Gauthron","doi":"10.1109/EASIC.1990.207958","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207958","url":null,"abstract":"Typical examples of analog functions and their testing are described. It is shown, that these tests can be performed on digital testers. A test strategy for mixed ASICs is proposed, as an extension of techniques applicable to digital ASICs.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125294452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207922
C. Caillon, P. Warembourg, J. Quervel
An innovative mixed A/D arrays family, developed on a high speed, high density bipolar process, is described with emphasis on associated macro-cells library and CAD tool. Development effort has been focused on design tools and methodology in order to ensure a great flexibility and safety in design, key features of the semicustom concept. Components and functions kit-parts availability for bread-boarding, extensive library of digital and analog cells allow the designer to easily and rapidly convert his discrete components based system to silicon. An innovative CAD tool, running on a very low-cost hardware platform (IBM-PC) ensures short design cycle and safety in the design since all design steps are managed by a unique system, from schematic to layout.<>
{"title":"Bipolar mixed arrays based on a linear and digital macro-cells concept","authors":"C. Caillon, P. Warembourg, J. Quervel","doi":"10.1109/EASIC.1990.207922","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207922","url":null,"abstract":"An innovative mixed A/D arrays family, developed on a high speed, high density bipolar process, is described with emphasis on associated macro-cells library and CAD tool. Development effort has been focused on design tools and methodology in order to ensure a great flexibility and safety in design, key features of the semicustom concept. Components and functions kit-parts availability for bread-boarding, extensive library of digital and analog cells allow the designer to easily and rapidly convert his discrete components based system to silicon. An innovative CAD tool, running on a very low-cost hardware platform (IBM-PC) ensures short design cycle and safety in the design since all design steps are managed by a unique system, from schematic to layout.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121772255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207973
A. Maeder, R.H. Rauscher
A chip and a corresponding PCB solution performing the special task of thinning is presented. Thinning, a common task in the field of image processing, preserves the overall structure of the image while making lines thinner and pixel spots smaller. While thinning (skeleting) is only available on special image processing architectures in realtime or has been implemented in 'slow' software, both solutions presented solutions make thinning (at realtime conditions) available for general purpose environments. This paper describes both realisations, based on the same architectural concept, and shows how to integrate into an image processing pipeline. This proceeding enables an objective comparison. At last the results, the chip-layout, and new ideas concerning testability aspects are presented.<>
{"title":"Comparison between a chip for realtime skeleting of images and its corresponding discrete realisation-a case study","authors":"A. Maeder, R.H. Rauscher","doi":"10.1109/EASIC.1990.207973","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207973","url":null,"abstract":"A chip and a corresponding PCB solution performing the special task of thinning is presented. Thinning, a common task in the field of image processing, preserves the overall structure of the image while making lines thinner and pixel spots smaller. While thinning (skeleting) is only available on special image processing architectures in realtime or has been implemented in 'slow' software, both solutions presented solutions make thinning (at realtime conditions) available for general purpose environments. This paper describes both realisations, based on the same architectural concept, and shows how to integrate into an image processing pipeline. This proceeding enables an objective comparison. At last the results, the chip-layout, and new ideas concerning testability aspects are presented.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116529301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207923
J. Trontelj, L. Trontelj, A. Pletersek, A. Vodopivec, D. Strle, G. Shenton
The most critical part of design automation of mixed analog digital circuits is layout related dependency of electrical characteristic of precision and sensitive analog parts of the ASIC. Circuit compilation principles and layout compilation principles are discussed. Design methodology, previously introduced, is refined to accommodate a wide variety of designs. A few design examples illustrating the capabilities of an expert design CAD tool based on the described principles are shown.<>
{"title":"Improved techniques for the synthesis and layout of mixed analog digital ASICs","authors":"J. Trontelj, L. Trontelj, A. Pletersek, A. Vodopivec, D. Strle, G. Shenton","doi":"10.1109/EASIC.1990.207923","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207923","url":null,"abstract":"The most critical part of design automation of mixed analog digital circuits is layout related dependency of electrical characteristic of precision and sensitive analog parts of the ASIC. Circuit compilation principles and layout compilation principles are discussed. Design methodology, previously introduced, is refined to accommodate a wide variety of designs. A few design examples illustrating the capabilities of an expert design CAD tool based on the described principles are shown.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130775922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207992
T. Gaillard, V. Karanov
This paper describes the design of the Kiwi processor, which hardwires a new efficient unification algorithm for PROLOG resolution, using high-performance silicon compilers of VLSI Technology, Inc. Moreover, a new method for high-level simulation has been performed and appears to be best suited for complex design reliability check.<>
{"title":"Silicon compilation of algorithm structures","authors":"T. Gaillard, V. Karanov","doi":"10.1109/EASIC.1990.207992","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207992","url":null,"abstract":"This paper describes the design of the Kiwi processor, which hardwires a new efficient unification algorithm for PROLOG resolution, using high-performance silicon compilers of VLSI Technology, Inc. Moreover, a new method for high-level simulation has been performed and appears to be best suited for complex design reliability check.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133876876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207903
G. Rietsche, M. Neher
The authors describe some of the state assignment heuristics, which are applied in the finite state machine synthesis system CASTOR. They concentrate on algorithms for two-level logic implementations, while work on algorithms for multi-level logic implementations is in progress. Input to the system is a description of the FSM in form of a state table. CASTOR generates an appropriate controller consisting of pre- and postprocessing structures around a kernel FSM, which may be a PLA, a ROM or random logic. In the case of a PLA or random logical controller coding constraints are extracted for the kernel FSM. Then these coding constraints have to be satisfied by adequate state assignment algorithms in order to minimize the area of the physical implementation.<>
{"title":"CASTOR: state assignment in a finite state machine synthesis system","authors":"G. Rietsche, M. Neher","doi":"10.1109/EASIC.1990.207903","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207903","url":null,"abstract":"The authors describe some of the state assignment heuristics, which are applied in the finite state machine synthesis system CASTOR. They concentrate on algorithms for two-level logic implementations, while work on algorithms for multi-level logic implementations is in progress. Input to the system is a description of the FSM in form of a state table. CASTOR generates an appropriate controller consisting of pre- and postprocessing structures around a kernel FSM, which may be a PLA, a ROM or random logic. In the case of a PLA or random logical controller coding constraints are extracted for the kernel FSM. Then these coding constraints have to be satisfied by adequate state assignment algorithms in order to minimize the area of the physical implementation.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123421638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207952
S.G. Smith, R. Morgan, J. Payne
Although digital signal processing is emerging as a major technological applications area, one has yet to witness the flourish of integrated-circuit design automation techniques which accompanied the recent boom in the computer industry. A potential catalyst to bring this about is the nascent field of high-level synthesis, which promises to furnish conventional datapath architectures with the power of parallelism and pipelining. This paper reports progress in a high-level IC design tool intended specifically for DSP users, now more than one year in development. While parallelism and pipelining are naturally exploited, novel use is made of synthesis techniques at bit-level, which brings both advantages and disadvantages in comparison to high-level synthesis. The approach is powerful and efficient in high-throughput, fixed-function applications.<>
{"title":"Progress in DSP design automation","authors":"S.G. Smith, R. Morgan, J. Payne","doi":"10.1109/EASIC.1990.207952","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207952","url":null,"abstract":"Although digital signal processing is emerging as a major technological applications area, one has yet to witness the flourish of integrated-circuit design automation techniques which accompanied the recent boom in the computer industry. A potential catalyst to bring this about is the nascent field of high-level synthesis, which promises to furnish conventional datapath architectures with the power of parallelism and pipelining. This paper reports progress in a high-level IC design tool intended specifically for DSP users, now more than one year in development. While parallelism and pipelining are naturally exploited, novel use is made of synthesis techniques at bit-level, which brings both advantages and disadvantages in comparison to high-level synthesis. The approach is powerful and efficient in high-throughput, fixed-function applications.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124546547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207904
C. Pitot, M. Ducateau, D. Popescu, E. Lemee
For many airborne digital data processing applications, equipment suppliers have developed discrete circuit solutions based upon bit slice processors. The ASIC-based replacement of a preexisting discrete components computer was a good opportunity to introduce some architectural enhancements. The authors describe these evolutions as well as the design methodology. Two comparisons are performed using benchmarks: first, the new computer throughput versus the former's one; second, the new performance versus a standard CPU's one.<>
{"title":"Integration of a microprogrammed CPU","authors":"C. Pitot, M. Ducateau, D. Popescu, E. Lemee","doi":"10.1109/EASIC.1990.207904","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207904","url":null,"abstract":"For many airborne digital data processing applications, equipment suppliers have developed discrete circuit solutions based upon bit slice processors. The ASIC-based replacement of a preexisting discrete components computer was a good opportunity to introduce some architectural enhancements. The authors describe these evolutions as well as the design methodology. Two comparisons are performed using benchmarks: first, the new computer throughput versus the former's one; second, the new performance versus a standard CPU's one.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"104 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122451733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207956
B. Hanstein
A fast, competitive CAD-procedure requires a high degree of automatization that also includes the generation of the test program. Starting with an analog test plan written by the user and a circuit description, a test program is generated automatically for analog circuits and for the analog part of hybrid circuits. The test program is synthesized from different, proven software modules. The additional hardware, which is required for the test, is realized in the standardized hardware modules.<>
{"title":"Automatic generation of analog test programs","authors":"B. Hanstein","doi":"10.1109/EASIC.1990.207956","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207956","url":null,"abstract":"A fast, competitive CAD-procedure requires a high degree of automatization that also includes the generation of the test program. Starting with an analog test plan written by the user and a circuit description, a test program is generated automatically for analog circuits and for the analog part of hybrid circuits. The test program is synthesized from different, proven software modules. The additional hardware, which is required for the test, is realized in the standardized hardware modules.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124329623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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