Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207906
D. Ku, G. De Micheli
Presents an approach to automated synthesis of digital circuits from behavioral specifications. The system, called Hercules and Hebe, offers many advantages to the designer. First, the system supports constraint-driven synthesis where timing and resource constraints are applied to guide the synthesis decisions. Second, systematic design space exploration is possible, where the designer explores the tradeoff between area and performance to meet the design objectives. Third, logic synthesis techniques are uniformly incorporated within the synthesis framework to provide estimates to guide high-level decisions. Along with a synthesis oriented hardware description language called HardwareC, Hercules/Hebe provides an environment for the design of general synchronous digital circuits, with specific attention to the requirements of ASIC designs. The system has been applied to complex ASIC designs, including the Digital Audio I/O, MAMA, and Bi-Dimensional DCT chips.<>
{"title":"High-level synthesis and optimization strategies in Hercules and Hebe","authors":"D. Ku, G. De Micheli","doi":"10.1109/EASIC.1990.207906","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207906","url":null,"abstract":"Presents an approach to automated synthesis of digital circuits from behavioral specifications. The system, called Hercules and Hebe, offers many advantages to the designer. First, the system supports constraint-driven synthesis where timing and resource constraints are applied to guide the synthesis decisions. Second, systematic design space exploration is possible, where the designer explores the tradeoff between area and performance to meet the design objectives. Third, logic synthesis techniques are uniformly incorporated within the synthesis framework to provide estimates to guide high-level decisions. Along with a synthesis oriented hardware description language called HardwareC, Hercules/Hebe provides an environment for the design of general synchronous digital circuits, with specific attention to the requirements of ASIC designs. The system has been applied to complex ASIC designs, including the Digital Audio I/O, MAMA, and Bi-Dimensional DCT chips.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122230334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207915
D. Dzahini, F. Gaffiot, B. Boutherin, M. Le Helley
Presents a set of tools for aiding to the design of analog CMOS circuits. The procedures described can generate automatically the layout of CMOS cells. In addition to the electrical parameters of each component, transistor, resistors, capacitors, the designer can give a shape description which will be used for placement and routing. The layout is generated with respect to specified design rules. The procedures have been written in SKILL language. SKILL is a trademark of CADENCE.<>
{"title":"Layout automation of CMOS analog building blocks with CADENCE","authors":"D. Dzahini, F. Gaffiot, B. Boutherin, M. Le Helley","doi":"10.1109/EASIC.1990.207915","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207915","url":null,"abstract":"Presents a set of tools for aiding to the design of analog CMOS circuits. The procedures described can generate automatically the layout of CMOS cells. In addition to the electrical parameters of each component, transistor, resistors, capacitors, the designer can give a shape description which will be used for placement and routing. The layout is generated with respect to specified design rules. The procedures have been written in SKILL language. SKILL is a trademark of CADENCE.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114952354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207931
J. Noullet
An application-specific-integrated-circuit (ASIC) family is presented in this paper. Its purpose is to interface a computer with the outer world with low cost and high flexibility, by means of a network of serially communicating ASICs. A communication protocol specially devised to be easily implemented by a set of ASICs is described, then details about the circuit design are given.<>
{"title":"ASICs for an interface ring network","authors":"J. Noullet","doi":"10.1109/EASIC.1990.207931","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207931","url":null,"abstract":"An application-specific-integrated-circuit (ASIC) family is presented in this paper. Its purpose is to interface a computer with the outer world with low cost and high flexibility, by means of a network of serially communicating ASICs. A communication protocol specially devised to be easily implemented by a set of ASICs is described, then details about the circuit design are given.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115621327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207909
R. Cates, J. J. Farrell
Describes a hard disk controller application and the RISC-based ISA Bus coprocessor called the I/O processor (IOP) from which the hard disk application was developed. The IOP is used as a central element in ISA (Industry Standard Architecture)-based peripheral controller applications. In this specific application, it incorporates a comprehensive set of function blocks in addition to the core 32-bit RISC processor. These include an ISA address decoder, a register file compatible with the PC/AT-compatible hard disk controller, a DRAM controller capable of support 16 M bytes of 32-bit memory, an interrupt controller, a DMA controller, a 2 K-byte ROM and a 512-byte RAM. The IOP has been optimized for application requiring high data transfer rates. Burst data transfers up to 40 M bytes per second may be attained with the RISC processor running at 10 MHz. A paging and interleaving DRAM controller is utilized so that slower DRAMs with 100 nanoseconds access times can be used.<>
{"title":"An ASIC RISC-based I/O processor for computer applications","authors":"R. Cates, J. J. Farrell","doi":"10.1109/EASIC.1990.207909","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207909","url":null,"abstract":"Describes a hard disk controller application and the RISC-based ISA Bus coprocessor called the I/O processor (IOP) from which the hard disk application was developed. The IOP is used as a central element in ISA (Industry Standard Architecture)-based peripheral controller applications. In this specific application, it incorporates a comprehensive set of function blocks in addition to the core 32-bit RISC processor. These include an ISA address decoder, a register file compatible with the PC/AT-compatible hard disk controller, a DRAM controller capable of support 16 M bytes of 32-bit memory, an interrupt controller, a DMA controller, a 2 K-byte ROM and a 512-byte RAM. The IOP has been optimized for application requiring high data transfer rates. Burst data transfers up to 40 M bytes per second may be attained with the RISC processor running at 10 MHz. A paging and interleaving DRAM controller is utilized so that slower DRAMs with 100 nanoseconds access times can be used.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130303193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207978
F. Durbin, J. Haussy, G. Berthiau, P. Siarry, W.M. Zuberek
The circuit design problem consists in determining acceptable parameter values (resistors, capacitors, transistor geometries . . .) which allow the circuit to meet various user given operational criteria (DC consumption, AC bandwidth, transient rise times, etc.). This task is equivalent to a multidimensional and/or multi objective optimization problem: n-variables functions have to be minimized in an hyperrectangular domain: equality and/or inequality constraints can be eventually specified. The authors propose an efficient algorithm, based on the repeated application of simulated annealing to a certain number of p-variables sub problems, with p<>
{"title":"Integrated circuit performance optimization with simulated annealing algorithm and SPICE-PAC circuit simulator","authors":"F. Durbin, J. Haussy, G. Berthiau, P. Siarry, W.M. Zuberek","doi":"10.1109/EASIC.1990.207978","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207978","url":null,"abstract":"The circuit design problem consists in determining acceptable parameter values (resistors, capacitors, transistor geometries . . .) which allow the circuit to meet various user given operational criteria (DC consumption, AC bandwidth, transient rise times, etc.). This task is equivalent to a multidimensional and/or multi objective optimization problem: n-variables functions have to be minimized in an hyperrectangular domain: equality and/or inequality constraints can be eventually specified. The authors propose an efficient algorithm, based on the repeated application of simulated annealing to a certain number of p-variables sub problems, with p<<n. Objective functions are computed through the modular SPICE-PAC simulator, which is controlled by the optimization algorithm.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128460927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207976
B. Kaminska, F. Mheir-El-Saadi
The object of this paper is to propose an ASIC design model that incorporates two aspects: design as a decision-making process and expert-like knowledge-based design control. The authors provide a integrated solution for the following important issues: incremental propagation of design characteristics, checking for design specification violation, evaluation of the quality of a design, and choosing the most appropriate solution. This paper attempts to make a step towards the building of a theoretical framework for knowledge-based design control based on the decision theory and expert systems methodology.<>
{"title":"A framework for performance and knowledge-based control of basic designs","authors":"B. Kaminska, F. Mheir-El-Saadi","doi":"10.1109/EASIC.1990.207976","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207976","url":null,"abstract":"The object of this paper is to propose an ASIC design model that incorporates two aspects: design as a decision-making process and expert-like knowledge-based design control. The authors provide a integrated solution for the following important issues: incremental propagation of design characteristics, checking for design specification violation, evaluation of the quality of a design, and choosing the most appropriate solution. This paper attempts to make a step towards the building of a theoretical framework for knowledge-based design control based on the decision theory and expert systems methodology.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133011883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207950
V. Grimblatt-Hinzpeter, C. Kingsley
Gives an overview of the VLSI Technology ASIC synthesizer. It is a synthesis tool that is able to compile whole chips from a hardware description language specification. Synthesis tools like this will increase the productivity of chip design to such an extent that current techniques of circuit design will someday be obsolete. The authors describe in this paper the capabilities that the ASIC Synthesizer has, the development phases and some applications.<>
{"title":"Designing an ASIC with the VLSI Technology ASIC synthesizer","authors":"V. Grimblatt-Hinzpeter, C. Kingsley","doi":"10.1109/EASIC.1990.207950","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207950","url":null,"abstract":"Gives an overview of the VLSI Technology ASIC synthesizer. It is a synthesis tool that is able to compile whole chips from a hardware description language specification. Synthesis tools like this will increase the productivity of chip design to such an extent that current techniques of circuit design will someday be obsolete. The authors describe in this paper the capabilities that the ASIC Synthesizer has, the development phases and some applications.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127871570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207932
A. Hohl
As it is well known, the development of the hardware description language (HDL) VHDL was started in 1980 sponsored by the US Department of Defense. Today VHDL has become an important topic in research development, and CAE fields in the US as well as in Europe. Because of this development, user groups were established during the last years, namely the VHD Users' Group (US) and the VHDL-Forum for CAD in Europe. This paper is aimed at emphasizing the engineering and scientific point of view toward the activities of the VHDL-Forum for CAD in Europe.<>
{"title":"VHDL-Forum for CAD in Europe: an engineering & scientific point of view","authors":"A. Hohl","doi":"10.1109/EASIC.1990.207932","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207932","url":null,"abstract":"As it is well known, the development of the hardware description language (HDL) VHDL was started in 1980 sponsored by the US Department of Defense. Today VHDL has become an important topic in research development, and CAE fields in the US as well as in Europe. Because of this development, user groups were established during the last years, namely the VHD Users' Group (US) and the VHDL-Forum for CAD in Europe. This paper is aimed at emphasizing the engineering and scientific point of view toward the activities of the VHDL-Forum for CAD in Europe.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128173026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207955
Y. Nakamura, K. Oguri, A. Nagoya, R. Nomura
Describes the hierarchical behavioral description language called SFL and its processing system. SFL was developed to aid in the design of the hardware functions and behaviors of ASICs composed solely of clock-synchronized circuits. The main features of SFL are as follows: (1) It is not mixed with connection description, but employs only behavioral description (like procedural description in program language), and it provides hierarchical expression of behavioral description. (2) It permits the description of parallel processing operations by adopting a new hardware task concept. And, (3) it is linked with the behavioral simulator, logic synthesizer, and other components of the processing system. After describing SFL in some detail, a brief explanation of its synthesizer and other processing components is provided, along with its application results in the design of some ASICs.<>
{"title":"A hierarchical behavioural description based CAD system","authors":"Y. Nakamura, K. Oguri, A. Nagoya, R. Nomura","doi":"10.1109/EASIC.1990.207955","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207955","url":null,"abstract":"Describes the hierarchical behavioral description language called SFL and its processing system. SFL was developed to aid in the design of the hardware functions and behaviors of ASICs composed solely of clock-synchronized circuits. The main features of SFL are as follows: (1) It is not mixed with connection description, but employs only behavioral description (like procedural description in program language), and it provides hierarchical expression of behavioral description. (2) It permits the description of parallel processing operations by adopting a new hardware task concept. And, (3) it is linked with the behavioral simulator, logic synthesizer, and other components of the processing system. After describing SFL in some detail, a brief explanation of its synthesizer and other processing components is provided, along with its application results in the design of some ASICs.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123028652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207971
H. Courjon
Increasingly complex ASICs need Design For Testability (DFT) techniques to by-pass the test bottleneck. Among the most popular is scan test. The Philips ASIC Test Environment (PATE) includes tools and libraries for scan test and gives ASIC designers a natural approach to DFT. The Philips Components software tools AMSAL and SIMTAP provide Automatic Test Pattern Generation (ATPG) and testability analysis. The silicon overhead due to the scan technique is minimized by dedicated scan flip-flops in the Philips Components ASIC libraries. The PATE approach ensures high quality test vectors and predictable development time from design capture to automatic test vector generation. This paper briefly recalls the basics of scan techniques and then shows their integration in PATE. It finishes with a practical example.<>
{"title":"Scan design in the Philips ASIC test environment","authors":"H. Courjon","doi":"10.1109/EASIC.1990.207971","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207971","url":null,"abstract":"Increasingly complex ASICs need Design For Testability (DFT) techniques to by-pass the test bottleneck. Among the most popular is scan test. The Philips ASIC Test Environment (PATE) includes tools and libraries for scan test and gives ASIC designers a natural approach to DFT. The Philips Components software tools AMSAL and SIMTAP provide Automatic Test Pattern Generation (ATPG) and testability analysis. The silicon overhead due to the scan technique is minimized by dedicated scan flip-flops in the Philips Components ASIC libraries. The PATE approach ensures high quality test vectors and predictable development time from design capture to automatic test vector generation. This paper briefly recalls the basics of scan techniques and then shows their integration in PATE. It finishes with a practical example.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"36 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123355944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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