Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207903
G. Rietsche, M. Neher
The authors describe some of the state assignment heuristics, which are applied in the finite state machine synthesis system CASTOR. They concentrate on algorithms for two-level logic implementations, while work on algorithms for multi-level logic implementations is in progress. Input to the system is a description of the FSM in form of a state table. CASTOR generates an appropriate controller consisting of pre- and postprocessing structures around a kernel FSM, which may be a PLA, a ROM or random logic. In the case of a PLA or random logical controller coding constraints are extracted for the kernel FSM. Then these coding constraints have to be satisfied by adequate state assignment algorithms in order to minimize the area of the physical implementation.<>
{"title":"CASTOR: state assignment in a finite state machine synthesis system","authors":"G. Rietsche, M. Neher","doi":"10.1109/EASIC.1990.207903","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207903","url":null,"abstract":"The authors describe some of the state assignment heuristics, which are applied in the finite state machine synthesis system CASTOR. They concentrate on algorithms for two-level logic implementations, while work on algorithms for multi-level logic implementations is in progress. Input to the system is a description of the FSM in form of a state table. CASTOR generates an appropriate controller consisting of pre- and postprocessing structures around a kernel FSM, which may be a PLA, a ROM or random logic. In the case of a PLA or random logical controller coding constraints are extracted for the kernel FSM. Then these coding constraints have to be satisfied by adequate state assignment algorithms in order to minimize the area of the physical implementation.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123421638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207978
F. Durbin, J. Haussy, G. Berthiau, P. Siarry, W.M. Zuberek
The circuit design problem consists in determining acceptable parameter values (resistors, capacitors, transistor geometries . . .) which allow the circuit to meet various user given operational criteria (DC consumption, AC bandwidth, transient rise times, etc.). This task is equivalent to a multidimensional and/or multi objective optimization problem: n-variables functions have to be minimized in an hyperrectangular domain: equality and/or inequality constraints can be eventually specified. The authors propose an efficient algorithm, based on the repeated application of simulated annealing to a certain number of p-variables sub problems, with p<>
{"title":"Integrated circuit performance optimization with simulated annealing algorithm and SPICE-PAC circuit simulator","authors":"F. Durbin, J. Haussy, G. Berthiau, P. Siarry, W.M. Zuberek","doi":"10.1109/EASIC.1990.207978","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207978","url":null,"abstract":"The circuit design problem consists in determining acceptable parameter values (resistors, capacitors, transistor geometries . . .) which allow the circuit to meet various user given operational criteria (DC consumption, AC bandwidth, transient rise times, etc.). This task is equivalent to a multidimensional and/or multi objective optimization problem: n-variables functions have to be minimized in an hyperrectangular domain: equality and/or inequality constraints can be eventually specified. The authors propose an efficient algorithm, based on the repeated application of simulated annealing to a certain number of p-variables sub problems, with p<<n. Objective functions are computed through the modular SPICE-PAC simulator, which is controlled by the optimization algorithm.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128460927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207932
A. Hohl
As it is well known, the development of the hardware description language (HDL) VHDL was started in 1980 sponsored by the US Department of Defense. Today VHDL has become an important topic in research development, and CAE fields in the US as well as in Europe. Because of this development, user groups were established during the last years, namely the VHD Users' Group (US) and the VHDL-Forum for CAD in Europe. This paper is aimed at emphasizing the engineering and scientific point of view toward the activities of the VHDL-Forum for CAD in Europe.<>
{"title":"VHDL-Forum for CAD in Europe: an engineering & scientific point of view","authors":"A. Hohl","doi":"10.1109/EASIC.1990.207932","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207932","url":null,"abstract":"As it is well known, the development of the hardware description language (HDL) VHDL was started in 1980 sponsored by the US Department of Defense. Today VHDL has become an important topic in research development, and CAE fields in the US as well as in Europe. Because of this development, user groups were established during the last years, namely the VHD Users' Group (US) and the VHDL-Forum for CAD in Europe. This paper is aimed at emphasizing the engineering and scientific point of view toward the activities of the VHDL-Forum for CAD in Europe.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128173026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207952
S.G. Smith, R. Morgan, J. Payne
Although digital signal processing is emerging as a major technological applications area, one has yet to witness the flourish of integrated-circuit design automation techniques which accompanied the recent boom in the computer industry. A potential catalyst to bring this about is the nascent field of high-level synthesis, which promises to furnish conventional datapath architectures with the power of parallelism and pipelining. This paper reports progress in a high-level IC design tool intended specifically for DSP users, now more than one year in development. While parallelism and pipelining are naturally exploited, novel use is made of synthesis techniques at bit-level, which brings both advantages and disadvantages in comparison to high-level synthesis. The approach is powerful and efficient in high-throughput, fixed-function applications.<>
{"title":"Progress in DSP design automation","authors":"S.G. Smith, R. Morgan, J. Payne","doi":"10.1109/EASIC.1990.207952","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207952","url":null,"abstract":"Although digital signal processing is emerging as a major technological applications area, one has yet to witness the flourish of integrated-circuit design automation techniques which accompanied the recent boom in the computer industry. A potential catalyst to bring this about is the nascent field of high-level synthesis, which promises to furnish conventional datapath architectures with the power of parallelism and pipelining. This paper reports progress in a high-level IC design tool intended specifically for DSP users, now more than one year in development. While parallelism and pipelining are naturally exploited, novel use is made of synthesis techniques at bit-level, which brings both advantages and disadvantages in comparison to high-level synthesis. The approach is powerful and efficient in high-throughput, fixed-function applications.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124546547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207950
V. Grimblatt-Hinzpeter, C. Kingsley
Gives an overview of the VLSI Technology ASIC synthesizer. It is a synthesis tool that is able to compile whole chips from a hardware description language specification. Synthesis tools like this will increase the productivity of chip design to such an extent that current techniques of circuit design will someday be obsolete. The authors describe in this paper the capabilities that the ASIC Synthesizer has, the development phases and some applications.<>
{"title":"Designing an ASIC with the VLSI Technology ASIC synthesizer","authors":"V. Grimblatt-Hinzpeter, C. Kingsley","doi":"10.1109/EASIC.1990.207950","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207950","url":null,"abstract":"Gives an overview of the VLSI Technology ASIC synthesizer. It is a synthesis tool that is able to compile whole chips from a hardware description language specification. Synthesis tools like this will increase the productivity of chip design to such an extent that current techniques of circuit design will someday be obsolete. The authors describe in this paper the capabilities that the ASIC Synthesizer has, the development phases and some applications.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127871570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207976
B. Kaminska, F. Mheir-El-Saadi
The object of this paper is to propose an ASIC design model that incorporates two aspects: design as a decision-making process and expert-like knowledge-based design control. The authors provide a integrated solution for the following important issues: incremental propagation of design characteristics, checking for design specification violation, evaluation of the quality of a design, and choosing the most appropriate solution. This paper attempts to make a step towards the building of a theoretical framework for knowledge-based design control based on the decision theory and expert systems methodology.<>
{"title":"A framework for performance and knowledge-based control of basic designs","authors":"B. Kaminska, F. Mheir-El-Saadi","doi":"10.1109/EASIC.1990.207976","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207976","url":null,"abstract":"The object of this paper is to propose an ASIC design model that incorporates two aspects: design as a decision-making process and expert-like knowledge-based design control. The authors provide a integrated solution for the following important issues: incremental propagation of design characteristics, checking for design specification violation, evaluation of the quality of a design, and choosing the most appropriate solution. This paper attempts to make a step towards the building of a theoretical framework for knowledge-based design control based on the decision theory and expert systems methodology.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133011883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207909
R. Cates, J. J. Farrell
Describes a hard disk controller application and the RISC-based ISA Bus coprocessor called the I/O processor (IOP) from which the hard disk application was developed. The IOP is used as a central element in ISA (Industry Standard Architecture)-based peripheral controller applications. In this specific application, it incorporates a comprehensive set of function blocks in addition to the core 32-bit RISC processor. These include an ISA address decoder, a register file compatible with the PC/AT-compatible hard disk controller, a DRAM controller capable of support 16 M bytes of 32-bit memory, an interrupt controller, a DMA controller, a 2 K-byte ROM and a 512-byte RAM. The IOP has been optimized for application requiring high data transfer rates. Burst data transfers up to 40 M bytes per second may be attained with the RISC processor running at 10 MHz. A paging and interleaving DRAM controller is utilized so that slower DRAMs with 100 nanoseconds access times can be used.<>
{"title":"An ASIC RISC-based I/O processor for computer applications","authors":"R. Cates, J. J. Farrell","doi":"10.1109/EASIC.1990.207909","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207909","url":null,"abstract":"Describes a hard disk controller application and the RISC-based ISA Bus coprocessor called the I/O processor (IOP) from which the hard disk application was developed. The IOP is used as a central element in ISA (Industry Standard Architecture)-based peripheral controller applications. In this specific application, it incorporates a comprehensive set of function blocks in addition to the core 32-bit RISC processor. These include an ISA address decoder, a register file compatible with the PC/AT-compatible hard disk controller, a DRAM controller capable of support 16 M bytes of 32-bit memory, an interrupt controller, a DMA controller, a 2 K-byte ROM and a 512-byte RAM. The IOP has been optimized for application requiring high data transfer rates. Burst data transfers up to 40 M bytes per second may be attained with the RISC processor running at 10 MHz. A paging and interleaving DRAM controller is utilized so that slower DRAMs with 100 nanoseconds access times can be used.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130303193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207906
D. Ku, G. De Micheli
Presents an approach to automated synthesis of digital circuits from behavioral specifications. The system, called Hercules and Hebe, offers many advantages to the designer. First, the system supports constraint-driven synthesis where timing and resource constraints are applied to guide the synthesis decisions. Second, systematic design space exploration is possible, where the designer explores the tradeoff between area and performance to meet the design objectives. Third, logic synthesis techniques are uniformly incorporated within the synthesis framework to provide estimates to guide high-level decisions. Along with a synthesis oriented hardware description language called HardwareC, Hercules/Hebe provides an environment for the design of general synchronous digital circuits, with specific attention to the requirements of ASIC designs. The system has been applied to complex ASIC designs, including the Digital Audio I/O, MAMA, and Bi-Dimensional DCT chips.<>
{"title":"High-level synthesis and optimization strategies in Hercules and Hebe","authors":"D. Ku, G. De Micheli","doi":"10.1109/EASIC.1990.207906","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207906","url":null,"abstract":"Presents an approach to automated synthesis of digital circuits from behavioral specifications. The system, called Hercules and Hebe, offers many advantages to the designer. First, the system supports constraint-driven synthesis where timing and resource constraints are applied to guide the synthesis decisions. Second, systematic design space exploration is possible, where the designer explores the tradeoff between area and performance to meet the design objectives. Third, logic synthesis techniques are uniformly incorporated within the synthesis framework to provide estimates to guide high-level decisions. Along with a synthesis oriented hardware description language called HardwareC, Hercules/Hebe provides an environment for the design of general synchronous digital circuits, with specific attention to the requirements of ASIC designs. The system has been applied to complex ASIC designs, including the Digital Audio I/O, MAMA, and Bi-Dimensional DCT chips.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122230334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207910
O. Vainio, H. Tenhunen, J. Nurmi
The two alternative design approaches discussed in this paper are dedicated DSP architectures and the core processor based design methodology. By the development of area-efficient high resolution A/D converters, it has become feasible to integrate the analog interface on the same chip with the DSP operations. However, lack of an interdisciplinary high-level CAE environment tends to lengthen the design times of DSP-ASICs.<>
{"title":"Architecture and circuit design for DSP-ASIC","authors":"O. Vainio, H. Tenhunen, J. Nurmi","doi":"10.1109/EASIC.1990.207910","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207910","url":null,"abstract":"The two alternative design approaches discussed in this paper are dedicated DSP architectures and the core processor based design methodology. By the development of area-efficient high resolution A/D converters, it has become feasible to integrate the analog interface on the same chip with the DSP operations. However, lack of an interdisciplinary high-level CAE environment tends to lengthen the design times of DSP-ASICs.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125148165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-29DOI: 10.1109/EASIC.1990.207916
A. Fabre, M. Alami
A translinear standard-cell approach in the field of analog ASICs is proposed. The translinear circuit principle is first summarized and an overview of the various properties which result from the implementation of translinear circuits is outlined. The concept of an hierarchic library, all in a translinear form, is introduced. Both basic cells, the current mirrors and the translinear mixed loops, appear to be the most important cells from which elementary building blocks (i.e. followers, conveyors. . .) can be implemented. Then, as demonstrated by some illustrative examples, high performance advanced macroblocks (i.e. amplifiers, filters. . .etc.) will be obtained. Simulated results, with SPICE, are given and discussed.<>
{"title":"A versatile translinear cell-library to implement high performance analog ASICs","authors":"A. Fabre, M. Alami","doi":"10.1109/EASIC.1990.207916","DOIUrl":"https://doi.org/10.1109/EASIC.1990.207916","url":null,"abstract":"A translinear standard-cell approach in the field of analog ASICs is proposed. The translinear circuit principle is first summarized and an overview of the various properties which result from the implementation of translinear circuits is outlined. The concept of an hierarchic library, all in a translinear form, is introduced. Both basic cells, the current mirrors and the translinear mixed loops, appear to be the most important cells from which elementary building blocks (i.e. followers, conveyors. . .) can be implemented. Then, as demonstrated by some illustrative examples, high performance advanced macroblocks (i.e. amplifiers, filters. . .etc.) will be obtained. Simulated results, with SPICE, are given and discussed.<<ETX>>","PeriodicalId":205695,"journal":{"name":"[Proceedings] EURO ASIC `90","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116600735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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