Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63876
F. Baba, A. Sinclair
A wafer scale memory has now been developed that has achieved a high enough yield to make it practical to manufacture. This CMOS wafer scale memory was developed with high density and low cost as higher priorities than high speed. The device fills a gap in the hierarchy of computer memory between high speed, high priced main memory and low speed, low priced off-line or hard disk memory. To achieve high density, standard 1-Mb DRAMs with a small amount of control logic were arranged as an array on the wafer. Partially good DRAMs are used as the basis for these devices, and several redundancy techniques requiring no additional process steps are used to increase yield. Since the number of wire bonds and solder joints was reduced by 90% compared to the same device manufactured using discrete DRAM chips, the reliability factor of these devices was greatly increased.<>
{"title":"200-Mb wafer scale memory","authors":"F. Baba, A. Sinclair","doi":"10.1109/ICWSI.1990.63876","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63876","url":null,"abstract":"A wafer scale memory has now been developed that has achieved a high enough yield to make it practical to manufacture. This CMOS wafer scale memory was developed with high density and low cost as higher priorities than high speed. The device fills a gap in the hierarchy of computer memory between high speed, high priced main memory and low speed, low priced off-line or hard disk memory. To achieve high density, standard 1-Mb DRAMs with a small amount of control logic were arranged as an array on the wafer. Partially good DRAMs are used as the basis for these devices, and several redundancy techniques requiring no additional process steps are used to increase yield. Since the number of wire bonds and solder joints was reduced by 90% compared to the same device manufactured using discrete DRAM chips, the reliability factor of these devices was greatly increased.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"372 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122345959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63903
N. Tsuda
Advanced redundancy configurations of static RAM modules based on word duplication and selection by horizontal parity checking (WDSH), as well as based on error correction by horizontal and vertical parity checking (ECHV), are proposed for enhancement of defect and fault tolerance capability of WSIs. The following additional redundancy technologies are applied to them: word selection by automatic access error checking, pair unit replacement are for WDSH-based configurations using multiple RAM units, and two-level hierarchical redundancy is for ECHV-based ones. Performance estimation using a 1.5-micron 128 K-bit CMOS static RAM module model indicates that a remarkably higher degree of effective active area reduction, in respect to defect and fault occurrence, can be attained by an optimum WDSH-based configuration than by a general triplication-based redundancy configuration.<>
{"title":"A defect and fault tolerant design of WSI static RAM modules","authors":"N. Tsuda","doi":"10.1109/ICWSI.1990.63903","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63903","url":null,"abstract":"Advanced redundancy configurations of static RAM modules based on word duplication and selection by horizontal parity checking (WDSH), as well as based on error correction by horizontal and vertical parity checking (ECHV), are proposed for enhancement of defect and fault tolerance capability of WSIs. The following additional redundancy technologies are applied to them: word selection by automatic access error checking, pair unit replacement are for WDSH-based configurations using multiple RAM units, and two-level hierarchical redundancy is for ECHV-based ones. Performance estimation using a 1.5-micron 128 K-bit CMOS static RAM module model indicates that a remarkably higher degree of effective active area reduction, in respect to defect and fault occurrence, can be attained by an optimum WDSH-based configuration than by a general triplication-based redundancy configuration.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116368918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63892
U. Ramacher, M. Wesseling, K. Goser
Discusses application and technology related constraints on the implementation of neurocomputing systems on a wafer. The resulting neurocomputer architecture builds on the experience obtained with a 42 cm/sup 2/ soft-configured chip which carries a 2-dimensional array of multipliers in CMOS. The architecture is specially adapted to pattern recognition of video images by means of generalized multilayer-perceptrons.<>
{"title":"WSI architecture of a neurocomputer module","authors":"U. Ramacher, M. Wesseling, K. Goser","doi":"10.1109/ICWSI.1990.63892","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63892","url":null,"abstract":"Discusses application and technology related constraints on the implementation of neurocomputing systems on a wafer. The resulting neurocomputer architecture builds on the experience obtained with a 42 cm/sup 2/ soft-configured chip which carries a 2-dimensional array of multipliers in CMOS. The architecture is specially adapted to pattern recognition of video images by means of generalized multilayer-perceptrons.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134429698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63890
A.D. Singh, H. Youn
Performance is the one area in which a monolithic technology has potential unmatched by other approaches. Integrating an entire high performance system on a single piece of silicon eliminates the off-chip signal delays encountered in multichip implementations, which can become the performance bottleneck in highly pipelined array architectures. The major problem with achieving full wafer integration is that it is virtually impossible to realize such large area circuits entirely defect free. The authors present a scheme which can reconfigure the rectangular array using channel width of 2, while allowing short maximum restructured edge length. The yield of desired array in their design is much higher than that of other designs with same degree of redundancy.<>
{"title":"Defect tolerance scheme for gigaFLOP WSI architectures","authors":"A.D. Singh, H. Youn","doi":"10.1109/ICWSI.1990.63890","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63890","url":null,"abstract":"Performance is the one area in which a monolithic technology has potential unmatched by other approaches. Integrating an entire high performance system on a single piece of silicon eliminates the off-chip signal delays encountered in multichip implementations, which can become the performance bottleneck in highly pipelined array architectures. The major problem with achieving full wafer integration is that it is virtually impossible to realize such large area circuits entirely defect free. The authors present a scheme which can reconfigure the rectangular array using channel width of 2, while allowing short maximum restructured edge length. The yield of desired array in their design is much higher than that of other designs with same degree of redundancy.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132656867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63891
F. Distante, M. Sami, G. Storti Gajani
Presents a solution that allows flexible mapping of neural nets (such as multi-layered ones) onto uncommitted processing arrays in which a large number of processing elements are interconnected by a switched-bus network. The basic algorithms leading to such mapping are outlined, providing a balance between structure simplicity and parallelism of operation speed. A protocol by which the array can be configured (and, therefore, initialized) is presented: nominal operation is then described, and it is seen that the same solution providing for initialization supports also subsequent algorithms. The structure of the basic elements of the architecture (switches and processing elements) is detailed, so as to allow an evaluation of complexity as regards silicon requirements in CMOS.<>
{"title":"A general configurable architecture for WSI implementation for neural nets","authors":"F. Distante, M. Sami, G. Storti Gajani","doi":"10.1109/ICWSI.1990.63891","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63891","url":null,"abstract":"Presents a solution that allows flexible mapping of neural nets (such as multi-layered ones) onto uncommitted processing arrays in which a large number of processing elements are interconnected by a switched-bus network. The basic algorithms leading to such mapping are outlined, providing a balance between structure simplicity and parallelism of operation speed. A protocol by which the array can be configured (and, therefore, initialized) is presented: nominal operation is then described, and it is seen that the same solution providing for initialization supports also subsequent algorithms. The structure of the basic elements of the architecture (switches and processing elements) is detailed, so as to allow an evaluation of complexity as regards silicon requirements in CMOS.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133410519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63912
U. Jagau, K. Dyck, H. Grabinski, Hiroshi Iden, M. Kuboschek
Investigations have shown that the layout of power lines and isolation circuits as well as the modules' circuit switching has a large influence on the behavior of the whole system. A current estimation strategy for the calculation of the module current consumption in CMOS technology is investigated. The electrical behavior of losses in signal and power lines is taken into account. An efficient current estimation is introduced with a new program-SIMCURRENT. Another program carries out analog circuit simulations including the modelling of coupled lossy transmission lines. Fast and accurate estimates of the I/sub dd/-current are carried out by SIMCURRENT. Simulations-often not possible with classical circuit analysis programs-were made with the program LISM. Regarding monolithic systems, one must include power isolation circuits in the power rail system. A proper layout of the global supply network (not using the lowest resistive layout) is proposed.<>
{"title":"Power distribution strategies based on current estimation and simulation of lossy transmission lines in conjunction with power isolation circuits","authors":"U. Jagau, K. Dyck, H. Grabinski, Hiroshi Iden, M. Kuboschek","doi":"10.1109/ICWSI.1990.63912","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63912","url":null,"abstract":"Investigations have shown that the layout of power lines and isolation circuits as well as the modules' circuit switching has a large influence on the behavior of the whole system. A current estimation strategy for the calculation of the module current consumption in CMOS technology is investigated. The electrical behavior of losses in signal and power lines is taken into account. An efficient current estimation is introduced with a new program-SIMCURRENT. Another program carries out analog circuit simulations including the modelling of coupled lossy transmission lines. Fast and accurate estimates of the I/sub dd/-current are carried out by SIMCURRENT. Simulations-often not possible with classical circuit analysis programs-were made with the program LISM. Regarding monolithic systems, one must include power isolation circuits in the power rail system. A proper layout of the global supply network (not using the lowest resistive layout) is proposed.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132874247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63914
R. Schmidt
Describes a monolithic multilayer thin film technology featuring discretionary wiring and a cellular design methodology which borrows heavily from VLSI design/fabrication technology. Referred to herein as Hybrid Wafer Scale Interconnect (HWSI), it preserves in many ways the advantages of monolithic Wafer Scale Integration (WSI), while simultaneously offering higher yield and superior performance typically associated with optimized subassemblies. It is noteworthy that many 'monolithic' WSI systems currently under development utilize the same, or even more discrete subassemblies, than the proposed HWSI technology.<>
{"title":"Hybrid wafer scale interconnection inventing a new technology","authors":"R. Schmidt","doi":"10.1109/ICWSI.1990.63914","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63914","url":null,"abstract":"Describes a monolithic multilayer thin film technology featuring discretionary wiring and a cellular design methodology which borrows heavily from VLSI design/fabrication technology. Referred to herein as Hybrid Wafer Scale Interconnect (HWSI), it preserves in many ways the advantages of monolithic Wafer Scale Integration (WSI), while simultaneously offering higher yield and superior performance typically associated with optimized subassemblies. It is noteworthy that many 'monolithic' WSI systems currently under development utilize the same, or even more discrete subassemblies, than the proposed HWSI technology.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116139653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63881
I. Jalowiecki, S. Hedge
The aim of the Brunel University/Aspex Microsystems WASP (WSI Associative String Processor) project is the production of high performance, cost-effective, practical monolithic Wafer-Scale Parallel Processing systems. The Associative String Processor (ASP) architecture is a massively parallel, fine-grain architecture, suitable for VLSI, ULSI and WSI fabrication. Following a considerable period of test chip experimentation, addressing fundamental WSI design issues, this work graduated to a programme of first technology, and then functional demonstrators. Designed to progress towards a practical WASP in a series of carefully planned steps, these devices prove the feasibility of the WASP architecture and provide engineering data and proof of principle unobtainable by any other means. The authors summarise the demonstrator programme to date, including the test results from the first technology demonstrator (WASP 1) and the architecture of the second technology demonstrator (WASP 2).<>
{"title":"The WASP demonstrator programme: the engineering of a wafer-scale system","authors":"I. Jalowiecki, S. Hedge","doi":"10.1109/ICWSI.1990.63881","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63881","url":null,"abstract":"The aim of the Brunel University/Aspex Microsystems WASP (WSI Associative String Processor) project is the production of high performance, cost-effective, practical monolithic Wafer-Scale Parallel Processing systems. The Associative String Processor (ASP) architecture is a massively parallel, fine-grain architecture, suitable for VLSI, ULSI and WSI fabrication. Following a considerable period of test chip experimentation, addressing fundamental WSI design issues, this work graduated to a programme of first technology, and then functional demonstrators. Designed to progress towards a practical WASP in a series of carefully planned steps, these devices prove the feasibility of the WASP architecture and provide engineering data and proof of principle unobtainable by any other means. The authors summarise the demonstrator programme to date, including the test results from the first technology demonstrator (WASP 1) and the architecture of the second technology demonstrator (WASP 2).<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122086227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63886
J. T. Arcos, B. Evans, S. Kung
The crosspoint (or crossbar) switch allows direct connection between arbitrary pairs of processors, minimizing the communication time overhead, but is considered impractical for large numbers of processors because the number of required connections is proportional to the square of the number of processors. However, crosspoint switches are very useful for small configurations (tens vs. hundreds of processors). In this paper, the authors explore the use of a crosspoint switch as the backbone of a general parallel arithmetic processor. This approach is appealing because it permits a compact, simple and easily producible chip set that could perform a variety of signal processing functions at high speed. The design can also provide the reconfigurability critical for improving the fault tolerance of the architecture. The basic configuration of the Crosspoint Arithmetic Processor (CAP) system consists of three principal components: a 32*32 crosspoint switch, an array of 32 computational nodes (CN), and a system controller.<>
{"title":"Crosspoint Arithmetic Processor architecture for wafer scale integration","authors":"J. T. Arcos, B. Evans, S. Kung","doi":"10.1109/ICWSI.1990.63886","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63886","url":null,"abstract":"The crosspoint (or crossbar) switch allows direct connection between arbitrary pairs of processors, minimizing the communication time overhead, but is considered impractical for large numbers of processors because the number of required connections is proportional to the square of the number of processors. However, crosspoint switches are very useful for small configurations (tens vs. hundreds of processors). In this paper, the authors explore the use of a crosspoint switch as the backbone of a general parallel arithmetic processor. This approach is appealing because it permits a compact, simple and easily producible chip set that could perform a variety of signal processing functions at high speed. The design can also provide the reconfigurability critical for improving the fault tolerance of the architecture. The basic configuration of the Crosspoint Arithmetic Processor (CAP) system consists of three principal components: a 32*32 crosspoint switch, an array of 32 computational nodes (CN), and a system controller.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115658208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63911
K. Ganapathy, A.D. Singh, D. Pradhan
Presents and analyzes redundant large area TRAM architectures (64 to 512 Mbit) for variations in redundancy level and determine the optimal redundancy organization for yield enhancement. A hierarchical redundancy scheme is used for defect tolerance and the yield of the redundant RAM is modelled using a compounded Poisson model. Results are presented that show the tradeoff in local versus global redundancy schemes for TRAM.<>
{"title":"Yield modeling and optimization of large redundant RAMs","authors":"K. Ganapathy, A.D. Singh, D. Pradhan","doi":"10.1109/ICWSI.1990.63911","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63911","url":null,"abstract":"Presents and analyzes redundant large area TRAM architectures (64 to 512 Mbit) for variations in redundancy level and determine the optimal redundancy organization for yield enhancement. A hierarchical redundancy scheme is used for defect tolerance and the yield of the redundant RAM is modelled using a compounded Poisson model. Results are presented that show the tradeoff in local versus global redundancy schemes for TRAM.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125379232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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