Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63897
P. Franzon, D. van den Bout, J. Paulos, T. Miller, W. Snyder, T. Nagle, Wentai Liu
Many of the defect tolerant techniques employed to achieve wafer-scale integration can also be used to construct flexible and scalable architectures. These techniques are applied to two artificial neural networks: a feed-forward analog network with backpropagation and an efficient digital recurrent network.<>
{"title":"Defect tolerant implementations of feed-forward and recurrent neural networks","authors":"P. Franzon, D. van den Bout, J. Paulos, T. Miller, W. Snyder, T. Nagle, Wentai Liu","doi":"10.1109/ICWSI.1990.63897","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63897","url":null,"abstract":"Many of the defect tolerant techniques employed to achieve wafer-scale integration can also be used to construct flexible and scalable architectures. These techniques are applied to two artificial neural networks: a feed-forward analog network with backpropagation and an efficient digital recurrent network.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126724421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63879
D. L. Allen, A. Anderson, C. Rader, C. Woodward
MUSE (Matrix Update Systolic Experiment) is a special-purpose digital signal processor being implemented using restructurable VLSI. It will consist of 5 million working transistors on a single wafer-scale integrated circuit. MUSE is a wafer-scale systolic array designed to operate at the continuous rate of 285 million rotations per second. It will enable space-based radar systems to perform real-time adaptive nulling on up to 63 jammers with nulls of 50 dB. The rotator cell has been fabricated in 2 mu m CMOS; a small testbed for 4 PEs has been built and operates at specification. Design for the wafer-scale interconnect is in progress. MUSE is a 1.7 Billion Real Operations per Second system which fits on a single 4" by 4" silicon substrate.<>
{"title":"MUSE: a wafer-scale systolic DSP","authors":"D. L. Allen, A. Anderson, C. Rader, C. Woodward","doi":"10.1109/ICWSI.1990.63879","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63879","url":null,"abstract":"MUSE (Matrix Update Systolic Experiment) is a special-purpose digital signal processor being implemented using restructurable VLSI. It will consist of 5 million working transistors on a single wafer-scale integrated circuit. MUSE is a wafer-scale systolic array designed to operate at the continuous rate of 285 million rotations per second. It will enable space-based radar systems to perform real-time adaptive nulling on up to 63 jammers with nulls of 50 dB. The rotator cell has been fabricated in 2 mu m CMOS; a small testbed for 4 PEs has been built and operates at specification. Design for the wafer-scale interconnect is in progress. MUSE is a 1.7 Billion Real Operations per Second system which fits on a single 4\" by 4\" silicon substrate.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114471675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63905
T. Varvarigou, V. Roychowdhury, T. Kailath
Deals with the issue of reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources. The models discussed consist of a set of identical Processing Elements (PEs) embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. Furthermore in order to incorporate fault tolerance a given array has a pre-determined distribution of spare PEs. The general issue in reconfiguration is to replace faulty non-spare PEs by healthy spare ones, subject to given hardware constraints. The authors present some new algorithms for reconfiguring N*(N+1) arrays (where the spare PEs are configured in the form of a spare row) into N*N arrays when N of the PEs are faulty. The algorithms developed are simple and perform better than other reconfiguration algorithms presented in the literature.<>
{"title":"Some new algorithms for reconfiguring VLSI/WSI arrays","authors":"T. Varvarigou, V. Roychowdhury, T. Kailath","doi":"10.1109/ICWSI.1990.63905","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63905","url":null,"abstract":"Deals with the issue of reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources. The models discussed consist of a set of identical Processing Elements (PEs) embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. Furthermore in order to incorporate fault tolerance a given array has a pre-determined distribution of spare PEs. The general issue in reconfiguration is to replace faulty non-spare PEs by healthy spare ones, subject to given hardware constraints. The authors present some new algorithms for reconfiguring N*(N+1) arrays (where the spare PEs are configured in the form of a spare row) into N*N arrays when N of the PEs are faulty. The algorithms developed are simple and perform better than other reconfiguration algorithms presented in the literature.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115557591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63888
Patrick O. Nunally
Currently a monolithic self configuring test structure has been fabricated which achieves wafer scale integration levels through General Dynamics patented architecture, new technology and methodologies. The test structure uses a new double metal 3.0-micron GD/P:WSI CMOS technology. The device was not developed as a functional product, but rather as a test of the configuration manager, configuration management architecture and the new GD/P:WSI30G technology. The device consists of four quadrants of functionality clusters and configuration managers (CMs).<>
{"title":"Introduction of a new architecture for wafer integration through configuration hierarchies: resulting in practical monolithic self configuring wafer scale integration","authors":"Patrick O. Nunally","doi":"10.1109/ICWSI.1990.63888","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63888","url":null,"abstract":"Currently a monolithic self configuring test structure has been fabricated which achieves wafer scale integration levels through General Dynamics patented architecture, new technology and methodologies. The test structure uses a new double metal 3.0-micron GD/P:WSI CMOS technology. The device was not developed as a functional product, but rather as a test of the configuration manager, configuration management architecture and the new GD/P:WSI30G technology. The device consists of four quadrants of functionality clusters and configuration managers (CMs).<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128319770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63907
Jack S. N. Jean, H. Fu, S. Kung
Addresses the enhancement of fabrication yield for arrays of large number of processors. An array grid model based on two-and-half-track switches is adopted. It is shown that two-and-half-track switches, possessing much better reconfigurability capability than that of one-and-half-track switches, are more suitable for yield enhancement. Moreover, the authors are able to develop a reconfiguration algorithm based on the one-and-half-track reconfiguration algorithm. The algorithm can effectively deal with faults on the switches, wires, and connections.<>
{"title":"Yield enhancement for WSI array processors using two-and-half-track switches","authors":"Jack S. N. Jean, H. Fu, S. Kung","doi":"10.1109/ICWSI.1990.63907","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63907","url":null,"abstract":"Addresses the enhancement of fabrication yield for arrays of large number of processors. An array grid model based on two-and-half-track switches is adopted. It is shown that two-and-half-track switches, possessing much better reconfigurability capability than that of one-and-half-track switches, are more suitable for yield enhancement. Moreover, the authors are able to develop a reconfiguration algorithm based on the one-and-half-track reconfiguration algorithm. The algorithm can effectively deal with faults on the switches, wires, and connections.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126001036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63887
R. Horst
A new architecture is proposed for constructing a linear array from cells on a partially defective wafer. Each cell connects to its four nearest neighbors in a way that guarantees a fixed delay between any pair of communicating cells. Phase-shifted synchronous clocking further improves performance. A simple configuration scheme is presented, and is shown to exceed 96% harvest of working cells when the configuration logic yield is above 75%. The architecture is shown to compare favorably to existing schemes in terms of performance, yield and overhead.<>
{"title":"A linear-array WSI architecture for improved yield and performance","authors":"R. Horst","doi":"10.1109/ICWSI.1990.63887","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63887","url":null,"abstract":"A new architecture is proposed for constructing a linear array from cells on a partially defective wafer. Each cell connects to its four nearest neighbors in a way that guarantees a fixed delay between any pair of communicating cells. Phase-shifted synchronous clocking further improves performance. A simple configuration scheme is presented, and is shown to exceed 96% harvest of working cells when the configuration logic yield is above 75%. The architecture is shown to compare favorably to existing schemes in terms of performance, yield and overhead.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122364957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63902
V. Piuri
Design of fault-tolerant WSI array processors is discussed: the use of Berger codes is presented to introduce a unifying approach both for arithmetic and logic operations. Detection of unidirectional errors and costs of the coding technique are evaluated in architectures based upon parallel computing units. Different structures are proposed for concurrent error detection and fault-localisation.<>
{"title":"Fault-tolerant WSI array processors: the use of Berger codes in parallel arithmetic-logic units","authors":"V. Piuri","doi":"10.1109/ICWSI.1990.63902","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63902","url":null,"abstract":"Design of fault-tolerant WSI array processors is discussed: the use of Berger codes is presented to introduce a unifying approach both for arithmetic and logic operations. Detection of unidirectional errors and costs of the coding technique are evaluated in architectures based upon parallel computing units. Different structures are proposed for concurrent error detection and fault-localisation.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121019443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63915
J. T. Arcos, W.T. Kamiyama, E. Swartzlander, W.E. Young
Development of a cheap, high yield interconnection technology is crucial to implementing WSI circuits. However, limitations in process yield and design complexity experienced with monolithic (on-wafer) interconnect have prevented WSI from being commercially feasible. Button contacts, by providing a means of interconnecting working die for WSI processors external to the wafer, fulfil the requirements of WSI at significantly lower cost than monolithic approaches. After probe test, a printed circuit board is combined with button contacts to provide a flexible method of achieving the discretionary interconnect to good die. A prototype package has been built which demonstrates the feasibility of the authors' WSI interconnect and packaging approach. The authors discuss the button board packaging approach, the electrical characteristics of their button contact interconnect along with future applications of this technology.<>
{"title":"WSI implemented with button board interconnection","authors":"J. T. Arcos, W.T. Kamiyama, E. Swartzlander, W.E. Young","doi":"10.1109/ICWSI.1990.63915","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63915","url":null,"abstract":"Development of a cheap, high yield interconnection technology is crucial to implementing WSI circuits. However, limitations in process yield and design complexity experienced with monolithic (on-wafer) interconnect have prevented WSI from being commercially feasible. Button contacts, by providing a means of interconnecting working die for WSI processors external to the wafer, fulfil the requirements of WSI at significantly lower cost than monolithic approaches. After probe test, a printed circuit board is combined with button contacts to provide a flexible method of achieving the discretionary interconnect to good die. A prototype package has been built which demonstrates the feasibility of the authors' WSI interconnect and packaging approach. The authors discuss the button board packaging approach, the electrical characteristics of their button contact interconnect along with future applications of this technology.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125845698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63896
M. Blatt
A fault tolerant switch network is evaluated, using a pipelined memory system as an example application. Monte Carlo simulation predicts the yield of each circuit piece directly from the layout. Circuit yields are combined with a system model to predict wafer yield. Previous work described system models based on site yield. System models requiring low latency are shown to also depend on switch yield.<>
{"title":"Effects of switch failure on soft-configurable WSI yield","authors":"M. Blatt","doi":"10.1109/ICWSI.1990.63896","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63896","url":null,"abstract":"A fault tolerant switch network is evaluated, using a pipelined memory system as an example application. Monte Carlo simulation predicts the yield of each circuit piece directly from the layout. Circuit yields are combined with a system model to predict wafer yield. Previous work described system models based on site yield. System models requiring low latency are shown to also depend on switch yield.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121790422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63899
M. Campbell, M. Little, M. Yung
Describes recent progress in the area of in-use fault tolerance for a massively parallel array processor. Specifically, the authors have taken the existing architecture of the Hughes 3D Computer and added fault tolerance capability to it. This has been possible to accomplish in modular, uniform way because of the unique circuit partitioning and implementation of the 3D Computer. The single instruction multiple data stream (SIMD) design of the 3D Computer greatly simplifies the control and reconfiguration process, while the fine-grained parallelism permits a high degree of redundancy with very low overhead. They have adopted a hierarchical strategy that mirrors the structure of the 3D Computer itself. Static reconfiguration is supported by special purpose hardware, the Realignment Plane wafer type, which allows them to treat failures uniformly at the row/column, processing element, and functional element levels.<>
{"title":"Hierarchical fault tolerance for 3D microelectronics","authors":"M. Campbell, M. Little, M. Yung","doi":"10.1109/ICWSI.1990.63899","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63899","url":null,"abstract":"Describes recent progress in the area of in-use fault tolerance for a massively parallel array processor. Specifically, the authors have taken the existing architecture of the Hughes 3D Computer and added fault tolerance capability to it. This has been possible to accomplish in modular, uniform way because of the unique circuit partitioning and implementation of the 3D Computer. The single instruction multiple data stream (SIMD) design of the 3D Computer greatly simplifies the control and reconfiguration process, while the fine-grained parallelism permits a high degree of redundancy with very low overhead. They have adopted a hierarchical strategy that mirrors the structure of the 3D Computer itself. Static reconfiguration is supported by special purpose hardware, the Realignment Plane wafer type, which allows them to treat failures uniformly at the row/column, processing element, and functional element levels.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114803158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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