Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63894
J. Wills, V. Jain
Multiprocessor system architectures require the use of INterconnection NETworks (INNETs) to provide for movement of data or instructions between memory and the processing elements. When an INNET is an integral part of the system, a WSI implementation will generally require a large fraction of the wafer area. This paper presents an area-reducing algorithm for the data manipulator network in silicon implementations where two or more levels of metal are available. The objective of multilevel metalization, i.e., more than the traditional two-level metalization, is two-fold: (a) to reduce the silicon area used by the wiring, and (b) to provide for mask programmability of metal layers. The emphasis of this paper is on the first of these aspects.<>
{"title":"Data manipulator network for WSI designs","authors":"J. Wills, V. Jain","doi":"10.1109/ICWSI.1990.63894","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63894","url":null,"abstract":"Multiprocessor system architectures require the use of INterconnection NETworks (INNETs) to provide for movement of data or instructions between memory and the processing elements. When an INNET is an integral part of the system, a WSI implementation will generally require a large fraction of the wafer area. This paper presents an area-reducing algorithm for the data manipulator network in silicon implementations where two or more levels of metal are available. The objective of multilevel metalization, i.e., more than the traditional two-level metalization, is two-fold: (a) to reduce the silicon area used by the wiring, and (b) to provide for mask programmability of metal layers. The emphasis of this paper is on the first of these aspects.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121760521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63901
S. Horiguchi
Presents a novel redundancy sorting array for WSI implementation. The redundancy sorting array consists of a mesh connected odd-even transposition sort and a modified bitonic sort with spare cells. The fault tolerance performance of the redundancy sorting array is discussed.<>
{"title":"Fault tolerance performance of WSI systolic sorter","authors":"S. Horiguchi","doi":"10.1109/ICWSI.1990.63901","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63901","url":null,"abstract":"Presents a novel redundancy sorting array for WSI implementation. The redundancy sorting array consists of a mesh connected odd-even transposition sort and a modified bitonic sort with spare cells. The fault tolerance performance of the redundancy sorting array is discussed.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131265458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63908
D. Sciuto, F. Lombardi
Deals with the testing of one-dimensional arrays in a complexity independent of array size (C-testability). The first aspect of C-testability analyzed in this paper, is a new model for the internal organization of a basic cell under a restricted fault assumption. This paper also presents a new approach for multiple fault detection of one-dimensional (linear) arrays.<>
{"title":"Testing wafer scale arrays: constant testability under multiple faults","authors":"D. Sciuto, F. Lombardi","doi":"10.1109/ICWSI.1990.63908","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63908","url":null,"abstract":"Deals with the testing of one-dimensional arrays in a complexity independent of array size (C-testability). The first aspect of C-testability analyzed in this paper, is a new model for the internal organization of a basic cell under a restricted fault assumption. This paper also presents a new approach for multiple fault detection of one-dimensional (linear) arrays.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132643434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63893
Sheng-Chiech Liang, S. Kuo
To overcome the yield problem in WSI, it is necessary to include redundancy and use more regular architectures for implementation. The authors present a novel hierarchical fault tolerant sorting network which satisfies both application requirements and area-time complexity constraints. It is very regular in structure and hence more easily reconfigurable than any existing sorting network with the same time complexity. Redundancy is provided at each level of the hierarchy. Hierarchical reconfiguration is implemented by replacing the faulty cells with spare cells at the lowest level first, and go to the next higher level to perform reconfiguration if there is not enough redundancy at the current level. In addition to defect tolerance after fabrication, these redundant cells can also be used for single error correction at run time.<>
{"title":"Defect tolerant sorting networks for WSI implementation","authors":"Sheng-Chiech Liang, S. Kuo","doi":"10.1109/ICWSI.1990.63893","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63893","url":null,"abstract":"To overcome the yield problem in WSI, it is necessary to include redundancy and use more regular architectures for implementation. The authors present a novel hierarchical fault tolerant sorting network which satisfies both application requirements and area-time complexity constraints. It is very regular in structure and hence more easily reconfigurable than any existing sorting network with the same time complexity. Redundancy is provided at each level of the hierarchy. Hierarchical reconfiguration is implemented by replacing the faulty cells with spare cells at the lowest level first, and go to the next higher level to perform reconfiguration if there is not enough redundancy at the current level. In addition to defect tolerance after fabrication, these redundant cells can also be used for single error correction at run time.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130291885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63884
Jaehee You, S.S. Wong
An architecture with p multiplier-adder's per butterfly stage has been developed to implement a radix p FFT. It is based on the p-fold symmetry in radix p constant geometry FFT algorithm. A methodology to realize a high radix processing element with lower radix hardware is presented. It is suitable for wafer scale integration. The latency and throughput of this architecture are evaluated. An experimental processor chip to implement a radix 2, 8 point FFT has been successfully designed in CMOS and the results are discussed.<>
{"title":"A high performance single chip FFT array processor for wafer scale integration","authors":"Jaehee You, S.S. Wong","doi":"10.1109/ICWSI.1990.63884","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63884","url":null,"abstract":"An architecture with p multiplier-adder's per butterfly stage has been developed to implement a radix p FFT. It is based on the p-fold symmetry in radix p constant geometry FFT algorithm. A methodology to realize a high radix processing element with lower radix hardware is presented. It is suitable for wafer scale integration. The latency and throughput of this architecture are evaluated. An experimental processor chip to implement a radix 2, 8 point FFT has been successfully designed in CMOS and the results are discussed.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"R-32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126633257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63883
K. Nakahara, H. Hatanaka, S. Kura, Y. Suminaga, Y. Hotta, M. Okada, K. Miyata
The needs for high density mask programmable ROM (MROM) have increased rapidly due to the demand for storing the Kanji character fonts and dictionaries used in Japanese word processors. For example, desktop publishing uses MROMs for 80 M bits fixed data. The authors describe a 64 Mb MROM which employs a 'good pair selection' as a type of redundancy technique. Employing the technology a flat cell structure and a bank selection architecture and a 0.8 mu m CMOS process, they have developed high density 64 Mb MROM.<>
由于日语文字处理器需要存储汉字字体和字典，对高密度掩模可编程ROM (MROM)的需求迅速增加。例如，桌面出版使用mrom存储80m位固定数据。作者描述了一种64 Mb的MROM，它采用了“良好的对选择”作为一种冗余技术。采用扁平单元结构和银行选择架构以及0.8 μ m CMOS工艺，他们开发出了高密度64mb的MROM。
{"title":"A 64 Mb MROM with good pair selection architecture","authors":"K. Nakahara, H. Hatanaka, S. Kura, Y. Suminaga, Y. Hotta, M. Okada, K. Miyata","doi":"10.1109/ICWSI.1990.63883","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63883","url":null,"abstract":"The needs for high density mask programmable ROM (MROM) have increased rapidly due to the demand for storing the Kanji character fonts and dictionaries used in Japanese word processors. For example, desktop publishing uses MROMs for 80 M bits fixed data. The authors describe a 64 Mb MROM which employs a 'good pair selection' as a type of redundancy technique. Employing the technology a flat cell structure and a bank selection architecture and a 0.8 mu m CMOS process, they have developed high density 64 Mb MROM.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115162429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63898
P. Ryan, D. Saab, W. Kent Fuchs
A visually oriented fault simulation environment for WSI architectures based on behavioral simulation of parallel message passing processors and switch-level fault simulation of selected processors is described. The environment was implemented by interfacing the CHAMP switch-level simulator with the OODRA behavioral simulator. The simulation environment was used to measure the fault coverage for a digital adaptive beamforming architecture with a synthetic workload. Fault coverage variation with input set size and array location was investigated. The rate at which faults produce errors in the architecture was also measured.<>
{"title":"A visually oriented architectural fault simulation environment for WSI","authors":"P. Ryan, D. Saab, W. Kent Fuchs","doi":"10.1109/ICWSI.1990.63898","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63898","url":null,"abstract":"A visually oriented fault simulation environment for WSI architectures based on behavioral simulation of parallel message passing processors and switch-level fault simulation of selected processors is described. The environment was implemented by interfacing the CHAMP switch-level simulator with the OODRA behavioral simulator. The simulation environment was used to measure the fault coverage for a digital adaptive beamforming architecture with a synthetic workload. Fault coverage variation with input set size and array location was investigated. The rate at which faults produce errors in the architecture was also measured.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124146064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63917
J. F. Mcdonald, S. Dabral, R. Philhower, M.E. Russinovich
Wafer scale integration of memories by row and column repair follows a well established path developed in industry for the repair of large DRAM's. Rows and columns in these memories can be diagnosed and those found faulty can be replaced by spares. If the entire wafer of dies can be fully repaired then all the cells on the wafer may be interconnected using artwork for chip to chip wiring which is the same on all wafers. What one would like is a similar approach which could be applied to logic circuits. Traditionally, however, logic is viewed as being inherently less regular than memory. This paper addresses one approach to accomplishing WSI based on a highly regular, restructurable logic component known as Programmable Gate Array (PGA), which is also known as a Logic Component Array (LCA).<>
{"title":"Wafer scale integration (WSI) of programmable gate arrays (PGA's)","authors":"J. F. Mcdonald, S. Dabral, R. Philhower, M.E. Russinovich","doi":"10.1109/ICWSI.1990.63917","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63917","url":null,"abstract":"Wafer scale integration of memories by row and column repair follows a well established path developed in industry for the repair of large DRAM's. Rows and columns in these memories can be diagnosed and those found faulty can be replaced by spares. If the entire wafer of dies can be fully repaired then all the cells on the wafer may be interconnected using artwork for chip to chip wiring which is the same on all wafers. What one would like is a similar approach which could be applied to logic circuits. Traditionally, however, logic is viewed as being inherently less regular than memory. This paper addresses one approach to accomplishing WSI based on a highly regular, restructurable logic component known as Programmable Gate Array (PGA), which is also known as a Logic Component Array (LCA).<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133216359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63913
H.-D. Hartmann, T. Hillmann-Ruge
Nd:YAG laser processing of vertical links and cutting of interconnections in both metallization levels have been investigated. Main emphasis was on examination of the statistics of laser processing and the reliability of the processed antifuses. For this purpose, a special test chip has been designed and fabricated in a standard double level CMOS process. Laser cutting of interconnections is possible with one pulse in both metallization levels without passivation opening. For laser linking with the pulsed Nd:YAG, simply expanded interconnections turned out to be best suitable. Structures which are passivated prior to laser processing showed a significantly higher yield than depassivated combined with improved reproducibility of laser processing. Best yield of 99.4% with contact resistances <0.3 Omega has been achieved with expansions of 20*20 mu m/sup 2/. However, expansions of 14*14 mu m/sup 2/ are the best choice as yield is only slightly below that of the larger structures and consumption of area is much less. Accelerated life time tests with current densities up to 1*10/sup 6/ A/cm/sup 2/ and temperatures up to 270 degrees C were carried out. Materials were analysed with EDX, AES, and SIMS.<>
{"title":"Investigations of Nd:YAG laser formed connections and disconnections of standard CMOS double level metallizations","authors":"H.-D. Hartmann, T. Hillmann-Ruge","doi":"10.1109/ICWSI.1990.63913","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63913","url":null,"abstract":"Nd:YAG laser processing of vertical links and cutting of interconnections in both metallization levels have been investigated. Main emphasis was on examination of the statistics of laser processing and the reliability of the processed antifuses. For this purpose, a special test chip has been designed and fabricated in a standard double level CMOS process. Laser cutting of interconnections is possible with one pulse in both metallization levels without passivation opening. For laser linking with the pulsed Nd:YAG, simply expanded interconnections turned out to be best suitable. Structures which are passivated prior to laser processing showed a significantly higher yield than depassivated combined with improved reproducibility of laser processing. Best yield of 99.4% with contact resistances <0.3 Omega has been achieved with expansions of 20*20 mu m/sup 2/. However, expansions of 14*14 mu m/sup 2/ are the best choice as yield is only slightly below that of the larger structures and consumption of area is much less. Accelerated life time tests with current densities up to 1*10/sup 6/ A/cm/sup 2/ and temperatures up to 270 degrees C were carried out. Materials were analysed with EDX, AES, and SIMS.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121927395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-01-23DOI: 10.1109/ICWSI.1990.63880
R. Lea
The new decade (1990-2000) heralds the age of very powerful compute-, graphics- and information-servers, based on Massively Parallel Processors (mppS), capable of TOPS (Tera Operations-Per-Second) performance in networked scientific, engineering, knowledge-base and artificial intelligence applications. This paper describes a WSI associative string processor (WASP) in CMOS fault-tolerant WSI MPP architecture which satisfies both the architectural and engineering requirements outlined and, thereby, offers a step-function improvement in cost-effectiveness compared with first-generation MPPs.<>
{"title":"WASP: a wafer-scale massively parallel processor","authors":"R. Lea","doi":"10.1109/ICWSI.1990.63880","DOIUrl":"https://doi.org/10.1109/ICWSI.1990.63880","url":null,"abstract":"The new decade (1990-2000) heralds the age of very powerful compute-, graphics- and information-servers, based on Massively Parallel Processors (mppS), capable of TOPS (Tera Operations-Per-Second) performance in networked scientific, engineering, knowledge-base and artificial intelligence applications. This paper describes a WSI associative string processor (WASP) in CMOS fault-tolerant WSI MPP architecture which satisfies both the architectural and engineering requirements outlined and, thereby, offers a step-function improvement in cost-effectiveness compared with first-generation MPPs.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117083136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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