Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634044
R. Gravrok, A. Byers, M. Piket-May
This paper presents a novel method for calculating the lumped inductance of a 3D distributed system. The inductance of a complex power distribution structure is extracted using a system level approach. The method is validated against theoretical solutions.
{"title":"Numerical modeling of inductance for a distributed system","authors":"R. Gravrok, A. Byers, M. Piket-May","doi":"10.1109/EPEP.1997.634044","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634044","url":null,"abstract":"This paper presents a novel method for calculating the lumped inductance of a 3D distributed system. The inductance of a complex power distribution structure is extracted using a system level approach. The method is validated against theoretical solutions.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"12088 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124563267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634056
Jin Zhao, J. Fang
The investigation on the relative significance of electromagnetic coupling between vias and parallel traces is presented in this paper. This study shows that the coupling between vias can often be stronger than the coupling between traces and is therefore not negligible in signal integrity analysis of high-speed electronic packages.
{"title":"Significance of electromagnetic coupling through vias in electronics packaging","authors":"Jin Zhao, J. Fang","doi":"10.1109/EPEP.1997.634056","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634056","url":null,"abstract":"The investigation on the relative significance of electromagnetic coupling between vias and parallel traces is presented in this paper. This study shows that the coupling between vias can often be stronger than the coupling between traces and is therefore not negligible in signal integrity analysis of high-speed electronic packages.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132506333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634042
A. Owzar, C. Weickhmann, F. Fazelpour, P. Windirsch, J. Reimers, H. Reichl
One of the main limitations for the application of the MCM approach is the factor of costs. This problem can be solved by using low cost PCB substrate material. It must be assured, that PCB materials can meet the demands on the interconnection parameter for MCM wiring systems. It is shown by measurement results, that the line impedance is in the required range for MCM application. However, the increase in wiring integration can be a handicap regarding the coupling factor.
{"title":"High frequency characterization of interconnection on glass fiber inforced PCB (G30)","authors":"A. Owzar, C. Weickhmann, F. Fazelpour, P. Windirsch, J. Reimers, H. Reichl","doi":"10.1109/EPEP.1997.634042","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634042","url":null,"abstract":"One of the main limitations for the application of the MCM approach is the factor of costs. This problem can be solved by using low cost PCB substrate material. It must be assured, that PCB materials can meet the demands on the interconnection parameter for MCM wiring systems. It is shown by measurement results, that the line impedance is in the required range for MCM application. However, the increase in wiring integration can be a handicap regarding the coupling factor.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129805386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634049
M. Trivedi, K. Shenai
This paper reports the use of two-dimensional numerical simulations in modeling the effects of packaging on the electrical performance of high-power modules. Non-isothermal simulations are performed to study the performance and failure of IGBTs under short-circuit and clamped inductive switching stress.
{"title":"Characterization, modeling and optimization of high power module packaging","authors":"M. Trivedi, K. Shenai","doi":"10.1109/EPEP.1997.634049","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634049","url":null,"abstract":"This paper reports the use of two-dimensional numerical simulations in modeling the effects of packaging on the electrical performance of high-power modules. Non-isothermal simulations are performed to study the performance and failure of IGBTs under short-circuit and clamped inductive switching stress.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"404 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115997409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634025
G. Katopis, W. Becker
The S/390 architecture lends itself to an MCM package solution that provides the best performance at the lowest cost for the maximum SMP system. In this paper we develop a cost performance criterion that can be used to evaluate several MCM structures and materials. The results of this comparison show that a Glass Ceramic based MCM is cost performance equivalent to a polyimide thin film based MCM for off chip bus speeds up to 250 MHz. At this range of frequency this work shows that an Alumina MCM implementation has 17% less cost performance. In addition, the trend curves shown in this study indicate that polyimide thin film MCM structures will be the best cost performers in future systems where the off chip bus speeds exceed 250 MHz.
{"title":"S/390 cost performance considerations for packaging choices","authors":"G. Katopis, W. Becker","doi":"10.1109/EPEP.1997.634025","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634025","url":null,"abstract":"The S/390 architecture lends itself to an MCM package solution that provides the best performance at the lowest cost for the maximum SMP system. In this paper we develop a cost performance criterion that can be used to evaluate several MCM structures and materials. The results of this comparison show that a Glass Ceramic based MCM is cost performance equivalent to a polyimide thin film based MCM for off chip bus speeds up to 250 MHz. At this range of frequency this work shows that an Alumina MCM implementation has 17% less cost performance. In addition, the trend curves shown in this study indicate that polyimide thin film MCM structures will be the best cost performers in future systems where the off chip bus speeds exceed 250 MHz.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130227535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634024
Y. Low, R. Frye, K. O'Connor
We describe a design methodology for several chip-on-chip applications that uses a single redistribution metal layer on each chip and solder bumps as vias to form a two-level routing system.
{"title":"Design methodology for chip-on-chip applications","authors":"Y. Low, R. Frye, K. O'Connor","doi":"10.1109/EPEP.1997.634024","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634024","url":null,"abstract":"We describe a design methodology for several chip-on-chip applications that uses a single redistribution metal layer on each chip and solder bumps as vias to form a two-level routing system.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122576532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634079
J.-R. Li, J. White
Method-of-Moments (MoM) based 3-D electromagnetic analysis programs typically generate dense systems of equations which are extremely expensive to solve. In the last several years, very fast MoM solvers have been developed by sparsifying the dense system using a hierarchy of multipole expansions or grid projection plus the fast Fourier transform. The hierarchical multipole algorithms represented clusters of source distributions with an expansion in the center of the cluster, where as grid projection algorithms represent clusters using grid-locked point sources. In this paper we consider how to improve the efficiency of either algorithm by using grid-locked multipole expansions to represent clusters of sources.
{"title":"Improving the efficiency of multipole-accelerated method-of-moments solvers using dual grid multipole expansions","authors":"J.-R. Li, J. White","doi":"10.1109/EPEP.1997.634079","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634079","url":null,"abstract":"Method-of-Moments (MoM) based 3-D electromagnetic analysis programs typically generate dense systems of equations which are extremely expensive to solve. In the last several years, very fast MoM solvers have been developed by sparsifying the dense system using a hierarchy of multipole expansions or grid projection plus the fast Fourier transform. The hierarchical multipole algorithms represented clusters of source distributions with an expansion in the center of the cluster, where as grid projection algorithms represent clusters using grid-locked point sources. In this paper we consider how to improve the efficiency of either algorithm by using grid-locked multipole expansions to represent clusters of sources.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"19 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116801346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634030
M. Cases, B. Singh, H. Smith
A methodology which controls induced di/dt noise for high performance chip designs is described. Delta-I modeling and analysis for the chip, module and card is used to define a strategy and effectiveness of various decoupling schemes over a broad frequency range.
{"title":"Delta-I noise avoidance methodology for high performance chip designs [CMOS microprocessors]","authors":"M. Cases, B. Singh, H. Smith","doi":"10.1109/EPEP.1997.634030","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634030","url":null,"abstract":"A methodology which controls induced di/dt noise for high performance chip designs is described. Delta-I modeling and analysis for the chip, module and card is used to define a strategy and effectiveness of various decoupling schemes over a broad frequency range.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115100504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634034
E. A. Dengi, R. Rohrer
Summary form only given. On-chip interconnect must be accounted for at all levels of the design hierarchy, starting with synthesis, through physical design and ending with verification. Each level of the design hierarchy brings its unique challenge to interconnect modeling. Decisions made at the synthesis level have the greatest influence on the final interconnect design, yet one must deal with the uncertainty of having no physical design at this stage. During physical design, the uncertainty gradually decreases as the layout takes shape while the accuracy requirements on the interconnect models become more demanding. At the post-layout verification stage, there are no physical uncertainties. However for final verification, the fact that interconnect plays a dominant role in all performance parameters of the design, i.e., power, system delay, area and signal integrity, necessitates the use of extremely accurate interconnect models. This paper focuses on on-chip interconnect modeling technologies for post-layout verification (often called "parasitic extraction") and characterization/silicon-correlation which is essential to interconnect modeling at all levels. The state-of-the-art in "parasitic extraction" is reviewed and strengths and shortcomings are discussed. The need for establishing correlation with silicon is emphasized. Various popular measures of accuracy are scrutinized and the concept of accuracy in performance variables is introduced. Finally, the impact of interconnect modeling error on performance and signal integrity verification is discussed.
{"title":"On-chip interconnect modeling technologies","authors":"E. A. Dengi, R. Rohrer","doi":"10.1109/EPEP.1997.634034","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634034","url":null,"abstract":"Summary form only given. On-chip interconnect must be accounted for at all levels of the design hierarchy, starting with synthesis, through physical design and ending with verification. Each level of the design hierarchy brings its unique challenge to interconnect modeling. Decisions made at the synthesis level have the greatest influence on the final interconnect design, yet one must deal with the uncertainty of having no physical design at this stage. During physical design, the uncertainty gradually decreases as the layout takes shape while the accuracy requirements on the interconnect models become more demanding. At the post-layout verification stage, there are no physical uncertainties. However for final verification, the fact that interconnect plays a dominant role in all performance parameters of the design, i.e., power, system delay, area and signal integrity, necessitates the use of extremely accurate interconnect models. This paper focuses on on-chip interconnect modeling technologies for post-layout verification (often called \"parasitic extraction\") and characterization/silicon-correlation which is essential to interconnect modeling at all levels. The state-of-the-art in \"parasitic extraction\" is reviewed and strengths and shortcomings are discussed. The need for establishing correlation with silicon is emphasized. Various popular measures of accuracy are scrutinized and the concept of accuracy in performance variables is introduced. Finally, the impact of interconnect modeling error on performance and signal integrity verification is discussed.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126221629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634062
S. Sercu, L. Martens
In this paper a technique is described for the measurement of the correct S-parameters of an N-port package or interconnection using a 2-port network analyzer with 50 /spl Omega/ system impedance and N imperfect terminations. The technique is fully general and can be applied using arbitrary terminations. Broadband 50 n loads are not required. The method is illustrated on a coupled microstrip line structure.
{"title":"Characterizing N-port packages and interconnections with a 2-port network analyzer","authors":"S. Sercu, L. Martens","doi":"10.1109/EPEP.1997.634062","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634062","url":null,"abstract":"In this paper a technique is described for the measurement of the correct S-parameters of an N-port package or interconnection using a 2-port network analyzer with 50 /spl Omega/ system impedance and N imperfect terminations. The technique is fully general and can be applied using arbitrary terminations. Broadband 50 n loads are not required. The method is illustrated on a coupled microstrip line structure.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121753880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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