Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634034
E. A. Dengi, R. Rohrer
Summary form only given. On-chip interconnect must be accounted for at all levels of the design hierarchy, starting with synthesis, through physical design and ending with verification. Each level of the design hierarchy brings its unique challenge to interconnect modeling. Decisions made at the synthesis level have the greatest influence on the final interconnect design, yet one must deal with the uncertainty of having no physical design at this stage. During physical design, the uncertainty gradually decreases as the layout takes shape while the accuracy requirements on the interconnect models become more demanding. At the post-layout verification stage, there are no physical uncertainties. However for final verification, the fact that interconnect plays a dominant role in all performance parameters of the design, i.e., power, system delay, area and signal integrity, necessitates the use of extremely accurate interconnect models. This paper focuses on on-chip interconnect modeling technologies for post-layout verification (often called "parasitic extraction") and characterization/silicon-correlation which is essential to interconnect modeling at all levels. The state-of-the-art in "parasitic extraction" is reviewed and strengths and shortcomings are discussed. The need for establishing correlation with silicon is emphasized. Various popular measures of accuracy are scrutinized and the concept of accuracy in performance variables is introduced. Finally, the impact of interconnect modeling error on performance and signal integrity verification is discussed.
{"title":"On-chip interconnect modeling technologies","authors":"E. A. Dengi, R. Rohrer","doi":"10.1109/EPEP.1997.634034","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634034","url":null,"abstract":"Summary form only given. On-chip interconnect must be accounted for at all levels of the design hierarchy, starting with synthesis, through physical design and ending with verification. Each level of the design hierarchy brings its unique challenge to interconnect modeling. Decisions made at the synthesis level have the greatest influence on the final interconnect design, yet one must deal with the uncertainty of having no physical design at this stage. During physical design, the uncertainty gradually decreases as the layout takes shape while the accuracy requirements on the interconnect models become more demanding. At the post-layout verification stage, there are no physical uncertainties. However for final verification, the fact that interconnect plays a dominant role in all performance parameters of the design, i.e., power, system delay, area and signal integrity, necessitates the use of extremely accurate interconnect models. This paper focuses on on-chip interconnect modeling technologies for post-layout verification (often called \"parasitic extraction\") and characterization/silicon-correlation which is essential to interconnect modeling at all levels. The state-of-the-art in \"parasitic extraction\" is reviewed and strengths and shortcomings are discussed. The need for establishing correlation with silicon is emphasized. Various popular measures of accuracy are scrutinized and the concept of accuracy in performance variables is introduced. Finally, the impact of interconnect modeling error on performance and signal integrity verification is discussed.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126221629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634036
S. Oh, K. Okasaki, J. Moll, O. S. Nakagawa, N. Chang
A 3D Global Interconnect Parameter ExtractoR (GIPER) has been developed to provide a practical extraction tool for the full-chip global critical path analysis. It extracts the interconnect parameters (R,C) of a typical global interconnect within several minutes per net on a HP 9000/755 workstation within 5% accuracy compared to full 3D numerical simulations.
{"title":"3D Global Interconnect Parameter ExtractoR for full-chip global critical path analysis","authors":"S. Oh, K. Okasaki, J. Moll, O. S. Nakagawa, N. Chang","doi":"10.1109/EPEP.1997.634036","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634036","url":null,"abstract":"A 3D Global Interconnect Parameter ExtractoR (GIPER) has been developed to provide a practical extraction tool for the full-chip global critical path analysis. It extracts the interconnect parameters (R,C) of a typical global interconnect within several minutes per net on a HP 9000/755 workstation within 5% accuracy compared to full 3D numerical simulations.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129533127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634038
B. Biswas, A. Glasser, S. Lipa, M. Steer, P. Franzon, D. Griffis, P. Russell
This paper describes the transmission line and capacitance measurements made on a 0.25 micron test chip. Transmission lines were characterized to frequencies up to 20 GHz using a Hewlett Packard network analyzer and capacitances were determined using conventional capacitance meter. These measurements will help to develop benchmark capacitance and resistance values of on-chip interconnect structures. Measurements of the physical dimension of the interconnect structures will facilitate the determination of the effects of geometric assumptions made by capacitance extraction tools.
{"title":"Experimental electrical characterization of on-chip interconnects","authors":"B. Biswas, A. Glasser, S. Lipa, M. Steer, P. Franzon, D. Griffis, P. Russell","doi":"10.1109/EPEP.1997.634038","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634038","url":null,"abstract":"This paper describes the transmission line and capacitance measurements made on a 0.25 micron test chip. Transmission lines were characterized to frequencies up to 20 GHz using a Hewlett Packard network analyzer and capacitances were determined using conventional capacitance meter. These measurements will help to develop benchmark capacitance and resistance values of on-chip interconnect structures. Measurements of the physical dimension of the interconnect structures will facilitate the determination of the effects of geometric assumptions made by capacitance extraction tools.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130881494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634058
P. Nordholz, H. Grabinski
A new approach for the time-domain analysis of transmission lines exposed to arbitrary external fields is presented. The approach is robust enough to make it compatible with virtually any line model and circuit simulator. The deviation between exact values and simulation results is less than 1%.
{"title":"Modelling and simulation of electromagnetic interference in electronic circuits","authors":"P. Nordholz, H. Grabinski","doi":"10.1109/EPEP.1997.634058","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634058","url":null,"abstract":"A new approach for the time-domain analysis of transmission lines exposed to arbitrary external fields is presented. The approach is robust enough to make it compatible with virtually any line model and circuit simulator. The deviation between exact values and simulation results is less than 1%.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130905640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634075
H. Cebi, K. Gupta
A network modeling approach is used to estimate the effect of package resonance on performance of microstrip circuits. An example of two-stage MESFET amplifier illustrates the methodology developed.
{"title":"A method for evaluating effect of package resonances on circuit performance [microstrip circuits]","authors":"H. Cebi, K. Gupta","doi":"10.1109/EPEP.1997.634075","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634075","url":null,"abstract":"A network modeling approach is used to estimate the effect of package resonance on performance of microstrip circuits. An example of two-stage MESFET amplifier illustrates the methodology developed.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121100804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634068
P. Petre, G. Valley, R. T. Kihm, S. Gedney
A new fast method of moments code is used to predict the performance and calculate the electromagnetic properties of packaged, dense, planar microwave circuits. It is demonstrated that circuits as large as transmit/receive (T/R) modules that cannot be simulated accurately with commercial tools can be modeled with this method.
{"title":"Simulation of large packaged dense microwave circuits","authors":"P. Petre, G. Valley, R. T. Kihm, S. Gedney","doi":"10.1109/EPEP.1997.634068","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634068","url":null,"abstract":"A new fast method of moments code is used to predict the performance and calculate the electromagnetic properties of packaged, dense, planar microwave circuits. It is demonstrated that circuits as large as transmit/receive (T/R) modules that cannot be simulated accurately with commercial tools can be modeled with this method.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129218568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634082
E. Chiprout, T. Nguyen
An overview of the recent advances in model reduction techniques of linear interconnect and packaging models for the purpose of simulation is given. The importance of different methods for accuracy, stability and generality are highlighted.
{"title":"Survey of model reduction techniques for analysis of package and interconnect models of high-speed designs","authors":"E. Chiprout, T. Nguyen","doi":"10.1109/EPEP.1997.634082","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634082","url":null,"abstract":"An overview of the recent advances in model reduction techniques of linear interconnect and packaging models for the purpose of simulation is given. The importance of different methods for accuracy, stability and generality are highlighted.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115030363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-01DOI: 10.1109/EPEP.1997.634076
D.F. Williams, M. Janezic, A. Ralston, R. S. List
This paper compares a simple quasi-TEM model for coplanar waveguide fabricated on moderately doped silicon substrates to measurement. While the coplanar waveguide currents and magnetic fields are unaffected by the substrate, a simple capacitive model can accurately account for the effects of the substrate.
{"title":"Quasi-TEM model for coplanar waveguide on silicon","authors":"D.F. Williams, M. Janezic, A. Ralston, R. S. List","doi":"10.1109/EPEP.1997.634076","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634076","url":null,"abstract":"This paper compares a simple quasi-TEM model for coplanar waveguide fabricated on moderately doped silicon substrates to measurement. While the coplanar waveguide currents and magnetic fields are unaffected by the substrate, a simple capacitive model can accurately account for the effects of the substrate.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132433816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EPEP.1997.634081
V. Veremey, R. Mittra
A finite difference (FD) method for rapid and accurate evaluation of capacitance matrices of interconnect configurations is described. Novel techniques for the truncation of FD mesh, that significantly reduce the CPU time, are presented.
{"title":"A technique for fast calculations of capacitance matrices of interconnect structures","authors":"V. Veremey, R. Mittra","doi":"10.1109/EPEP.1997.634081","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634081","url":null,"abstract":"A finite difference (FD) method for rapid and accurate evaluation of capacitance matrices of interconnect configurations is described. Novel techniques for the truncation of FD mesh, that significantly reduce the CPU time, are presented.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121059899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EPEP.1997.634077
A. Baghai-Wadji
Summary form only given. The characterisation and design of microwave packaging, and the need for predicting the radiation directivity and interference pattern of novel interconnect structures, and also the necessity for validating simpler models, all require rigorous numerical methods and fast algorithms which allow parallel computing. To this end integral- rather than differential-formulations seem to be advantageous. The various formulations of integral equations in computational electromagnetics involve volume and surface integrals, which, generally, have to be solved numerically. For nearly three decades Harrington's method of moments (MoMs) has been successfully used to discretize these integrals and to obtain reliable approximations to the field solutions. However, MoM has three drawbacks: (1) The resulting (frequency-dependent impedance) matrices are dense. (2) The interaction coefficients (nondiagonal matrix elements) are Fourier-type integrals, and their numerical calculation is comparatively time consuming. (3) The selfaction coefficients (diagonal matrix elements) are Fourier-type singular integrals, and have to be evaluated carefully in Cauchy's sense (Hadamard's finite part). The author's recent efforts to remove these drawbacks have led to the fast-MoM. In many applications fast-MoM eliminates the difficulties in (2) and (3), and if combined with the wavelet analysis relaxes the drawback in (1). In this review the author first briefly points out useful features of the wavelet theory, and emphasizes the role of iterative techniques for solving large matrix equations. He then focuses on the problems in (2) and (3).
{"title":"An introduction to the fast-MoM in computational electromagnetics","authors":"A. Baghai-Wadji","doi":"10.1109/EPEP.1997.634077","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634077","url":null,"abstract":"Summary form only given. The characterisation and design of microwave packaging, and the need for predicting the radiation directivity and interference pattern of novel interconnect structures, and also the necessity for validating simpler models, all require rigorous numerical methods and fast algorithms which allow parallel computing. To this end integral- rather than differential-formulations seem to be advantageous. The various formulations of integral equations in computational electromagnetics involve volume and surface integrals, which, generally, have to be solved numerically. For nearly three decades Harrington's method of moments (MoMs) has been successfully used to discretize these integrals and to obtain reliable approximations to the field solutions. However, MoM has three drawbacks: (1) The resulting (frequency-dependent impedance) matrices are dense. (2) The interaction coefficients (nondiagonal matrix elements) are Fourier-type integrals, and their numerical calculation is comparatively time consuming. (3) The selfaction coefficients (diagonal matrix elements) are Fourier-type singular integrals, and have to be evaluated carefully in Cauchy's sense (Hadamard's finite part). The author's recent efforts to remove these drawbacks have led to the fast-MoM. In many applications fast-MoM eliminates the difficulties in (2) and (3), and if combined with the wavelet analysis relaxes the drawback in (1). In this review the author first briefly points out useful features of the wavelet theory, and emphasizes the role of iterative techniques for solving large matrix equations. He then focuses on the problems in (2) and (3).","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134446374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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