Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634027
S. Yamaguchi, T. Hayashi, Y. Ohno, T. Mikazuki
This paper describes an innovative high-speed optical backboard bus composed of an optical star coupler, optical-transmitter (E/O) modules, optical-receiver (O/E) modules, and optical multimode glass fibers. A highly efficient optical coupling structure with an aspherical lens and a laser diode was designed to achieve coupling efficiency of up to 90%, enabling the distribution of optical signals at up to 1 Gb/s to 32 functional boards. Embedded optical fibers in the printed circuit board are used to achieve precise control of the optical propagation delay time, and permit a high packaging density. E/O and O/E modules are placed with a pitch of about 15 mm. We developed small laser diode and photo diode modules suitable for optical coupling to the end of embedded fibers through the use of an alignment tool. A fabricated 8/spl times/8 prototype optical backboard bus was able to distribute high-speed optical signals of up to 1 Gb/s to function boards with a high packaging density.
{"title":"Large-scale optical backboard bus","authors":"S. Yamaguchi, T. Hayashi, Y. Ohno, T. Mikazuki","doi":"10.1109/EPEP.1997.634027","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634027","url":null,"abstract":"This paper describes an innovative high-speed optical backboard bus composed of an optical star coupler, optical-transmitter (E/O) modules, optical-receiver (O/E) modules, and optical multimode glass fibers. A highly efficient optical coupling structure with an aspherical lens and a laser diode was designed to achieve coupling efficiency of up to 90%, enabling the distribution of optical signals at up to 1 Gb/s to 32 functional boards. Embedded optical fibers in the printed circuit board are used to achieve precise control of the optical propagation delay time, and permit a high packaging density. E/O and O/E modules are placed with a pitch of about 15 mm. We developed small laser diode and photo diode modules suitable for optical coupling to the end of embedded fibers through the use of an alignment tool. A fabricated 8/spl times/8 prototype optical backboard bus was able to distribute high-speed optical signals of up to 1 Gb/s to function boards with a high packaging density.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125601806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634029
D. Herrell, B. Beker
This paper addresses the relationship of power transient design with the EMI characteristics of high-performance microprocessors. After a brief review of EMI and its role in modern PC systems, a modeling approach for a complete CPGA package is discussed. The model includes on-chip and on-package decoupling capacitors, multiple power and ground planes for core voltages, C4 bumps, inter-planar vias, and pins. Equivalent SPICE circuit for the chip-package combination is obtained and the results for power transients and frequency domain transfer characteristics are given.
{"title":"EMI and power delivery design in PC systems","authors":"D. Herrell, B. Beker","doi":"10.1109/EPEP.1997.634029","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634029","url":null,"abstract":"This paper addresses the relationship of power transient design with the EMI characteristics of high-performance microprocessors. After a brief review of EMI and its role in modern PC systems, a modeling approach for a complete CPGA package is discussed. The model includes on-chip and on-package decoupling capacitors, multiple power and ground planes for core voltages, C4 bumps, inter-planar vias, and pins. Equivalent SPICE circuit for the chip-package combination is obtained and the results for power transients and frequency domain transfer characteristics are given.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116607073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634084
M. Kamon, N. Marques, L. M. Silveira, Jacob K. White
In the past, model order reduction techniques have been successfully employed for 3-D PEEC (Partial Element Equivalent Circuit) interconnect models. This paper explores the difficulties in generating low order models when PEEC-like models include volume filaments to accurately capture skin and proximity effects.
{"title":"Generating reduced order models via PEEC for capturing skin and proximity effects","authors":"M. Kamon, N. Marques, L. M. Silveira, Jacob K. White","doi":"10.1109/EPEP.1997.634084","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634084","url":null,"abstract":"In the past, model order reduction techniques have been successfully employed for 3-D PEEC (Partial Element Equivalent Circuit) interconnect models. This paper explores the difficulties in generating low order models when PEEC-like models include volume filaments to accurately capture skin and proximity effects.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125141443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634052
Zhonghua Wu, O. Siguenza
Electrical characterization of flip-chip redistribution layer and detailed study of the associated ohmic drop, simultaneous switching output (SSO) noise and crosstalk are presented. Noise margins are analyzed and design rules are generated based on the simulation.
{"title":"Flip-chip redistribution layer electrical characterization and SSO noise simulation","authors":"Zhonghua Wu, O. Siguenza","doi":"10.1109/EPEP.1997.634052","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634052","url":null,"abstract":"Electrical characterization of flip-chip redistribution layer and detailed study of the associated ohmic drop, simultaneous switching output (SSO) noise and crosstalk are presented. Noise margins are analyzed and design rules are generated based on the simulation.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122653983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634063
A. Tripathi, V. Tripathi
An algorithm to extract the normal mode parameters of uniformly coupled lines in an inhomogeneous medium is developed. The sufficiency of the measured multiport time domain reflection coefficient matrix elements in extracting all the normal mode parameters is exemplified with the example of typical coupled lines system.
{"title":"Characterization of multiconductor inhomogeneous uniformly coupled lines from TDR data","authors":"A. Tripathi, V. Tripathi","doi":"10.1109/EPEP.1997.634063","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634063","url":null,"abstract":"An algorithm to extract the normal mode parameters of uniformly coupled lines in an inhomogeneous medium is developed. The sufficiency of the measured multiport time domain reflection coefficient matrix elements in extracting all the normal mode parameters is exemplified with the example of typical coupled lines system.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122896232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634039
H.H. Chen
This paper describes the use of a 12/spl times/12 SCM power supply distribution model, a 50/spl times/50 on-chip power bus model, and a distributed switching circuit model to analyze the on-chip power supply noise for high-performance VLSI design. The integrated model provides a complete analysis of the Vdd distribution, and allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise.
{"title":"A hierarchical power supply distribution model for full-chip switching noise analysis","authors":"H.H. Chen","doi":"10.1109/EPEP.1997.634039","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634039","url":null,"abstract":"This paper describes the use of a 12/spl times/12 SCM power supply distribution model, a 50/spl times/50 on-chip power bus model, and a distributed switching circuit model to analyze the on-chip power supply noise for high-performance VLSI design. The integrated model provides a complete analysis of the Vdd distribution, and allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115120248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634064
R. Lutz, A. Tripathi, V. K. Tripathi, T. Arabi
Calibration and de-embedding techniques for time domain measurements associated with high speed off chip digital interconnects are presented. The techniques are demonstrated by measurements of skew, signal degradation, and crosstalk associated with typical interconnects in multilayered boards.
{"title":"Accurate characterization of board level interconnects for high performance systems","authors":"R. Lutz, A. Tripathi, V. K. Tripathi, T. Arabi","doi":"10.1109/EPEP.1997.634064","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634064","url":null,"abstract":"Calibration and de-embedding techniques for time domain measurements associated with high speed off chip digital interconnects are presented. The techniques are demonstrated by measurements of skew, signal degradation, and crosstalk associated with typical interconnects in multilayered boards.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123698636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634078
D. Heckmann, S. Dvorak, A. Cangellaris
In this paper, a closed-form solution is presented for the individual elements of the impedance matrix generated by the application of the Method of Moments to the integral equation solution of shielded multiconductor structures. Using these expressions, impedance matrix fill time is reduced by one to four orders of magnitude.
{"title":"Rapid electromagnetic analysis of multilayer interconnects","authors":"D. Heckmann, S. Dvorak, A. Cangellaris","doi":"10.1109/EPEP.1997.634078","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634078","url":null,"abstract":"In this paper, a closed-form solution is presented for the individual elements of the impedance matrix generated by the application of the Method of Moments to the integral equation solution of shielded multiconductor structures. Using these expressions, impedance matrix fill time is reduced by one to four orders of magnitude.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125870863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634035
Ching-Chao Huang, K. S. Oh, Shunxi Wang, S. Panchapakesan
The rule-based layout parameter extraction (LPE) tools are most often used to extract the full-chip parasitics, but their accuracy strongly depends on how the capacitance models are specified. This paper shows that the generation of accurate capacitance models can be automated with thousands of field-solver simulations and nonlinear regression. The fundamental limitations of LPE tools are discussed. Finally, a 3D Monte-Carlo field solver is used to validate and further improve the LPE results.
{"title":"Improving the accuracy of on-chip parasitic extraction","authors":"Ching-Chao Huang, K. S. Oh, Shunxi Wang, S. Panchapakesan","doi":"10.1109/EPEP.1997.634035","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634035","url":null,"abstract":"The rule-based layout parameter extraction (LPE) tools are most often used to extract the full-chip parasitics, but their accuracy strongly depends on how the capacitance models are specified. This paper shows that the generation of accurate capacitance models can be automated with thousands of field-solver simulations and nonlinear regression. The fundamental limitations of LPE tools are discussed. Finally, a 3D Monte-Carlo field solver is used to validate and further improve the LPE results.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128388605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-27DOI: 10.1109/EPEP.1997.634061
J. Balbastre, M. Bort, L. Nuño
The generalised circuit analysis (GCA), together with the finite element method (FEM), has been used to study the coupling phenomena arising in transmission line structures inside slotted envelopes. The proposed approach is very systematic and versatile.
{"title":"Study of coupling phenomena in transmission line structures covered by slotted screens using the generalised circuit analysis","authors":"J. Balbastre, M. Bort, L. Nuño","doi":"10.1109/EPEP.1997.634061","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634061","url":null,"abstract":"The generalised circuit analysis (GCA), together with the finite element method (FEM), has been used to study the coupling phenomena arising in transmission line structures inside slotted envelopes. The proposed approach is very systematic and versatile.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123794978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：