There are economic advantages to time-sharing a facility with hybrid resources. It is quite unlikely that any single hybrid problem will be able to utilize all of the system resources 100 percent of the time. This is the same kind of reasoning that leads one to consider time-sharing for conventional digital problems. However, time synchronous real-time hybrid time-sharing and non-synchronous non-real-time digital timesharing are quite different problems, with the former posing some considerable difficulty to sequential digital machines.
{"title":"A time shared I/O processor for realtime hybrid computation","authors":"T. Strollo, R. Tomlinson, E. Fiala","doi":"10.1145/1478559.1478653","DOIUrl":"https://doi.org/10.1145/1478559.1478653","url":null,"abstract":"There are economic advantages to time-sharing a facility with hybrid resources. It is quite unlikely that any single hybrid problem will be able to utilize all of the system resources 100 percent of the time. This is the same kind of reasoning that leads one to consider time-sharing for conventional digital problems. However, time synchronous real-time hybrid time-sharing and non-synchronous non-real-time digital timesharing are quite different problems, with the former posing some considerable difficulty to sequential digital machines.","PeriodicalId":230827,"journal":{"name":"AFIPS '69 (Fall)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1969-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117105380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thomas W. Hart, Durrell W. Hillis, J. Marley, R. C. Lutz, C. R. Hoffman
It has been obvious for several years that Large Scale Integration could be applied to memories. Memories offer several advantages in that a large volume of one type of device can be manufactured, and that the design can be optimized for one application. There exists a wide spectrum of memory product areas with varying size, costs, speed and enviromental performance. Most of these application areas are presently serviced by various forms of magnetic storage.
{"title":"A main frame semiconductor memory for fourth generation computers","authors":"Thomas W. Hart, Durrell W. Hillis, J. Marley, R. C. Lutz, C. R. Hoffman","doi":"10.1145/1478559.1478616","DOIUrl":"https://doi.org/10.1145/1478559.1478616","url":null,"abstract":"It has been obvious for several years that Large Scale Integration could be applied to memories. Memories offer several advantages in that a large volume of one type of device can be manufactured, and that the design can be optimized for one application. There exists a wide spectrum of memory product areas with varying size, costs, speed and enviromental performance. Most of these application areas are presently serviced by various forms of magnetic storage.","PeriodicalId":230827,"journal":{"name":"AFIPS '69 (Fall)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1969-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134426098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a set of augmentations to the language BEAST (Brookings Economics and Statistical Translator) as part of a continuing effort to define a language for a particular group of computer users, social scientists. In this nebulous group we include professional economists, political scientists, psychologists, sociologists, and a large number of university students in those disciplines. An important assumption underlying our work has been that the cost of not having substantially better software than presently exists is very large and should be measured in terms of researchers' time. The true cost of inappropriate methods of computer utilization should not be measured by staff and computer costs, but by the social cost of the output foregone. When answers to questions of importance for national public policy formation require weeks, months, or even years to obtain, the cost becomes a social cost that we all eventually bear.
{"title":"Incorporating complex data structures into a language for social science research","authors":"S. Kidd","doi":"10.1145/1478559.1478612","DOIUrl":"https://doi.org/10.1145/1478559.1478612","url":null,"abstract":"This paper presents a set of augmentations to the language BEAST (Brookings Economics and Statistical Translator) as part of a continuing effort to define a language for a particular group of computer users, social scientists. In this nebulous group we include professional economists, political scientists, psychologists, sociologists, and a large number of university students in those disciplines. An important assumption underlying our work has been that the cost of not having substantially better software than presently exists is very large and should be measured in terms of researchers' time. The true cost of inappropriate methods of computer utilization should not be measured by staff and computer costs, but by the social cost of the output foregone. When answers to questions of importance for national public policy formation require weeks, months, or even years to obtain, the cost becomes a social cost that we all eventually bear.","PeriodicalId":230827,"journal":{"name":"AFIPS '69 (Fall)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1969-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130311851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper discusses the dilemma posed by the promises made about large-scale integration, and the expectations derived from the promises. Furthermore, it examines LSI's present form. In some instances what have appeared to be "broken promises" are not in fact that at all. Some believers wanted to believe and thus have suffered from self-delusion. Some promises certainly were unwise or premature, thus creating false impressions. But others represented a misunderstanding between component and system engineers.
{"title":"Large-scale integration: promises versus accomplishments: the dilemma of our industry","authors":"H. Rudenberg","doi":"10.1145/1478559.1478601","DOIUrl":"https://doi.org/10.1145/1478559.1478601","url":null,"abstract":"This paper discusses the dilemma posed by the promises made about large-scale integration, and the expectations derived from the promises. Furthermore, it examines LSI's present form. In some instances what have appeared to be \"broken promises\" are not in fact that at all. Some believers wanted to believe and thus have suffered from self-delusion. Some promises certainly were unwise or premature, thus creating false impressions. But others represented a misunderstanding between component and system engineers.","PeriodicalId":230827,"journal":{"name":"AFIPS '69 (Fall)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1969-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125797778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The interconnection of circuits required in Large Scale Integration (LSI) using multi-level metalization above monolithic semiconductor arrays is taking basically two approaches. One is predicated on processing with a reasonable yield entire arrays without any semiconductor defects (i.e., 100 percent yield chips) which allows once-generated fixed-wiring patterns to obtain the required interconnect. The second approach aims at much larger semiconductor arrays (i.e., full-slice LSI) for which defect-free processing cannot be expected. Thus, probe tests are made of the semiconductor circuits processed on each LSI slice (or wafer) and record is made of the good and bad circuit positions. Unique interconnection masks are then generated to interconnect good circuits in each wafer's particular yield pattern using certain "discretion" in avoiding the bad circuits. As a result, the 100 percent yield approach emphasizes the need to use standard interconnect masks but is complexity limited by the occurrence of defective circuits in larger arrays, whereas approaches capable of routing around the defective circuits have required a full set of unique signal interconnect masks for each wafer's particular yield pattern.
{"title":"The pad relocation technique for interconnecting LSI arrays of imperfect yield","authors":"D. F. Calhoun","doi":"10.1145/1478559.1478571","DOIUrl":"https://doi.org/10.1145/1478559.1478571","url":null,"abstract":"The interconnection of circuits required in Large Scale Integration (LSI) using multi-level metalization above monolithic semiconductor arrays is taking basically two approaches. One is predicated on processing with a reasonable yield entire arrays without any semiconductor defects (i.e., 100 percent yield chips) which allows once-generated fixed-wiring patterns to obtain the required interconnect. The second approach aims at much larger semiconductor arrays (i.e., full-slice LSI) for which defect-free processing cannot be expected. Thus, probe tests are made of the semiconductor circuits processed on each LSI slice (or wafer) and record is made of the good and bad circuit positions. Unique interconnection masks are then generated to interconnect good circuits in each wafer's particular yield pattern using certain \"discretion\" in avoiding the bad circuits. As a result, the 100 percent yield approach emphasizes the need to use standard interconnect masks but is complexity limited by the occurrence of defective circuits in larger arrays, whereas approaches capable of routing around the defective circuits have required a full set of unique signal interconnect masks for each wafer's particular yield pattern.","PeriodicalId":230827,"journal":{"name":"AFIPS '69 (Fall)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1969-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126548126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The computer-aided design (CAD) system described herein was developed to aid in the design of digital systems to be implemented by custom integrated circuits (CIC) and multi-chip hybrid custom integrated systems (CIS). The terms MSI/LSI are avoided here due to the general confusion which exists in the literature as to what constitutes an MSI/LSI circuit. The CAD system philosophy is that each CIC is implemented from a selected set of "library elements". This design approach results in some size inefficiencies, compared with manual designs, but provides many advantages, of which flexibility and a shortened design cycle are the most important. This CAD system captures fundamental design information in a machine-readable form early in the design process, thus maximizing potential computer assistance and minimizing costly and time-consuming errors. This paper contains an overview of the complete CAD system, highlighting its more distinctive features. The complete system has been operational on a 360/30 for several months, and specific experiences with it can therefore be discussed.
{"title":"Computer-aided design for custom integrated systems","authors":"W. K. Orr","doi":"10.1145/1478559.1478632","DOIUrl":"https://doi.org/10.1145/1478559.1478632","url":null,"abstract":"The computer-aided design (CAD) system described herein was developed to aid in the design of digital systems to be implemented by custom integrated circuits (CIC) and multi-chip hybrid custom integrated systems (CIS). The terms MSI/LSI are avoided here due to the general confusion which exists in the literature as to what constitutes an MSI/LSI circuit. The CAD system philosophy is that each CIC is implemented from a selected set of \"library elements\". This design approach results in some size inefficiencies, compared with manual designs, but provides many advantages, of which flexibility and a shortened design cycle are the most important. This CAD system captures fundamental design information in a machine-readable form early in the design process, thus maximizing potential computer assistance and minimizing costly and time-consuming errors. This paper contains an overview of the complete CAD system, highlighting its more distinctive features. The complete system has been operational on a 360/30 for several months, and specific experiences with it can therefore be discussed.","PeriodicalId":230827,"journal":{"name":"AFIPS '69 (Fall)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1969-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129610499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Previous research and development efforts in digital monolithic integrated circuits and arrays were almost exclusively concerned with Boolean logic. However, by introducing threshold logic, considerable savings in gate count as well as in subsystem processing speed are evident. When logic subsystems, such as registers, adders, counters or combinational control logic, designed with common NOR logic, were replaced by subsystems employing threshold logic, average savings in gate count of three to one have been demonstrated. Furthermore, the number of consecutive logic levels necessary to implement a given switching function, and thus the relative processing delay, is also generally reduced by the same ratio.
{"title":"Nanosecond threshold logic gates for 16 X 16 bit, 80 ns LSI multiplier","authors":"L. Micheel","doi":"10.1145/1478559.1478614","DOIUrl":"https://doi.org/10.1145/1478559.1478614","url":null,"abstract":"Previous research and development efforts in digital monolithic integrated circuits and arrays were almost exclusively concerned with Boolean logic. However, by introducing threshold logic, considerable savings in gate count as well as in subsystem processing speed are evident. When logic subsystems, such as registers, adders, counters or combinational control logic, designed with common NOR logic, were replaced by subsystems employing threshold logic, average savings in gate count of three to one have been demonstrated. Furthermore, the number of consecutive logic levels necessary to implement a given switching function, and thus the relative processing delay, is also generally reduced by the same ratio.","PeriodicalId":230827,"journal":{"name":"AFIPS '69 (Fall)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1969-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132698129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hybrid executive programs have long been prevalent in the hybrid computer simulation industry, however, what should be the essential features of a hybrid executive is still a controversial subject. For the most part, the design of hybrid executives has been undertaken by the manufacturers of hybrid systems and in many designs the complexity in the operation of these programs has resulted in their usage only on large class digital systems. Consequently, hybrid facilities which employ a small to medium class digital computer system are faced with the task of developing an executive program compatible with the facility environment. However, in many of these small to medium hybrid facilities, the segregated program development effort for a hybrid executive is not undertaken until considerable time after the installation of the hybrid system. The normal reasons are inadequate programming funds or a higher priority assignment of available personnel to satisfy programming and development needs of existing hybrid simulations.
{"title":"Hybrid executive: user's approach","authors":"W. L. Graves, R. MacDonald","doi":"10.1145/1478559.1478591","DOIUrl":"https://doi.org/10.1145/1478559.1478591","url":null,"abstract":"Hybrid executive programs have long been prevalent in the hybrid computer simulation industry, however, what should be the essential features of a hybrid executive is still a controversial subject. For the most part, the design of hybrid executives has been undertaken by the manufacturers of hybrid systems and in many designs the complexity in the operation of these programs has resulted in their usage only on large class digital systems. Consequently, hybrid facilities which employ a small to medium class digital computer system are faced with the task of developing an executive program compatible with the facility environment. However, in many of these small to medium hybrid facilities, the segregated program development effort for a hybrid executive is not undertaken until considerable time after the installation of the hybrid system. The normal reasons are inadequate programming funds or a higher priority assignment of available personnel to satisfy programming and development needs of existing hybrid simulations.","PeriodicalId":230827,"journal":{"name":"AFIPS '69 (Fall)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1969-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132874876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Multics PL/1 compiler is in many respects a "second generation" PL/1 compiler. It was built at a time when the language was considerably more stable and well defined than it had been when the first compilers were built. It has benefited from the experience of the first compilers and avoids some of the difficulties which they encountered. The Multics compiler is the only PL/1 compiler written in PL/1 and is believed to be the first PL/1 compiler to produce high speed object code.
{"title":"The multics PL/1 compiler","authors":"R. Freiburghouse","doi":"10.1145/1478559.1478581","DOIUrl":"https://doi.org/10.1145/1478559.1478581","url":null,"abstract":"The Multics PL/1 compiler is in many respects a \"second generation\" PL/1 compiler. It was built at a time when the language was considerably more stable and well defined than it had been when the first compilers were built. It has benefited from the experience of the first compilers and avoids some of the difficulties which they encountered. The Multics compiler is the only PL/1 compiler written in PL/1 and is believed to be the first PL/1 compiler to produce high speed object code.","PeriodicalId":230827,"journal":{"name":"AFIPS '69 (Fall)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1969-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126248893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The subject of this paper is a general syntax directed macro preprocessor system. One of the suggested potential uses of this system is that of evaluating new or extended programming languages by the technique of syntax directed macros. This led to the association of the acronym SYMPLE (SYntax Macro Preprocessor for Language Evaluations) with this system.
{"title":"SYMPLE: a general syntax directed macro preprocessor","authors":"J. E. V. Mey, R. C. Varney, Robert E. Patchen","doi":"10.1145/1478559.1478578","DOIUrl":"https://doi.org/10.1145/1478559.1478578","url":null,"abstract":"The subject of this paper is a general syntax directed macro preprocessor system. One of the suggested potential uses of this system is that of evaluating new or extended programming languages by the technique of syntax directed macros. This led to the association of the acronym SYMPLE (SYntax Macro Preprocessor for Language Evaluations) with this system.","PeriodicalId":230827,"journal":{"name":"AFIPS '69 (Fall)","volume":"8 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1969-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124260803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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