Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514611
N. Togawa, M. Sato, T. Ohtsuki
Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.
{"title":"Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs","authors":"N. Togawa, M. Sato, T. Ohtsuki","doi":"10.1109/APCCAS.1994.514611","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514611","url":null,"abstract":"Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"286 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123442052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514555
Jong-Jy Shyu, S. Pei
A new method is proposed for designing complex all-pass IIR filters, the all-pass IIR filters with complex coefficients, in this paper. By minimizing the integration of certain square phase error over interested frequencies, an eigenvector of an appropriate real, symmetric and positive-definite matrix is computed to get the filter coefficients. The stability is achieved by specifying properly the desired phase specifications. If an appropriate iterative process is used, equiripple complex all-pass filter design can be obtained. The method is simple and the performance is comparable to the existing methods. Several examples are presented to demonstrate the effectiveness of the approach.
{"title":"Equiripple phase design of complex all-pass networks","authors":"Jong-Jy Shyu, S. Pei","doi":"10.1109/APCCAS.1994.514555","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514555","url":null,"abstract":"A new method is proposed for designing complex all-pass IIR filters, the all-pass IIR filters with complex coefficients, in this paper. By minimizing the integration of certain square phase error over interested frequencies, an eigenvector of an appropriate real, symmetric and positive-definite matrix is computed to get the filter coefficients. The stability is achieved by specifying properly the desired phase specifications. If an appropriate iterative process is used, equiripple complex all-pass filter design can be obtained. The method is simple and the performance is comparable to the existing methods. Several examples are presented to demonstrate the effectiveness of the approach.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122099113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514546
Y. Takeuchi, K. Shibata, H. Kunieda
Software/hardware codesign have been well researched. Many codesign systems' targets are the application specific systems which use CPU core and its hardware peripherals. We expand this application specific codesign concept into the general purpose codesign concept. We propose the codesign system concept using a workstation as a general purpose hardware and a field programmable logic device (FPGA) as a program specific hardware. In our proposed system, FPGA behaves like a programmable hardware engine for target programs. The advantage of our codesign system is shown on the prototype system using an example for image processing.
{"title":"Codesign methodology on programmable hardware and software system","authors":"Y. Takeuchi, K. Shibata, H. Kunieda","doi":"10.1109/APCCAS.1994.514546","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514546","url":null,"abstract":"Software/hardware codesign have been well researched. Many codesign systems' targets are the application specific systems which use CPU core and its hardware peripherals. We expand this application specific codesign concept into the general purpose codesign concept. We propose the codesign system concept using a workstation as a general purpose hardware and a field programmable logic device (FPGA) as a program specific hardware. In our proposed system, FPGA behaves like a programmable hardware engine for target programs. The advantage of our codesign system is shown on the prototype system using an example for image processing.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116565136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514629
M. Mancuso, V. D'Alto, R. Poluzzi
To improve TV image quality without changing the current transmission standards, advanced soft-decision fuzzy logic techniques have been applied to remove noise affecting pictures and to avoid interlaced-scan-related artifacts, thus leading to the definition of a new Fuzzy Noise Reducer and Scanning Rate Converter system.
{"title":"Fuzzy edge-oriented motion-adaptive noise reduction and scanning rate conversion","authors":"M. Mancuso, V. D'Alto, R. Poluzzi","doi":"10.1109/APCCAS.1994.514629","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514629","url":null,"abstract":"To improve TV image quality without changing the current transmission standards, advanced soft-decision fuzzy logic techniques have been applied to remove noise affecting pictures and to avoid interlaced-scan-related artifacts, thus leading to the definition of a new Fuzzy Noise Reducer and Scanning Rate Converter system.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134599825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514570
Shiunn-Jang Chern, Jeng-Shiann Jiang
In many applications of digital communication engineering, the bits of the data sequence transmitted do not have equal significance. To seek a more reliable information transmission, some unequal error protection (UEP) coding schemes have been devised. In this paper, however, we do not suggest a new UEP coding scheme, instead, through intimate combination of quantizer, interleaver, and the best convolutional code (CC) or trellis-coded modulation (TCM), the UEP capability can be achieved. Moreover, to investigate the performance of the proposed UEP coding scheme, we deduce the bit error rates of the corresponding encoder input ports from the transfer function of the encoder. The transfer function is derived based on the state diagram, such that the UEP capability of the encoder can be proved. Finally, from the simulation results we find that the mean square error between the original quantized signal and the received quantized signal can be reduced when the presented method is employed compared to the CC or TCM without the interleaver.
{"title":"The performance improvement of UEP code with interleaver","authors":"Shiunn-Jang Chern, Jeng-Shiann Jiang","doi":"10.1109/APCCAS.1994.514570","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514570","url":null,"abstract":"In many applications of digital communication engineering, the bits of the data sequence transmitted do not have equal significance. To seek a more reliable information transmission, some unequal error protection (UEP) coding schemes have been devised. In this paper, however, we do not suggest a new UEP coding scheme, instead, through intimate combination of quantizer, interleaver, and the best convolutional code (CC) or trellis-coded modulation (TCM), the UEP capability can be achieved. Moreover, to investigate the performance of the proposed UEP coding scheme, we deduce the bit error rates of the corresponding encoder input ports from the transfer function of the encoder. The transfer function is derived based on the state diagram, such that the UEP capability of the encoder can be proved. Finally, from the simulation results we find that the mean square error between the original quantized signal and the received quantized signal can be reduced when the presented method is employed compared to the CC or TCM without the interleaver.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134150333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514573
H. Shirahama, K. Taniguchi, O. Tsukahara
The proposed PLL realizes a fast and wide-ranging pull-in, and a stable locked condition by controlling a frequency difference detector and a PLL core with a dual loop constants in three modes. Simulations of the PLL designed with an 0.8 /spl mu/m bipolar devices and experiments using a PLL-IC together with PLAs demonstrated the features; a short pull-in time comparable to SAW filters even for 63 bit PRBS NRZ inputs, low output jitter and no slowly-recovering phase error.
{"title":"A very fast three-mode retiming PLL with low jitter and wide operating margin","authors":"H. Shirahama, K. Taniguchi, O. Tsukahara","doi":"10.1109/APCCAS.1994.514573","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514573","url":null,"abstract":"The proposed PLL realizes a fast and wide-ranging pull-in, and a stable locked condition by controlling a frequency difference detector and a PLL core with a dual loop constants in three modes. Simulations of the PLL designed with an 0.8 /spl mu/m bipolar devices and experiments using a PLL-IC together with PLAs demonstrated the features; a short pull-in time comparable to SAW filters even for 63 bit PRBS NRZ inputs, low output jitter and no slowly-recovering phase error.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133680949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514593
T. Her, W. Tsai, F. Kurdahi, Yulin Chen
We present a new state assignment model for minimizing power dissipation in Finite State Machines (FSMs). Our model takes into account power dissipation in terms of transition densities during state assignment process such that the number of transitions of the state encoding bits is minimized. Given the set of input signal probabilities, we compute not only the transition probabilities but also the exact state probabilities, the fractions of time for FSMs being in certain states, to be used in an objective weight function depending on encodings of states in FSMs. For every benchmark example circuits, our model always generates the least number of transitions among several state assignment models that confirms the effectiveness of our model.
{"title":"Low-power driven state assignment of finite state machines","authors":"T. Her, W. Tsai, F. Kurdahi, Yulin Chen","doi":"10.1109/APCCAS.1994.514593","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514593","url":null,"abstract":"We present a new state assignment model for minimizing power dissipation in Finite State Machines (FSMs). Our model takes into account power dissipation in terms of transition densities during state assignment process such that the number of transitions of the state encoding bits is minimized. Given the set of input signal probabilities, we compute not only the transition probabilities but also the exact state probabilities, the fractions of time for FSMs being in certain states, to be used in an objective weight function depending on encodings of states in FSMs. For every benchmark example circuits, our model always generates the least number of transitions among several state assignment models that confirms the effectiveness of our model.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132008677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514520
M. Kawabe, T. Sato, T. Kato, A. Fukasawa, R. Kohno
This paper describes the configuration, analysis and characteristics of an M-ary CDMA using Interference Cancellation (IC) with the Walsh orthogonal code. The IC reduces interference signals of other Personal Stations (PSs), improves communication quality and increases system capacity in a cell. In this IC scheme, the cancellation value is calculated from the correlation value, and then the cancellation value corresponds to the variation of fading. Analysis results indicate that the limitation of the system capacity becomes equal to the spreading ratio when IC is used. A computer simulation shows that simultaneously accessing users per cell are obtained up to 40 channels using 2/sup 6/ Walsh codes as spreading codes under Rayleigh fading conditions.
{"title":"M-ary CDMA scheme based on interference cancellation","authors":"M. Kawabe, T. Sato, T. Kato, A. Fukasawa, R. Kohno","doi":"10.1109/APCCAS.1994.514520","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514520","url":null,"abstract":"This paper describes the configuration, analysis and characteristics of an M-ary CDMA using Interference Cancellation (IC) with the Walsh orthogonal code. The IC reduces interference signals of other Personal Stations (PSs), improves communication quality and increases system capacity in a cell. In this IC scheme, the cancellation value is calculated from the correlation value, and then the cancellation value corresponds to the variation of fading. Analysis results indicate that the limitation of the system capacity becomes equal to the spreading ratio when IC is used. A computer simulation shows that simultaneously accessing users per cell are obtained up to 40 channels using 2/sup 6/ Walsh codes as spreading codes under Rayleigh fading conditions.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129411752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514556
F. Leeb
In modern digital communication systems the need for digital filters with high selectivity and good phase linearity is rapidly increasing. A new all-pass equalization approach is presented that uses a new design strategy based on the interaction between amplitude and phase (or group-delay) requirements and lattice wave digital filter (WDF) cascaded by an all-pass filter for the realization. Furthermore for given amplitude and phase specifications a method for predicting the minimum required degree of the transfer function is presented. The design example demonstrates the properties of the proposed method and the efficiency in comparison to simultaneous amplitude and phase approximation method.
{"title":"The comeback of the all-pass equalization approach for digital filter with combined amplitude and phase specifications","authors":"F. Leeb","doi":"10.1109/APCCAS.1994.514556","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514556","url":null,"abstract":"In modern digital communication systems the need for digital filters with high selectivity and good phase linearity is rapidly increasing. A new all-pass equalization approach is presented that uses a new design strategy based on the interaction between amplitude and phase (or group-delay) requirements and lattice wave digital filter (WDF) cascaded by an all-pass filter for the realization. Furthermore for given amplitude and phase specifications a method for predicting the minimum required degree of the transfer function is presented. The design example demonstrates the properties of the proposed method and the efficiency in comparison to simultaneous amplitude and phase approximation method.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129470043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514539
F. El-Hadidy, O. E. Herrmann
Many techniques and design tools have been developed for mapping algorithms to array processors. Linear mapping is usually used for regular algorithms. Large and complex problems are not regular by nature and regularization may cause a computational overhead which prevents the ability to meet real-time deadlines. In this paper, a systematic design methodology for mapping partially-regular as well as regular Dependence Graphs is presented. In this approach the set of all optimal solutions is generated under the given constraints. Due to nature of the problem and the tight timing constraints of real-time systems the set of alternative solutions is limited. An image processing example is discussed.
{"title":"Generalized methodology for array processor design of real-time systems","authors":"F. El-Hadidy, O. E. Herrmann","doi":"10.1109/APCCAS.1994.514539","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514539","url":null,"abstract":"Many techniques and design tools have been developed for mapping algorithms to array processors. Linear mapping is usually used for regular algorithms. Large and complex problems are not regular by nature and regularization may cause a computational overhead which prevents the ability to meet real-time deadlines. In this paper, a systematic design methodology for mapping partially-regular as well as regular Dependence Graphs is presented. In this approach the set of all optimal solutions is generated under the given constraints. Due to nature of the problem and the tight timing constraints of real-time systems the set of alternative solutions is limited. An image processing example is discussed.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128210675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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