Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514576
J. Shimizu, Yoshikazu Miyanaga, K. Tochinai
Multirate adaptive filters for the identification of time-varying systems are very important. However, a decimation factor to be used in the multirate adaptive filtering for the identification of time-varying system has not been considered quantitatively. We derive two conditions which limit the maximally decimated factor used in the time-varying system identification.
{"title":"Consideration on decimation factors in multirate adaptive filtering for a time-varying AR model","authors":"J. Shimizu, Yoshikazu Miyanaga, K. Tochinai","doi":"10.1109/APCCAS.1994.514576","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514576","url":null,"abstract":"Multirate adaptive filters for the identification of time-varying systems are very important. However, a decimation factor to be used in the multirate adaptive filtering for the identification of time-varying system has not been considered quantitatively. We derive two conditions which limit the maximally decimated factor used in the time-varying system identification.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117137259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514514
H. Yoshida, M. Miura
The concept of chirality is introduced artificial neural network field separation methods of enantiomers. The separated chiral network shows a characteristic function in most cases, and the combination of the chiral subunits implements new functions.
{"title":"Chirality in neural network systems","authors":"H. Yoshida, M. Miura","doi":"10.1109/APCCAS.1994.514514","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514514","url":null,"abstract":"The concept of chirality is introduced artificial neural network field separation methods of enantiomers. The separated chiral network shows a characteristic function in most cases, and the combination of the chiral subunits implements new functions.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117324709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514547
T. Hee, G. Hellestrand
As the number and type of design tools available increase, it becomes necessary to provide management and assistance services to designers during design process. Often the design tools may not run on a single hardware platform. Thus, the design process needs be conducted across machines. In this paper we present the implementation of the distributed, multi-agent framework, Colossus, for the synthesis of VLSI design process systems. Colossus allows design process knowledge to be abstracted and grouped to form domains, which are distinct entities providing specialised design services. It allows VLSI design process systems to be realised by integrating a set of domains to offer integrated design services as a whole. We illustrate how design process systems based on the framework are synthesised and used to undertake design processes.
{"title":"On the implementation of a distributed, multi-agent framework for VLSI design process system synthesis","authors":"T. Hee, G. Hellestrand","doi":"10.1109/APCCAS.1994.514547","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514547","url":null,"abstract":"As the number and type of design tools available increase, it becomes necessary to provide management and assistance services to designers during design process. Often the design tools may not run on a single hardware platform. Thus, the design process needs be conducted across machines. In this paper we present the implementation of the distributed, multi-agent framework, Colossus, for the synthesis of VLSI design process systems. Colossus allows design process knowledge to be abstracted and grouped to form domains, which are distinct entities providing specialised design services. It allows VLSI design process systems to be realised by integrating a set of domains to offer integrated design services as a whole. We illustrate how design process systems based on the framework are synthesised and used to undertake design processes.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115761939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514552
K. Su, Y. Chen, C. Lai, J. Kuo, J.S. Wu, H.W. Tso
This paper presents a 1.5 V 10 MHz quasi-digital vector modulator using low-voltage BiCMOS dynamic logic circuit and digital-to-analog converter for wireless communication IC. Based on a 1 /spl mu/m BiCMOS technology, the 1.5 V quasi-digital vector modulator shows a total harmonic distortion of 20.7% at a carrier frequency of 10 MHz.
利用低压BiCMOS动态逻辑电路和数模转换器设计了一种用于无线通信IC的1.5 V 10 MHz准数字矢量调制器。基于1 /spl mu/m BiCMOS技术，该1.5 V准数字矢量调制器在载波频率为10 MHz时的总谐波失真为20.7%。
{"title":"A 1.5 V 10 MHz BiCMOS quasi-digital vector modulator for wireless communication IC","authors":"K. Su, Y. Chen, C. Lai, J. Kuo, J.S. Wu, H.W. Tso","doi":"10.1109/APCCAS.1994.514552","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514552","url":null,"abstract":"This paper presents a 1.5 V 10 MHz quasi-digital vector modulator using low-voltage BiCMOS dynamic logic circuit and digital-to-analog converter for wireless communication IC. Based on a 1 /spl mu/m BiCMOS technology, the 1.5 V quasi-digital vector modulator shows a total harmonic distortion of 20.7% at a carrier frequency of 10 MHz.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127623494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514525
Feng-li Lin, S. Chang, Heng-Dao Lin
A coverage area prediction method developed in TL (Telecommunication Laboratories) is introduced. The program uses a simple method to predict the signal interference and coverage area automatically and quickly. This technique helps us to re-allocate the site and frequency of radio stations efficiently, especially useful for the advent of HDTV.
{"title":"Coverage area prediction for HDTV","authors":"Feng-li Lin, S. Chang, Heng-Dao Lin","doi":"10.1109/APCCAS.1994.514525","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514525","url":null,"abstract":"A coverage area prediction method developed in TL (Telecommunication Laboratories) is introduced. The program uses a simple method to predict the signal interference and coverage area automatically and quickly. This technique helps us to re-allocate the site and frequency of radio stations efficiently, especially useful for the advent of HDTV.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123018482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514605
C. C. Chiu, J. Deller
In this paper, a two-pass graph search technique is presented to conduct the search in the partitioned language graph. The first stage of the search uses a evaluation subroutine to efficiently reduce the graph to a subgraph consisting of the top "n" best paths. This small graph comprises a small search space of usually much less than size /spl Oscr/(/spl radic/N), whereas the original graph is or size N. The second stage of the search seeks out the optimal path from among those remaining in the subgraph. At the end of the search, the most likely path corresponding to the input utterance is found. This technique is applied to recognition of continuous speech taken from TIMIT speech database, and provides encouraging results.
{"title":"A two-pass decoding algorithm for partitioned search in continuous speech recognition","authors":"C. C. Chiu, J. Deller","doi":"10.1109/APCCAS.1994.514605","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514605","url":null,"abstract":"In this paper, a two-pass graph search technique is presented to conduct the search in the partitioned language graph. The first stage of the search uses a evaluation subroutine to efficiently reduce the graph to a subgraph consisting of the top \"n\" best paths. This small graph comprises a small search space of usually much less than size /spl Oscr/(/spl radic/N), whereas the original graph is or size N. The second stage of the search seeks out the optimal path from among those remaining in the subgraph. At the end of the search, the most likely path corresponding to the input utterance is found. This technique is applied to recognition of continuous speech taken from TIMIT speech database, and provides encouraging results.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124434874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514563
T. Ohtsuka, H. Kunieda
This paper presents a new approach to circuit optimization, aiming at both short optimization time and high accuracy. Initially, the design variables of the analog circuit module are optimized with simple transistor models with the aim at making design variables closer to the optimal solution speedy. After the design variable vector reaches the near optimal solution, the device model refinement is performed for each device to achieve higher precision. This procedure is repeated until the device model becomes precise enough in the IC environment. The sequence of the device model refinement should be set in advance by designers. A design example indicates that the optimization using device model refining can be carried out in a shorter time than the simulation based approach, whilst achieving a high precision for the solution.
{"title":"Hierarchical circuit optimization for analog LSIs using device model refining","authors":"T. Ohtsuka, H. Kunieda","doi":"10.1109/APCCAS.1994.514563","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514563","url":null,"abstract":"This paper presents a new approach to circuit optimization, aiming at both short optimization time and high accuracy. Initially, the design variables of the analog circuit module are optimized with simple transistor models with the aim at making design variables closer to the optimal solution speedy. After the design variable vector reaches the near optimal solution, the device model refinement is performed for each device to achieve higher precision. This procedure is repeated until the device model becomes precise enough in the IC environment. The sequence of the device model refinement should be set in advance by designers. A design example indicates that the optimization using device model refining can be carried out in a shorter time than the simulation based approach, whilst achieving a high precision for the solution.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114153995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514585
T. Deng, T. Soma
This paper proposes an efficient technique for designing recursive two-dimensional (2-D) variable digital filters with arbitrary magnitude characteristics. The technique is based on the decomposition of the given 2-D variable magnitude specifications. Using this technique we can obtain a 2-D variable digital filter by simply designing a set of 2-D constant filters and approximating a set of 1-D polynomials. Consequently, the original difficult 2-D variable filter design problem can be significantly simplified.
{"title":"Decomposition-based 2-D variable digital filter design","authors":"T. Deng, T. Soma","doi":"10.1109/APCCAS.1994.514585","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514585","url":null,"abstract":"This paper proposes an efficient technique for designing recursive two-dimensional (2-D) variable digital filters with arbitrary magnitude characteristics. The technique is based on the decomposition of the given 2-D variable magnitude specifications. Using this technique we can obtain a 2-D variable digital filter by simply designing a set of 2-D constant filters and approximating a set of 1-D polynomials. Consequently, the original difficult 2-D variable filter design problem can be significantly simplified.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114330050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514584
Sau-Gee Chen, K. Chen
A new 1-D linear-phase interpolation algorithm is proposed in this paper. For every M output points the new algorithm reduces the number of multiplication operations from the best known N/2 to N/4+N/(2M), while it requires 3N/4+3N/(2M)+2M-2 addition operations, which may be smaller or greater than the best known N-M, where N and M are the interpolator tap number and interpolation factor respectively. The algorithms are further extended to 1-D nonlinear-phase interpolation and 2-D linear-phase interpolations. Systolic array realization for 1-D linear-phase algorithm is also given, which is highly regular and suitable for VLSI implementation. The algorithm assumes a filter order of an even multiple of the interpolation factor. The condition is not too restrictive, because the interpolator tap number can be shown to be empirically proportional to the interpolation factor. Moreover, the drawback of possibly increased filter order could be overcompensated by the saving of close to N/2 multiplication operations, as well as the gain in tighter filter specifications.
{"title":"New efficient interpolation algorithm and its realizations","authors":"Sau-Gee Chen, K. Chen","doi":"10.1109/APCCAS.1994.514584","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514584","url":null,"abstract":"A new 1-D linear-phase interpolation algorithm is proposed in this paper. For every M output points the new algorithm reduces the number of multiplication operations from the best known N/2 to N/4+N/(2M), while it requires 3N/4+3N/(2M)+2M-2 addition operations, which may be smaller or greater than the best known N-M, where N and M are the interpolator tap number and interpolation factor respectively. The algorithms are further extended to 1-D nonlinear-phase interpolation and 2-D linear-phase interpolations. Systolic array realization for 1-D linear-phase algorithm is also given, which is highly regular and suitable for VLSI implementation. The algorithm assumes a filter order of an even multiple of the interpolation factor. The condition is not too restrictive, because the interpolator tap number can be shown to be empirically proportional to the interpolation factor. Moreover, the drawback of possibly increased filter order could be overcompensated by the saving of close to N/2 multiplication operations, as well as the gain in tighter filter specifications.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"524 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125485596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514519
Wang Duanyi, Hu Zhengming
A brief survey of recent developments in combined channel coding and digital modulation (in short coded modulation) for Rayleigh fading channels is presented. Theoretical guidance for design and identification of the most important system parameters are given. Two constructive schemes that are suited for the fading channel are discussed. The systematic design method for coded modulation on the fading channel is summarized, which can construct coded modulation systems to give optimum asymptotic performance on the fading channel. Some proposed schemes are compared according to the design method.
{"title":"The systematic design method for coded modulation on fading channels","authors":"Wang Duanyi, Hu Zhengming","doi":"10.1109/APCCAS.1994.514519","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514519","url":null,"abstract":"A brief survey of recent developments in combined channel coding and digital modulation (in short coded modulation) for Rayleigh fading channels is presented. Theoretical guidance for design and identification of the most important system parameters are given. Two constructive schemes that are suited for the fading channel are discussed. The systematic design method for coded modulation on the fading channel is summarized, which can construct coded modulation systems to give optimum asymptotic performance on the fading channel. Some proposed schemes are compared according to the design method.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124444141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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