Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514581
F. Sakaguchi
If the covariance function of a random signal can be written in a diagonal form via the wavelet basis, this random signal can be regarded as a superposition of the wavelets which arise randomly. However, it is known that, in general, such an expression is not possible. In this paper, in place of a perfect diagonalization, an optimal approximate diagonalization in the sense of the relative entropy is investigated theoretically. Especially, it is shown that when a set of wavelets forming complete orthonormal sets expressed in a vector form as {/spl phi//sub i/} is used as the basis, an optimal diagonal approximation of the covariance matrix /spl Gamma/ is not the diagonal form /spl Sigma//sub h/(/spl phi/~/sub h//sup /spl tau///spl Gamma//spl phi//sub h/)/spl phi//sub h//spl phi/~/sub h//sup /spl tau// using the so-called 'wavelet spectrum' but /spl Sigma//sub h/(/spl phi/~/sub h//sup /spl tau///spl Gamma//sup -1//spl phi//sub h/)/sup -1//spl phi//sub h//spl phi/~/sub h//sup /spl tau//. Further, several examples are given where Haar wavelets are used.
{"title":"On the diagonal approximation of the auto-correlation function with the wavelet basis which is optimal with respect to the relative entropy","authors":"F. Sakaguchi","doi":"10.1109/APCCAS.1994.514581","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514581","url":null,"abstract":"If the covariance function of a random signal can be written in a diagonal form via the wavelet basis, this random signal can be regarded as a superposition of the wavelets which arise randomly. However, it is known that, in general, such an expression is not possible. In this paper, in place of a perfect diagonalization, an optimal approximate diagonalization in the sense of the relative entropy is investigated theoretically. Especially, it is shown that when a set of wavelets forming complete orthonormal sets expressed in a vector form as {/spl phi//sub i/} is used as the basis, an optimal diagonal approximation of the covariance matrix /spl Gamma/ is not the diagonal form /spl Sigma//sub h/(/spl phi/~/sub h//sup /spl tau///spl Gamma//spl phi//sub h/)/spl phi//sub h//spl phi/~/sub h//sup /spl tau// using the so-called 'wavelet spectrum' but /spl Sigma//sub h/(/spl phi/~/sub h//sup /spl tau///spl Gamma//sup -1//spl phi//sub h/)/sup -1//spl phi//sub h//spl phi/~/sub h//sup /spl tau//. Further, several examples are given where Haar wavelets are used.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131892062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514618
Y. Shiwen, S. Tsuiki, M. Ishida, Y. Fukui
A versatile current-mode biquad filter using three operational amplifiers and 9 passive elements is proposed. By the suitable choice of the output branch, lowpass, bandpass, highpass, bandstop and allpass transfer functions are realized simultaneously without changing the circuit configuration and elements. Two circuits, one is for low frequency application and the other for high frequency, are proposed. The center frequency, quality factor and gain constants of the circuit can be tuned independently. Simulated results will show that the circuits work successfully.
{"title":"A versatile current-mode biquad using operational amplifiers","authors":"Y. Shiwen, S. Tsuiki, M. Ishida, Y. Fukui","doi":"10.1109/APCCAS.1994.514618","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514618","url":null,"abstract":"A versatile current-mode biquad filter using three operational amplifiers and 9 passive elements is proposed. By the suitable choice of the output branch, lowpass, bandpass, highpass, bandstop and allpass transfer functions are realized simultaneously without changing the circuit configuration and elements. Two circuits, one is for low frequency application and the other for high frequency, are proposed. The center frequency, quality factor and gain constants of the circuit can be tuned independently. Simulated results will show that the circuits work successfully.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129911912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514567
K. Yoon, Doo-Bok Lee, P. K. Rhee, S. Han, S.J. Park
This paper describes a parallel algorithm of an automated CMOS circuit extraction that transforms an IC layout into a circuit netlist suitable for circuit simulations. Using reconfigurable parallel machine architecture, the newly developed algorithm achieved a circuit extraction performance which is a constant time complexity. The layout of a CMOS inverter used successfully to demonstrate an efficiency of the newly developed algorithm.
{"title":"A VLSI circuit extractor with a parallel algorithm","authors":"K. Yoon, Doo-Bok Lee, P. K. Rhee, S. Han, S.J. Park","doi":"10.1109/APCCAS.1994.514567","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514567","url":null,"abstract":"This paper describes a parallel algorithm of an automated CMOS circuit extraction that transforms an IC layout into a circuit netlist suitable for circuit simulations. Using reconfigurable parallel machine architecture, the newly developed algorithm achieved a circuit extraction performance which is a constant time complexity. The layout of a CMOS inverter used successfully to demonstrate an efficiency of the newly developed algorithm.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125897772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514587
M. Muneyasu, T. Hinamoto
An adaptive technique is developed for designing two-dimensional (2-D) state-space digital filters in the frequency domain. The Roesser local state-space (LSS) model is used to describe the 2-D digital filters. First, the frequency response of the Roesser LSS model is investigated to define a performance index in which the reference signal is specified by magnitude response and group delays in the pass-band. An iterative algorithm based on the least mean square (LMS) method is then presented together with the calculation of gradient vectors required in the adaptive process. Finally, two numerical examples are solved to illustrate the utility of the proposed technique.
{"title":"Frequency-domain design of 2-D state-space digital filters using adaptive LMS algorithm","authors":"M. Muneyasu, T. Hinamoto","doi":"10.1109/APCCAS.1994.514587","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514587","url":null,"abstract":"An adaptive technique is developed for designing two-dimensional (2-D) state-space digital filters in the frequency domain. The Roesser local state-space (LSS) model is used to describe the 2-D digital filters. First, the frequency response of the Roesser LSS model is investigated to define a performance index in which the reference signal is specified by magnitude response and group delays in the pass-band. An iterative algorithm based on the least mean square (LMS) method is then presented together with the calculation of gradient vectors required in the adaptive process. Finally, two numerical examples are solved to illustrate the utility of the proposed technique.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"647 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115115058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514542
Yih-Fang Huang
Summary form only given. This presentation is intended to address issues that are related to learning and generalization capability of ANN. It is also intended to examine the state-of-the-art and, hopefully, stimulate discussions on where research should be directed. A survey on recent developments in supervised and unsupervised learning is given. Details of both learning strategies are elaborated with regard to some classes of ANN and their applications examined. The concept of selective learning is also discussed. Generalization capability of some classes of ANN is addressed, particularly, from the viewpoint of function realization. Special attention is focused on multilayer perceptrons. Other related questions such as "How large does a network have to be to perform a desired task?" are discussed.
{"title":"Artificial neural networks-learning and generalization","authors":"Yih-Fang Huang","doi":"10.1109/APCCAS.1994.514542","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514542","url":null,"abstract":"Summary form only given. This presentation is intended to address issues that are related to learning and generalization capability of ANN. It is also intended to examine the state-of-the-art and, hopefully, stimulate discussions on where research should be directed. A survey on recent developments in supervised and unsupervised learning is given. Details of both learning strategies are elaborated with regard to some classes of ANN and their applications examined. The concept of selective learning is also discussed. Generalization capability of some classes of ANN is addressed, particularly, from the viewpoint of function realization. Special attention is focused on multilayer perceptrons. Other related questions such as \"How large does a network have to be to perform a desired task?\" are discussed.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114810492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514613
Zhi-Ming Lin, Yu-Jung Huang, Kuo-Hong Hsiau
LAKE is an automatic layout generator that lays out CMOS analog integrated circuits subject to circuit layout constraints such as: matching, symmetry, signal coupling cell aspect ratio (or cell height), and specified cell input/output pin locations. Unlike most previous works, LAKE focuses on effective rules and methods that suit any type of CMOS analog circuit to be incorporated in an application-specific mixed analog digital layout system. Placement is based on the characteristics of circuit structure and the layout constraints. The proposed slot structure provides the capability of handling fully symmetric layouts. The simulated evolution process evaluates the quality of layout based detailed layout information in pursuing minimal parasitic effects on circuit performance. We test some real life examples. The design experiments have shown that LAKE can produce manual-quality analog layouts.
{"title":"LAKE: a performance-driven analog CMOS cell layout generator","authors":"Zhi-Ming Lin, Yu-Jung Huang, Kuo-Hong Hsiau","doi":"10.1109/APCCAS.1994.514613","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514613","url":null,"abstract":"LAKE is an automatic layout generator that lays out CMOS analog integrated circuits subject to circuit layout constraints such as: matching, symmetry, signal coupling cell aspect ratio (or cell height), and specified cell input/output pin locations. Unlike most previous works, LAKE focuses on effective rules and methods that suit any type of CMOS analog circuit to be incorporated in an application-specific mixed analog digital layout system. Placement is based on the characteristics of circuit structure and the layout constraints. The proposed slot structure provides the capability of handling fully symmetric layouts. The simulated evolution process evaluates the quality of layout based detailed layout information in pursuing minimal parasitic effects on circuit performance. We test some real life examples. The design experiments have shown that LAKE can produce manual-quality analog layouts.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125168817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514517
T. Dai, Ta-Sung Lee, C. Hwang
A novel beamspace radial basis function neural network for the estimation of the angle-of-arrival (AOA) of a mobile unit in cellular communications is proposed. By training the network with the data emitted from different sub-cells in the field of interest, and then collected by a set of antenna array beamformers optimum weights which lead to the best approximation of the desired response in least-square sense can be obtained. In principle, the network performs mapping from the complex input data into the desired angle response. Computer simulations demonstrate that the proposed scheme is effective in combating multipath interference.
{"title":"Novel beamspace neural network approach to mobile unit localization","authors":"T. Dai, Ta-Sung Lee, C. Hwang","doi":"10.1109/APCCAS.1994.514517","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514517","url":null,"abstract":"A novel beamspace radial basis function neural network for the estimation of the angle-of-arrival (AOA) of a mobile unit in cellular communications is proposed. By training the network with the data emitted from different sub-cells in the field of interest, and then collected by a set of antenna array beamformers optimum weights which lead to the best approximation of the desired response in least-square sense can be obtained. In principle, the network performs mapping from the complex input data into the desired angle response. Computer simulations demonstrate that the proposed scheme is effective in combating multipath interference.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116798743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514566
S. Smith, M. Ismail, C. Hung, Shu-Chuan Huang
Analysis of two layout designs used in the realization of MOS continuous-time integrated filters is presented. The effect of MOS parasitic capacitances is thoroughly studied and compared in the two layout design techniques. It is found that one layout method performs well at high frequencies or high Q, at the expense of increased harmonic distortion in comparison with the other method. A tradeoff between transistor matching and sensitivity to MOS intrinsic parasitic capacitances is revealed. A set of performance graphs are developed with the ratio of parasitic to integrating capacitance, C/sub P//C, as a parameter. These graphs are useful in the design of high performance MOS continuous-time integrated filters.
{"title":"Layout design considerations in MOS continuous-time integrated filters","authors":"S. Smith, M. Ismail, C. Hung, Shu-Chuan Huang","doi":"10.1109/APCCAS.1994.514566","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514566","url":null,"abstract":"Analysis of two layout designs used in the realization of MOS continuous-time integrated filters is presented. The effect of MOS parasitic capacitances is thoroughly studied and compared in the two layout design techniques. It is found that one layout method performs well at high frequencies or high Q, at the expense of increased harmonic distortion in comparison with the other method. A tradeoff between transistor matching and sensitivity to MOS intrinsic parasitic capacitances is revealed. A set of performance graphs are developed with the ratio of parasitic to integrating capacitance, C/sub P//C, as a parameter. These graphs are useful in the design of high performance MOS continuous-time integrated filters.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122225004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514535
M. Song, K. Asada
In this paper, a design methodology of a low power 54/spl times/54 bit multiplier based on a Window Detector is proposed. This multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea is the design of a Window Detector which implements the block of data compression. The role of the Window Detector is detecting the input data, choosing the optimized output data, and driving the next stage. Furthermore, it can reduce the power consumption drastically because only one optimized operation unit (a Window) is activated. Therefore, it can be called an intelligent Window Detector. Using it, the power consumption of the proposed multiplier is reduced by about 50%, compared with that of the conventional multiplier, while the propagation delay is not much more than that of the conventional one.
{"title":"Design of a low power 54/spl times/54 bit multiplier based on an intelligent window detector","authors":"M. Song, K. Asada","doi":"10.1109/APCCAS.1994.514535","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514535","url":null,"abstract":"In this paper, a design methodology of a low power 54/spl times/54 bit multiplier based on a Window Detector is proposed. This multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea is the design of a Window Detector which implements the block of data compression. The role of the Window Detector is detecting the input data, choosing the optimized output data, and driving the next stage. Furthermore, it can reduce the power consumption drastically because only one optimized operation unit (a Window) is activated. Therefore, it can be called an intelligent Window Detector. Using it, the power consumption of the proposed multiplier is reduced by about 50%, compared with that of the conventional multiplier, while the propagation delay is not much more than that of the conventional one.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117250613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514615
A. Charoenrook, M. Soma
This paper presents a very linear and wide dynamic range BiCMOS operational transconductance amplifier for use in high performance, high frequency analog and mixed-signal applications. The design structure of the input stage together with the optimized use of BiCMOS technology provides the OTA with wide dynamic range and very low distortion properties. Comparisons between MOSFET, bipolar and BiCMOS configurations of the conversion stage are presented. The frequency response of the circuit is also analyzed in detail, including frequency compensation techniques. Simulation results using a generic BiCMOS technology illustrate a THD of less than -68 dB at Vin=/spl plusmn/4 V at 50 MHz.
{"title":"A linear wide-dynamic-range BiCMOS operational transconductance amplifier for high frequency applications","authors":"A. Charoenrook, M. Soma","doi":"10.1109/APCCAS.1994.514615","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514615","url":null,"abstract":"This paper presents a very linear and wide dynamic range BiCMOS operational transconductance amplifier for use in high performance, high frequency analog and mixed-signal applications. The design structure of the input stage together with the optimized use of BiCMOS technology provides the OTA with wide dynamic range and very low distortion properties. Comparisons between MOSFET, bipolar and BiCMOS configurations of the conversion stage are presented. The frequency response of the circuit is also analyzed in detail, including frequency compensation techniques. Simulation results using a generic BiCMOS technology illustrate a THD of less than -68 dB at Vin=/spl plusmn/4 V at 50 MHz.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116819492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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