Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514609
Jin-Tai Yan, P.-Y. Hsiao
A unified partitioning based algorithm for the orientation and rotation assignments of macro cells is proposed to minimize total wire length in a macro cell placement. For the orientation and rotation assignments of macro cells, we transform the orientation problem and the rotation problem into a constrained graph bisection problem and a constrained graph quadrisection problem, respectively. Furthermore, a unified fuzzy graph clustering is proposed to solve the two constrained partitioning problems at the same time. The partitioning results of the constrained graph bisection and the constrained graph quadrisection will lend to the orientation and rotation assignments for a macro cell placement. As a result, the proposed partitioning based approach has tested some macro cell placements for the orientation and rotation assignments. The experimental results show that the partitioning based approach obtains better wire reductions on these tested placements.
{"title":"A partitioning-based approach for the orientation and rotation assignments of macro cells","authors":"Jin-Tai Yan, P.-Y. Hsiao","doi":"10.1109/APCCAS.1994.514609","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514609","url":null,"abstract":"A unified partitioning based algorithm for the orientation and rotation assignments of macro cells is proposed to minimize total wire length in a macro cell placement. For the orientation and rotation assignments of macro cells, we transform the orientation problem and the rotation problem into a constrained graph bisection problem and a constrained graph quadrisection problem, respectively. Furthermore, a unified fuzzy graph clustering is proposed to solve the two constrained partitioning problems at the same time. The partitioning results of the constrained graph bisection and the constrained graph quadrisection will lend to the orientation and rotation assignments for a macro cell placement. As a result, the proposed partitioning based approach has tested some macro cell placements for the orientation and rotation assignments. The experimental results show that the partitioning based approach obtains better wire reductions on these tested placements.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122525952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514592
T. Her, W. Tsai, F. Kurdahi, Y. Chen
We present a model based on the PLA implementation of logic circuits to estimate the transition densities in two-level combinational logic circuits. Given the primary input signal probabilities and transition densities, our model computes the transition densities at the internal and output nodes directly from the sum-of-products representation of the two-level logic circuits without further converting the circuits into other representations. The experimental results from our model compared to those from SPICE simulations are within an average of 1.7% error, confirming the effectiveness of our model.
{"title":"A PLA-based algorithm for estimating transition densities in two-level combinational logic circuits","authors":"T. Her, W. Tsai, F. Kurdahi, Y. Chen","doi":"10.1109/APCCAS.1994.514592","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514592","url":null,"abstract":"We present a model based on the PLA implementation of logic circuits to estimate the transition densities in two-level combinational logic circuits. Given the primary input signal probabilities and transition densities, our model computes the transition densities at the internal and output nodes directly from the sum-of-products representation of the two-level logic circuits without further converting the circuits into other representations. The experimental results from our model compared to those from SPICE simulations are within an average of 1.7% error, confirming the effectiveness of our model.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131998319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514581
F. Sakaguchi
If the covariance function of a random signal can be written in a diagonal form via the wavelet basis, this random signal can be regarded as a superposition of the wavelets which arise randomly. However, it is known that, in general, such an expression is not possible. In this paper, in place of a perfect diagonalization, an optimal approximate diagonalization in the sense of the relative entropy is investigated theoretically. Especially, it is shown that when a set of wavelets forming complete orthonormal sets expressed in a vector form as {/spl phi//sub i/} is used as the basis, an optimal diagonal approximation of the covariance matrix /spl Gamma/ is not the diagonal form /spl Sigma//sub h/(/spl phi/~/sub h//sup /spl tau///spl Gamma//spl phi//sub h/)/spl phi//sub h//spl phi/~/sub h//sup /spl tau// using the so-called 'wavelet spectrum' but /spl Sigma//sub h/(/spl phi/~/sub h//sup /spl tau///spl Gamma//sup -1//spl phi//sub h/)/sup -1//spl phi//sub h//spl phi/~/sub h//sup /spl tau//. Further, several examples are given where Haar wavelets are used.
{"title":"On the diagonal approximation of the auto-correlation function with the wavelet basis which is optimal with respect to the relative entropy","authors":"F. Sakaguchi","doi":"10.1109/APCCAS.1994.514581","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514581","url":null,"abstract":"If the covariance function of a random signal can be written in a diagonal form via the wavelet basis, this random signal can be regarded as a superposition of the wavelets which arise randomly. However, it is known that, in general, such an expression is not possible. In this paper, in place of a perfect diagonalization, an optimal approximate diagonalization in the sense of the relative entropy is investigated theoretically. Especially, it is shown that when a set of wavelets forming complete orthonormal sets expressed in a vector form as {/spl phi//sub i/} is used as the basis, an optimal diagonal approximation of the covariance matrix /spl Gamma/ is not the diagonal form /spl Sigma//sub h/(/spl phi/~/sub h//sup /spl tau///spl Gamma//spl phi//sub h/)/spl phi//sub h//spl phi/~/sub h//sup /spl tau// using the so-called 'wavelet spectrum' but /spl Sigma//sub h/(/spl phi/~/sub h//sup /spl tau///spl Gamma//sup -1//spl phi//sub h/)/sup -1//spl phi//sub h//spl phi/~/sub h//sup /spl tau//. Further, several examples are given where Haar wavelets are used.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131892062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514542
Yih-Fang Huang
Summary form only given. This presentation is intended to address issues that are related to learning and generalization capability of ANN. It is also intended to examine the state-of-the-art and, hopefully, stimulate discussions on where research should be directed. A survey on recent developments in supervised and unsupervised learning is given. Details of both learning strategies are elaborated with regard to some classes of ANN and their applications examined. The concept of selective learning is also discussed. Generalization capability of some classes of ANN is addressed, particularly, from the viewpoint of function realization. Special attention is focused on multilayer perceptrons. Other related questions such as "How large does a network have to be to perform a desired task?" are discussed.
{"title":"Artificial neural networks-learning and generalization","authors":"Yih-Fang Huang","doi":"10.1109/APCCAS.1994.514542","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514542","url":null,"abstract":"Summary form only given. This presentation is intended to address issues that are related to learning and generalization capability of ANN. It is also intended to examine the state-of-the-art and, hopefully, stimulate discussions on where research should be directed. A survey on recent developments in supervised and unsupervised learning is given. Details of both learning strategies are elaborated with regard to some classes of ANN and their applications examined. The concept of selective learning is also discussed. Generalization capability of some classes of ANN is addressed, particularly, from the viewpoint of function realization. Special attention is focused on multilayer perceptrons. Other related questions such as \"How large does a network have to be to perform a desired task?\" are discussed.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114810492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514562
M. Kaneko, Y. Fujikawa
This paper presents a novel approach to parameter design for analog circuits. This approach is based on the peculiarity of the design equations which are linear with respect to every one of the design parameters. Once the initial feasible hyper cube of the design parameters is defined, the solution space (reduced cube) within the cube for each of design equations can be estimated by evaluating zeros only at the boundary edges of the initial cube. Furthermore, the solution space of simultaneous equations can be estimated as the intersection of reduced cubes for each equation. The proposed Boundary Search Method finds the simultaneous solution of a set of design equations by iterative reduction of the feasible cube. This method needs only specifications of minimum and maximum values of design parameters, and it may find all feasible solutions. (Conventional nonlinear programming (nonlinear optimization) needs an appropriate initial solution, and it may easily be trapped by a local optimum).
{"title":"Boundary search approach to parameter design for analog circuits","authors":"M. Kaneko, Y. Fujikawa","doi":"10.1109/APCCAS.1994.514562","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514562","url":null,"abstract":"This paper presents a novel approach to parameter design for analog circuits. This approach is based on the peculiarity of the design equations which are linear with respect to every one of the design parameters. Once the initial feasible hyper cube of the design parameters is defined, the solution space (reduced cube) within the cube for each of design equations can be estimated by evaluating zeros only at the boundary edges of the initial cube. Furthermore, the solution space of simultaneous equations can be estimated as the intersection of reduced cubes for each equation. The proposed Boundary Search Method finds the simultaneous solution of a set of design equations by iterative reduction of the feasible cube. This method needs only specifications of minimum and maximum values of design parameters, and it may find all feasible solutions. (Conventional nonlinear programming (nonlinear optimization) needs an appropriate initial solution, and it may easily be trapped by a local optimum).","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122549025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514613
Zhi-Ming Lin, Yu-Jung Huang, Kuo-Hong Hsiau
LAKE is an automatic layout generator that lays out CMOS analog integrated circuits subject to circuit layout constraints such as: matching, symmetry, signal coupling cell aspect ratio (or cell height), and specified cell input/output pin locations. Unlike most previous works, LAKE focuses on effective rules and methods that suit any type of CMOS analog circuit to be incorporated in an application-specific mixed analog digital layout system. Placement is based on the characteristics of circuit structure and the layout constraints. The proposed slot structure provides the capability of handling fully symmetric layouts. The simulated evolution process evaluates the quality of layout based detailed layout information in pursuing minimal parasitic effects on circuit performance. We test some real life examples. The design experiments have shown that LAKE can produce manual-quality analog layouts.
{"title":"LAKE: a performance-driven analog CMOS cell layout generator","authors":"Zhi-Ming Lin, Yu-Jung Huang, Kuo-Hong Hsiau","doi":"10.1109/APCCAS.1994.514613","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514613","url":null,"abstract":"LAKE is an automatic layout generator that lays out CMOS analog integrated circuits subject to circuit layout constraints such as: matching, symmetry, signal coupling cell aspect ratio (or cell height), and specified cell input/output pin locations. Unlike most previous works, LAKE focuses on effective rules and methods that suit any type of CMOS analog circuit to be incorporated in an application-specific mixed analog digital layout system. Placement is based on the characteristics of circuit structure and the layout constraints. The proposed slot structure provides the capability of handling fully symmetric layouts. The simulated evolution process evaluates the quality of layout based detailed layout information in pursuing minimal parasitic effects on circuit performance. We test some real life examples. The design experiments have shown that LAKE can produce manual-quality analog layouts.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125168817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514614
Y. Setou, Y. Nishio, A. Ushida
In this article, we investigate the synchronization phenomena in N oscillators coupled by resistors as a ring. Since the system tends to minimize the energy consumed by the coupling resistors, the phase shift must be /spl plusmn//spl pi/ and /spl plusmn/(N-1)/spl pi//N, for the case of N is even and odd respectively. In addition, only for the case of N is odd, we confirmed that the oscillation was stopped in some range of the coupling resistors. It is interesting that this phenomenon occurs for parameter values which are not too large or too small. These interesting phenomena are confirmed by both of circuit experiments and numerical calculations, and are analyzed by the averaging method theoretically.
{"title":"Synchronization phenomena in many oscillators coupled by resistors as a ring","authors":"Y. Setou, Y. Nishio, A. Ushida","doi":"10.1109/APCCAS.1994.514614","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514614","url":null,"abstract":"In this article, we investigate the synchronization phenomena in N oscillators coupled by resistors as a ring. Since the system tends to minimize the energy consumed by the coupling resistors, the phase shift must be /spl plusmn//spl pi/ and /spl plusmn/(N-1)/spl pi//N, for the case of N is even and odd respectively. In addition, only for the case of N is odd, we confirmed that the oscillation was stopped in some range of the coupling resistors. It is interesting that this phenomenon occurs for parameter values which are not too large or too small. These interesting phenomena are confirmed by both of circuit experiments and numerical calculations, and are analyzed by the averaging method theoretically.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125530242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514517
T. Dai, Ta-Sung Lee, C. Hwang
A novel beamspace radial basis function neural network for the estimation of the angle-of-arrival (AOA) of a mobile unit in cellular communications is proposed. By training the network with the data emitted from different sub-cells in the field of interest, and then collected by a set of antenna array beamformers optimum weights which lead to the best approximation of the desired response in least-square sense can be obtained. In principle, the network performs mapping from the complex input data into the desired angle response. Computer simulations demonstrate that the proposed scheme is effective in combating multipath interference.
{"title":"Novel beamspace neural network approach to mobile unit localization","authors":"T. Dai, Ta-Sung Lee, C. Hwang","doi":"10.1109/APCCAS.1994.514517","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514517","url":null,"abstract":"A novel beamspace radial basis function neural network for the estimation of the angle-of-arrival (AOA) of a mobile unit in cellular communications is proposed. By training the network with the data emitted from different sub-cells in the field of interest, and then collected by a set of antenna array beamformers optimum weights which lead to the best approximation of the desired response in least-square sense can be obtained. In principle, the network performs mapping from the complex input data into the desired angle response. Computer simulations demonstrate that the proposed scheme is effective in combating multipath interference.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116798743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514535
M. Song, K. Asada
In this paper, a design methodology of a low power 54/spl times/54 bit multiplier based on a Window Detector is proposed. This multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea is the design of a Window Detector which implements the block of data compression. The role of the Window Detector is detecting the input data, choosing the optimized output data, and driving the next stage. Furthermore, it can reduce the power consumption drastically because only one optimized operation unit (a Window) is activated. Therefore, it can be called an intelligent Window Detector. Using it, the power consumption of the proposed multiplier is reduced by about 50%, compared with that of the conventional multiplier, while the propagation delay is not much more than that of the conventional one.
{"title":"Design of a low power 54/spl times/54 bit multiplier based on an intelligent window detector","authors":"M. Song, K. Asada","doi":"10.1109/APCCAS.1994.514535","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514535","url":null,"abstract":"In this paper, a design methodology of a low power 54/spl times/54 bit multiplier based on a Window Detector is proposed. This multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea is the design of a Window Detector which implements the block of data compression. The role of the Window Detector is detecting the input data, choosing the optimized output data, and driving the next stage. Furthermore, it can reduce the power consumption drastically because only one optimized operation unit (a Window) is activated. Therefore, it can be called an intelligent Window Detector. Using it, the power consumption of the proposed multiplier is reduced by about 50%, compared with that of the conventional multiplier, while the propagation delay is not much more than that of the conventional one.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117250613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514615
A. Charoenrook, M. Soma
This paper presents a very linear and wide dynamic range BiCMOS operational transconductance amplifier for use in high performance, high frequency analog and mixed-signal applications. The design structure of the input stage together with the optimized use of BiCMOS technology provides the OTA with wide dynamic range and very low distortion properties. Comparisons between MOSFET, bipolar and BiCMOS configurations of the conversion stage are presented. The frequency response of the circuit is also analyzed in detail, including frequency compensation techniques. Simulation results using a generic BiCMOS technology illustrate a THD of less than -68 dB at Vin=/spl plusmn/4 V at 50 MHz.
{"title":"A linear wide-dynamic-range BiCMOS operational transconductance amplifier for high frequency applications","authors":"A. Charoenrook, M. Soma","doi":"10.1109/APCCAS.1994.514615","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514615","url":null,"abstract":"This paper presents a very linear and wide dynamic range BiCMOS operational transconductance amplifier for use in high performance, high frequency analog and mixed-signal applications. The design structure of the input stage together with the optimized use of BiCMOS technology provides the OTA with wide dynamic range and very low distortion properties. Comparisons between MOSFET, bipolar and BiCMOS configurations of the conversion stage are presented. The frequency response of the circuit is also analyzed in detail, including frequency compensation techniques. Simulation results using a generic BiCMOS technology illustrate a THD of less than -68 dB at Vin=/spl plusmn/4 V at 50 MHz.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116819492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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