Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514620
Y. Takeishi, T. Takeishi
A diode-switched capacitor was developed and theoretical calculations and experimental results of fundamental characteristics for its operations are reported. The experimental results of applications for RC low/high-pass filters and frequency selective/rejective filters are also shown.
{"title":"Parallel-T-diode switched-capacitor","authors":"Y. Takeishi, T. Takeishi","doi":"10.1109/APCCAS.1994.514620","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514620","url":null,"abstract":"A diode-switched capacitor was developed and theoretical calculations and experimental results of fundamental characteristics for its operations are reported. The experimental results of applications for RC low/high-pass filters and frequency selective/rejective filters are also shown.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121965746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514523
K. Shimada, T. Watanabe, M. Sengoku, T. Abe, S. Shinoda
Popular reuse partitioning systems with fixed channel assignment in cellular systems are effective to improve the channel utilization in space. This paper explores an application of the reuse partitioning scheme, in which the dynamic channel assignment technique is introduced. In the proposed strategy, a channel can be simultaneously assigned to both the inner cells and the outer cells by reducing the transmitted power in the inner cells. Also, the rearrangement method is applied to this strategy. The simulation results show that the strategy results in higher channel occupancy. The traffic carried can be increased by 1.5 times as compared with the original fixed channel assignment system.
{"title":"Dynamic channel assignment with reuse partitioning in cellular radio systems","authors":"K. Shimada, T. Watanabe, M. Sengoku, T. Abe, S. Shinoda","doi":"10.1109/APCCAS.1994.514523","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514523","url":null,"abstract":"Popular reuse partitioning systems with fixed channel assignment in cellular systems are effective to improve the channel utilization in space. This paper explores an application of the reuse partitioning scheme, in which the dynamic channel assignment technique is introduced. In the proposed strategy, a channel can be simultaneously assigned to both the inner cells and the outer cells by reducing the transmitted power in the inner cells. Also, the rearrangement method is applied to this strategy. The simulation results show that the strategy results in higher channel occupancy. The traffic carried can be increased by 1.5 times as compared with the original fixed channel assignment system.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115869466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514522
Jae-Soo Kim, I. Hwang
Two multichannel media access protocols with different frequency channels for a mobile cellular environment are investigated. MPRMA is a multichannel PRMA protocol and MSAC is a multichannel protocol with a slotted ALOHA based control channel. Fixed total bandwidth is used. For integrated services and different quality service requirements, only the voice packet can reserve the future slot during talkspurt when the information packet is transmitted successfully. A semi-Markov model was developed to study the operations of the protocols. The comparisons of these protocols are investigated through analytical models as well as discrete-event simulation in terms of the number of simultaneous users, packet dropping probability with the variations of the number of channels and the information packet size.
{"title":"Performance analysis of multichannel reservation random access protocol for mobile cellular network","authors":"Jae-Soo Kim, I. Hwang","doi":"10.1109/APCCAS.1994.514522","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514522","url":null,"abstract":"Two multichannel media access protocols with different frequency channels for a mobile cellular environment are investigated. MPRMA is a multichannel PRMA protocol and MSAC is a multichannel protocol with a slotted ALOHA based control channel. Fixed total bandwidth is used. For integrated services and different quality service requirements, only the voice packet can reserve the future slot during talkspurt when the information packet is transmitted successfully. A semi-Markov model was developed to study the operations of the protocols. The comparisons of these protocols are investigated through analytical models as well as discrete-event simulation in terms of the number of simultaneous users, packet dropping probability with the variations of the number of channels and the information packet size.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121044424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514595
J. Jou, Shung-Chih Chen
A fault simulator for large synchronous sequential circuits is presented in this paper. There are four key ideas to the fault simulator. (1) It uses the critical path tracing method to screen out the single event faults that need not map into equivalent stem faults. (2) It uses the single fault propagation method to map the traced single event faults into equivalent stem faults. (3) All the multiple event faults are dynamically ordered for each test pattern such that the faults with the same faulty effects can be put into the same packet, so as to reduce the number of events created during simulation. (4) All the packets are propagated simultaneously; therefore, each gate is simulated only once for each test pattern, and while propagating packets, equivalent stem faults are also inserted into the packets and propagated as well. A memory sharing technique is used to reduce the memory overhead. Experimental results show that our fault simulator runs faster than PROOFS, HOPE, and improved HOPE (HOPE1.1) for large synchronous sequential benchmark circuits.
{"title":"A new fault simulator for large synchronous sequential circuits","authors":"J. Jou, Shung-Chih Chen","doi":"10.1109/APCCAS.1994.514595","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514595","url":null,"abstract":"A fault simulator for large synchronous sequential circuits is presented in this paper. There are four key ideas to the fault simulator. (1) It uses the critical path tracing method to screen out the single event faults that need not map into equivalent stem faults. (2) It uses the single fault propagation method to map the traced single event faults into equivalent stem faults. (3) All the multiple event faults are dynamically ordered for each test pattern such that the faults with the same faulty effects can be put into the same packet, so as to reduce the number of events created during simulation. (4) All the packets are propagated simultaneously; therefore, each gate is simulated only once for each test pattern, and while propagating packets, equivalent stem faults are also inserted into the packets and propagated as well. A memory sharing technique is used to reduce the memory overhead. Experimental results show that our fault simulator runs faster than PROOFS, HOPE, and improved HOPE (HOPE1.1) for large synchronous sequential benchmark circuits.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124922242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514534
C. Chen, Anup Kumar
Previous research in VLSI adders has identified the existence of tradeoffs between asymptotic area and asymptotic time. This paper presents a systematic method of implementing a BiCMOS carry look-ahead adder design which is optimized with respect to area and time. Since the adder circuits usually lie on the critical path delay of carry generator due to large fan-out and output capacitances, speed determines the clock cycle time. In view of the driving capability of bipolar transistors, the BiCMOS buffer/driver and BiCMOS cells are chosen and modified to drive large fan-out or heavy capacitive loads. Combining the bipolar and CMOS circuits on a single chip, the performance of the carry generator circuit is improved due to the acceleration of the critical path. A comparison between BiCMOS and CMOS parallel adders is made. It is shown that the parallel adders designed using the BiCMOS cells achieved improvement in the performance, by shortening the critical path delay by 32.486% in the case of 16-bit, 58.365% in the case of 32-bit and 79.944% in the case of 66-bit where the delay is calculated as the average propagation delay measured from HSPICE simulations.
{"title":"Area-time optimal digital BiCMOS carry look-ahead adder","authors":"C. Chen, Anup Kumar","doi":"10.1109/APCCAS.1994.514534","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514534","url":null,"abstract":"Previous research in VLSI adders has identified the existence of tradeoffs between asymptotic area and asymptotic time. This paper presents a systematic method of implementing a BiCMOS carry look-ahead adder design which is optimized with respect to area and time. Since the adder circuits usually lie on the critical path delay of carry generator due to large fan-out and output capacitances, speed determines the clock cycle time. In view of the driving capability of bipolar transistors, the BiCMOS buffer/driver and BiCMOS cells are chosen and modified to drive large fan-out or heavy capacitive loads. Combining the bipolar and CMOS circuits on a single chip, the performance of the carry generator circuit is improved due to the acceleration of the critical path. A comparison between BiCMOS and CMOS parallel adders is made. It is shown that the parallel adders designed using the BiCMOS cells achieved improvement in the performance, by shortening the critical path delay by 32.486% in the case of 16-bit, 58.365% in the case of 32-bit and 79.944% in the case of 66-bit where the delay is calculated as the average propagation delay measured from HSPICE simulations.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114053750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514526
Mao-Fu Lai, Yan-Pei Wu, C. Hsieh
This paper presents a systolic architecture for the squared-error clustering algorithm. The proposed architecture exploits a 2-dimensional systolic array which uses intensively parallel and pipelined processing. The architecture dramatically reduces the huge number of processing elements required by previous architectures. Furthermore, the same organization can be utilized for applications where the number of input patterns is varied. In addition, the time complexity of our architecture is reduced in comparison with earlier architectures. A cost-effective VLSI implementation for high speed clustering analysis can be realized with considerably less circuit complexity using this novel architecture.
{"title":"Design of clustering analyzer based on systolic array architecture","authors":"Mao-Fu Lai, Yan-Pei Wu, C. Hsieh","doi":"10.1109/APCCAS.1994.514526","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514526","url":null,"abstract":"This paper presents a systolic architecture for the squared-error clustering algorithm. The proposed architecture exploits a 2-dimensional systolic array which uses intensively parallel and pipelined processing. The architecture dramatically reduces the huge number of processing elements required by previous architectures. Furthermore, the same organization can be utilized for applications where the number of input patterns is varied. In addition, the time complexity of our architecture is reduced in comparison with earlier architectures. A cost-effective VLSI implementation for high speed clustering analysis can be realized with considerably less circuit complexity using this novel architecture.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126992021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514603
I. Jou, Ron-Yi Liu, Chung-Yu Wu
In this paper, a Spatiotemporal Probabilistic Neural Network (SPNN) is proposed for spatiotemporal pattern recognition. This new model is developed by applying the concept of Gaussian density function to the network structure of the SPR (Spatiotemporal Pattern Recognition). The main advantages of this new model include faster training and recalling process for patterns, and the overall architecture is also simple, modular, regular, locally connected for VLSI implementation. The CMOS current-mode IC technology is used to implement the SPNN to achieve the objective of minimum classification error in a more direct manner. In this design, neural computation is performed in analog circuits while template information is stored in digital circuits. One set of independent speaker isolated (Mandarin digit) speech database is used as an example to demonstrate the superiority of the neural networks for spatiotemporal pattern recognition.
{"title":"CMOS implementation of neural networks for speech recognition","authors":"I. Jou, Ron-Yi Liu, Chung-Yu Wu","doi":"10.1109/APCCAS.1994.514603","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514603","url":null,"abstract":"In this paper, a Spatiotemporal Probabilistic Neural Network (SPNN) is proposed for spatiotemporal pattern recognition. This new model is developed by applying the concept of Gaussian density function to the network structure of the SPR (Spatiotemporal Pattern Recognition). The main advantages of this new model include faster training and recalling process for patterns, and the overall architecture is also simple, modular, regular, locally connected for VLSI implementation. The CMOS current-mode IC technology is used to implement the SPNN to achieve the objective of minimum classification error in a more direct manner. In this design, neural computation is performed in analog circuits while template information is stored in digital circuits. One set of independent speaker isolated (Mandarin digit) speech database is used as an example to demonstrate the superiority of the neural networks for spatiotemporal pattern recognition.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127568418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514610
H.H. Chen, C. K. Wong
In the design of thermal conduction modules, chips are interconnected through thin-film layers and glass-ceramic layers. The total amount of noise on the package consists of not only the crosstalk between adjacent signal lines in the X and Y directions, but also the coupled noise between adjacent pins and vias in the Z direction. While the crosstalk between adjacent wires can be minimized by reducing wire length and increasing wire spacing, the via noise problem has never been considered during layout design. This paper introduces the via noise constraints for physical design, and proposes a net ordering and layer assignment method to minimize the via coupled noise in thermal conduction module (TCM) design.
{"title":"Minimizing via coupled noise in high performance thermal conduction module design","authors":"H.H. Chen, C. K. Wong","doi":"10.1109/APCCAS.1994.514610","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514610","url":null,"abstract":"In the design of thermal conduction modules, chips are interconnected through thin-film layers and glass-ceramic layers. The total amount of noise on the package consists of not only the crosstalk between adjacent signal lines in the X and Y directions, but also the coupled noise between adjacent pins and vias in the Z direction. While the crosstalk between adjacent wires can be minimized by reducing wire length and increasing wire spacing, the via noise problem has never been considered during layout design. This paper introduces the via noise constraints for physical design, and proposes a net ordering and layer assignment method to minimize the via coupled noise in thermal conduction module (TCM) design.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133508965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514513
H. Yasuda
Summary form only given, as follows. Standardization of MPEG2 has been almost completed and it is expected to be the most important technology for fascination multimedia services in telecommunication, broadcasting and interdisciplinary services areas. The MPEG2 coding algorithm for video and audio signals is outlined and the main features of the MPEG2 standard are presented. The LSI technology required to implement functions for MPEG2 is described, and the current status of the development for LSI chips in the world is touched upon. Finally some pilot systems in Japan to provide multimedia services using MPEG2 standard are introduced.
{"title":"Audio visual coding technologies and LSI circuits based on MPEG2 standard to implement multimedia services","authors":"H. Yasuda","doi":"10.1109/APCCAS.1994.514513","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514513","url":null,"abstract":"Summary form only given, as follows. Standardization of MPEG2 has been almost completed and it is expected to be the most important technology for fascination multimedia services in telecommunication, broadcasting and interdisciplinary services areas. The MPEG2 coding algorithm for video and audio signals is outlined and the main features of the MPEG2 standard are presented. The LSI technology required to implement functions for MPEG2 is described, and the current status of the development for LSI chips in the world is touched upon. Finally some pilot systems in Japan to provide multimedia services using MPEG2 standard are introduced.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133705610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514598
Wen-Bin Lin, T. Kuo, Chuen-Hsien Su, Ji-Rong Chen
A novel design and analysis method for a 4th-order sigma-delta modulator (SDM or DSM) based on leapfrog topologies is presented. First, we discuss the arrangement of delayed and non-delayed type integrators for the leapfrog topologies and then determine a stable topology for analysis. Using the theoretical analysis including DC analysis and the relationship of roots and coefficients of an equation, the ranges of the loop coefficients which stabilize the system are determined. The numerical analysis is then adopted to analyze the ranges of the loop coefficients. According to the above analysis methods, the stable regions in frequency domain are easily determined. From these stable regions, a set of coefficients for VLSI implementation is chosen. The chosen loop coefficients of the leapfrog topologies are very simple and such that circuit complexity is reduced, To component variations, the performance of leapfrog SDM is less sensitive than that of leapfrog filter. Hence, circuit design becomes simpler and more effective. Behavior simulation shows that a 4th-order leapfrog topology can achieve the inband signal-to-noise ratio (SNR) more than 110 dB and the dynamic range (DR) more than 110 dB for 640 oversampling ratio. Besides, it also shows that both the gain ripple for inband signal and group delay variation are negligible, Hence, the leapfrog topologies can be used in ultra-high resolution signal processing system such as speech application, codec in digital cellular phone, and high precision measurement equipment.
{"title":"Design and analysis of fourth-order leapfrog topologies for sigma-delta A/D converters","authors":"Wen-Bin Lin, T. Kuo, Chuen-Hsien Su, Ji-Rong Chen","doi":"10.1109/APCCAS.1994.514598","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514598","url":null,"abstract":"A novel design and analysis method for a 4th-order sigma-delta modulator (SDM or DSM) based on leapfrog topologies is presented. First, we discuss the arrangement of delayed and non-delayed type integrators for the leapfrog topologies and then determine a stable topology for analysis. Using the theoretical analysis including DC analysis and the relationship of roots and coefficients of an equation, the ranges of the loop coefficients which stabilize the system are determined. The numerical analysis is then adopted to analyze the ranges of the loop coefficients. According to the above analysis methods, the stable regions in frequency domain are easily determined. From these stable regions, a set of coefficients for VLSI implementation is chosen. The chosen loop coefficients of the leapfrog topologies are very simple and such that circuit complexity is reduced, To component variations, the performance of leapfrog SDM is less sensitive than that of leapfrog filter. Hence, circuit design becomes simpler and more effective. Behavior simulation shows that a 4th-order leapfrog topology can achieve the inband signal-to-noise ratio (SNR) more than 110 dB and the dynamic range (DR) more than 110 dB for 640 oversampling ratio. Besides, it also shows that both the gain ripple for inband signal and group delay variation are negligible, Hence, the leapfrog topologies can be used in ultra-high resolution signal processing system such as speech application, codec in digital cellular phone, and high precision measurement equipment.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115045912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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