Polymorphic electronics provides a new way for obtaining circuits that are able to perform two or more functions depending on the environment in which they operate. These functions can be activated under certain conditions by changing control parameters of the circuit (such as temperature, power supply voltage, light etc.). Existing polymorphic gates are difficult to use as building blocks in complex digital circuits. In this paper, some modifications of existing polymorphic gates are proposed in order to utilize them in non-trivial digital multifunctional circuits. The presented multifunctional circuits composed of these gates represent the most complex multifunctional circuits available nowadays. In particular, NAND/NOR and AND/OR polymorphic gates controlled by the power supply voltage are discussed and used in circuits such as the five-bit majority/AND circuit and three-bit multiplier/six-bit sorting network circuit
{"title":"Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage","authors":"L. Sekanina, Lukás Starecek, Z. Gajda, Z. Kotásek","doi":"10.1109/AHS.2006.35","DOIUrl":"https://doi.org/10.1109/AHS.2006.35","url":null,"abstract":"Polymorphic electronics provides a new way for obtaining circuits that are able to perform two or more functions depending on the environment in which they operate. These functions can be activated under certain conditions by changing control parameters of the circuit (such as temperature, power supply voltage, light etc.). Existing polymorphic gates are difficult to use as building blocks in complex digital circuits. In this paper, some modifications of existing polymorphic gates are proposed in order to utilize them in non-trivial digital multifunctional circuits. The presented multifunctional circuits composed of these gates represent the most complex multifunctional circuits available nowadays. In particular, NAND/NOR and AND/OR polymorphic gates controlled by the power supply voltage are discussed and used in circuits such as the five-bit majority/AND circuit and three-bit multiplier/six-bit sorting network circuit","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115713089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose and demonstrate a method of automatic alignment for multiple optical components using a genetic algorithm. The connection between two optical components requires extremely precise alignment in the order of sub-micron-meters. It, therefore, typically takes an experienced technician around 30 to 60 minutes to manually align optical components. Although automatic fiber alignment systems are being developed, they are not practical for use when the degrees of freedom in the alignment of multiple optical components are large. To overcome this difficulty, we have devised a method of automatic alignment for multiple optical components using a genetic algorithm. In a conducted experiment, we successfully connected three optical components within a short span of time (3 minutes) through simultaneous alignment
{"title":"Automatic Alignment of Multiple Optical Components Using Genetic Algorithm","authors":"H. Nosato, M. Murakawa, T. Higuchi","doi":"10.1109/AHS.2006.27","DOIUrl":"https://doi.org/10.1109/AHS.2006.27","url":null,"abstract":"We propose and demonstrate a method of automatic alignment for multiple optical components using a genetic algorithm. The connection between two optical components requires extremely precise alignment in the order of sub-micron-meters. It, therefore, typically takes an experienced technician around 30 to 60 minutes to manually align optical components. Although automatic fiber alignment systems are being developed, they are not practical for use when the degrees of freedom in the alignment of multiple optical components are large. To overcome this difficulty, we have devised a method of automatic alignment for multiple optical components using a genetic algorithm. In a conducted experiment, we successfully connected three optical components within a short span of time (3 minutes) through simultaneous alignment","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124285100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A simple technique is proposed to adjust coefficients of transfer functions in switched-capacitor circuits. Transfer-function-coefficients are defined by capacitor-values considering full-charge transfer among capacitors. The proposed tuning technique in this paper is based on adjusting the amount of charge transferred from one capacitor to next capacitor. By all means, the net charge transferred in switched-capacitor circuits will effectively modify transfer function of a particular block without modifying individual capacitor values
{"title":"A Tuning Technique for Switched-Capacitor Circuits","authors":"M. Keskin, N. Keskin","doi":"10.1109/AHS.2006.13","DOIUrl":"https://doi.org/10.1109/AHS.2006.13","url":null,"abstract":"A simple technique is proposed to adjust coefficients of transfer functions in switched-capacitor circuits. Transfer-function-coefficients are defined by capacitor-values considering full-charge transfer among capacitors. The proposed tuning technique in this paper is based on adjusting the amount of charge transferred from one capacitor to next capacitor. By all means, the net charge transferred in switched-capacitor circuits will effectively modify transfer function of a particular block without modifying individual capacitor values","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127276474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an on-chip processor. This gives higher flexibility compared to implementing an evolutionary algorithm directly in hardware, since the parameters and behaviour of the algorithm can easily be changed, and complex operators are more feasible to implement. In this paper a Xilinx MicroBlaze soft core processor is used, and the system is implemented in a Xilinx FPGA. A suitable hardware architecture for image recognition has been proposed, and it is applied to a face recognition task. Data buses and higher level functions have been utilized in order to reduce the search space for the evolutionary algorithm. Experiments have been performed on the physical device, with software running in parallel with fitness computation in digital logic. Results show that the MicroBlaze system evolves at half the speed of a Pentium M system running at 17 times the FPGA clock frequency. The distinction of a certain face from others is performed at 94.9% accuracy. In addition, the possibilities for evolutionary adaptation over time are explored by introducing changes in the training set. The system shows ability to adapt to these changes
{"title":"On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition","authors":"K. Glette, J. Tørresen, M. Yasunaga, Y. Yamaguchi","doi":"10.1109/AHS.2006.55","DOIUrl":"https://doi.org/10.1109/AHS.2006.55","url":null,"abstract":"To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an on-chip processor. This gives higher flexibility compared to implementing an evolutionary algorithm directly in hardware, since the parameters and behaviour of the algorithm can easily be changed, and complex operators are more feasible to implement. In this paper a Xilinx MicroBlaze soft core processor is used, and the system is implemented in a Xilinx FPGA. A suitable hardware architecture for image recognition has been proposed, and it is applied to a face recognition task. Data buses and higher level functions have been utilized in order to reduce the search space for the evolutionary algorithm. Experiments have been performed on the physical device, with software running in parallel with fitness computation in digital logic. Results show that the MicroBlaze system evolves at half the speed of a Pentium M system running at 17 times the FPGA clock frequency. The distinction of a certain face from others is performed at 94.9% accuracy. In addition, the possibilities for evolutionary adaptation over time are explored by introducing changes in the training set. The system shows ability to adapt to these changes","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124825079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Adaptive systems based on reconfigurable hardware provide an attractive platform for the implementation of mechatronic controller functionality. Such control algorithms comprise various operating states, parameter sets or algorithms that depend on changing external conditions. This paper presents an implemented and tested adaptive mechatronic control system, supporting the partial reconfiguration of real-time controller functionality. It provides a distributed reconfiguration and activation management as well as on/off-chip communication solutions including a delta-sigma ADC and an USB 2.0 interface. All functionality and the reconfiguration management are implemented directly in hardware using bit serial methods. This approach avoids real-time problems and takes advantage of high level parallel signal processing
{"title":"An Adaptive FPGA-Based Mechatronic Control System Supporting Partial Reconfiguration of Controller Functionalities","authors":"S. Toscher, T. Reinemann, R. Kasper","doi":"10.1109/AHS.2006.17","DOIUrl":"https://doi.org/10.1109/AHS.2006.17","url":null,"abstract":"Adaptive systems based on reconfigurable hardware provide an attractive platform for the implementation of mechatronic controller functionality. Such control algorithms comprise various operating states, parameter sets or algorithms that depend on changing external conditions. This paper presents an implemented and tested adaptive mechatronic control system, supporting the partial reconfiguration of real-time controller functionality. It provides a distributed reconfiguration and activation management as well as on/off-chip communication solutions including a delta-sigma ADC and an USB 2.0 interface. All functionality and the reconfiguration management are implemented directly in hardware using bit serial methods. This approach avoids real-time problems and takes advantage of high level parallel signal processing","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115344239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It has been a decade since the need of VLSI design intellectual property (IP) protection was identified. The goals of IP protection are: 1) to enable IP providers to protect their IPs against unauthorized use, 2) to protect all types of design data used to produce and deliver IPs, 3) to detect the use of IPs, and 4) to trace the use of IPs. There are significant advances from both industry and academic towards these goals. However, do we have solutions to achieve all these goals? What are the current state-of-the-art IP protection techniques? Do they meet the protection requirement designers sought for? What are the (new) challenges and is there any feasible answer to them in the foreseeable future? This paper addresses these questions and provides possible solutions mainly from academia point of view. Several successful industry practice and ongoing efforts are also discussed briefly
{"title":"VLSI Design IP Protection: Solutions, New Challenges, and Opportunities","authors":"Lin Yuan, G. Qu, L. Ghouti, A. Bouridane","doi":"10.1109/AHS.2006.77","DOIUrl":"https://doi.org/10.1109/AHS.2006.77","url":null,"abstract":"It has been a decade since the need of VLSI design intellectual property (IP) protection was identified. The goals of IP protection are: 1) to enable IP providers to protect their IPs against unauthorized use, 2) to protect all types of design data used to produce and deliver IPs, 3) to detect the use of IPs, and 4) to trace the use of IPs. There are significant advances from both industry and academic towards these goals. However, do we have solutions to achieve all these goals? What are the current state-of-the-art IP protection techniques? Do they meet the protection requirement designers sought for? What are the (new) challenges and is there any feasible answer to them in the foreseeable future? This paper addresses these questions and provides possible solutions mainly from academia point of view. Several successful industry practice and ongoing efforts are also discussed briefly","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"340 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116073513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the development of a wireless communication system, the RF identification tag, built and tested in Heriot-Watt University, Edinburgh. The design flow commences in SPIN, a high level model-checking tool at present deployed towards the verification of safety critical software designs including NASA missions. The formally verified model of the application is then enhanced with software based monitoring architectures comparable with that applied in conventional firmware development such as the watchdog timer defending rational control related execution of the high level system representation. Following automated synthesis into hardware (HDL) with the aid of an ESL method, the generated RTL design can be further protected against increased levels of radiation and SEUs with the aid of the xTMR tool. It is claimed that a development route of this type promotes high levels of algorithmic testability and reliability attained via fault prevention means in the model checking process as well as multi-layered run-time monitoring and fault management strategies leveraging upon the design on the vertical implementation phase. The application developed in the proposed lifecycle and targeting the FPGA technology is finally tested under a lab emulated EMI scheme and system survivability is examined and quantified. Reliability is then estimated and analyzed in the CASRE tool (developed by JPL NASA)
{"title":"SW-HW Co-design and Fault Tolerant Implementation for the LRID Wireless Communication System","authors":"S. Skoulaxinos","doi":"10.1109/AHS.2006.68","DOIUrl":"https://doi.org/10.1109/AHS.2006.68","url":null,"abstract":"This paper presents the development of a wireless communication system, the RF identification tag, built and tested in Heriot-Watt University, Edinburgh. The design flow commences in SPIN, a high level model-checking tool at present deployed towards the verification of safety critical software designs including NASA missions. The formally verified model of the application is then enhanced with software based monitoring architectures comparable with that applied in conventional firmware development such as the watchdog timer defending rational control related execution of the high level system representation. Following automated synthesis into hardware (HDL) with the aid of an ESL method, the generated RTL design can be further protected against increased levels of radiation and SEUs with the aid of the xTMR tool. It is claimed that a development route of this type promotes high levels of algorithmic testability and reliability attained via fault prevention means in the model checking process as well as multi-layered run-time monitoring and fault management strategies leveraging upon the design on the vertical implementation phase. The application developed in the proposed lifecycle and targeting the FPGA technology is finally tested under a lab emulated EMI scheme and system survivability is examined and quantified. Reliability is then estimated and analyzed in the CASRE tool (developed by JPL NASA)","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127998943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has shown one of its main deficiencies, when applied to solving real world applications, to be scalability. In the past few years several techniques have been proposed to avoid and/or solve this problem. Generalized disjunction decomposition (GDD) is one of these proposed methods. GDD was successful for the evolution of large combinational logic circuits based on a FPGA structure when used together with bi-directional incremental evolution and with (1+lambda) evolution strategy. In this paper a modified generalized disjunction decomposition, together with a recently introduced multi-population genetic algorithm, are implemented and tested for its scalability for solving large combinational logic circuits based on programmable logic array (PLA) structures
{"title":"Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures","authors":"E. Stomeo, T. Kalganova, Cyrille Lambert","doi":"10.1109/AHS.2006.47","DOIUrl":"https://doi.org/10.1109/AHS.2006.47","url":null,"abstract":"Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has shown one of its main deficiencies, when applied to solving real world applications, to be scalability. In the past few years several techniques have been proposed to avoid and/or solve this problem. Generalized disjunction decomposition (GDD) is one of these proposed methods. GDD was successful for the evolution of large combinational logic circuits based on a FPGA structure when used together with bi-directional incremental evolution and with (1+lambda) evolution strategy. In this paper a modified generalized disjunction decomposition, together with a recently introduced multi-population genetic algorithm, are implemented and tested for its scalability for solving large combinational logic circuits based on programmable logic array (PLA) structures","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128812124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a new approach to routing operations in wireless sensor networks (WSNs). We have developed a routing scheme and adapted ant colony optimization (ACO) algorithm to this scheme to get a dynamic and reliable routing protocol. We have also implemented our approach to a small sized hardware component as a router chip to propose sensor node designers an easy handling of WSN routing operations. The chip is tested and its performance results are obtained by using proteus simulation program. The ACO approach and its hardware implementation seem to provide a promising solution for node designers to operate routing tasks easily and effectively
{"title":"Routing in Wireless Sensor Networks Using Ant Colony Optimization","authors":"S. Okdem, D. Karaboğa","doi":"10.1109/AHS.2006.63","DOIUrl":"https://doi.org/10.1109/AHS.2006.63","url":null,"abstract":"This paper introduces a new approach to routing operations in wireless sensor networks (WSNs). We have developed a routing scheme and adapted ant colony optimization (ACO) algorithm to this scheme to get a dynamic and reliable routing protocol. We have also implemented our approach to a small sized hardware component as a router chip to propose sensor node designers an easy handling of WSN routing operations. The chip is tested and its performance results are obtained by using proteus simulation program. The ACO approach and its hardware implementation seem to provide a promising solution for node designers to operate routing tasks easily and effectively","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133781343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent development of wireless sensor networks (WSN) has led to the appearance of many application specific communication protocols which must be energy-efficient. Among those protocols developed for WSN, LEACH (low energy adaptive clustering hierarchy) protocol is one of the most promising protocols. In this paper, a novel self-organizing energy efficient hybrid protocol based on LEACH is presented, combining cluster based architecture and multiple-hop routing. Multi-hop routing is utilized for inter-cluster communication between cluster heads and the base station, instead of direct transmission in order to minimize transmission energy. Besides, this protocol adds some mechanisms to CSMA/CD (carrier sense multiple access with collision detection) so as to avoid collisions, instead of using other more complicated MAC protocols during the period of cluster formation. The performance of the novel protocol is evaluated and compared with LEACH. Simulation results demonstrate that our novel protocol can achieve better performance on energy efficiency and the lifetime of WSN
近年来无线传感器网络(WSN)的发展导致了许多特定应用的通信协议的出现，这些协议必须是节能的。在针对无线传感器网络开发的协议中，LEACH(低能量自适应聚类层次)协议是最有前途的协议之一。本文提出了一种基于LEACH的自组织节能混合协议，将基于集群的架构与多跳路由相结合。簇头与基站之间的簇间通信采用多跳路由，而不是直接传输，以减少传输能量。此外，该协议在CSMA/CD (carrier - sense multiple access with collision detection)基础上增加了一些避免碰撞的机制，而不是在集群形成期间使用其他更复杂的MAC协议。对新协议的性能进行了评估，并与LEACH进行了比较。仿真结果表明，该协议在无线传感器网络的能效和寿命方面取得了较好的效果
{"title":"A Novel Self-Organizing Hybrid Network Protocol for Wireless Sensor Networks","authors":"Jichuan Zhao, A. Erdogan","doi":"10.1109/AHS.2006.11","DOIUrl":"https://doi.org/10.1109/AHS.2006.11","url":null,"abstract":"Recent development of wireless sensor networks (WSN) has led to the appearance of many application specific communication protocols which must be energy-efficient. Among those protocols developed for WSN, LEACH (low energy adaptive clustering hierarchy) protocol is one of the most promising protocols. In this paper, a novel self-organizing energy efficient hybrid protocol based on LEACH is presented, combining cluster based architecture and multiple-hop routing. Multi-hop routing is utilized for inter-cluster communication between cluster heads and the base station, instead of direct transmission in order to minimize transmission energy. Besides, this protocol adds some mechanisms to CSMA/CD (carrier sense multiple access with collision detection) so as to avoid collisions, instead of using other more complicated MAC protocols during the period of cluster formation. The performance of the novel protocol is evaluated and compared with LEACH. Simulation results demonstrate that our novel protocol can achieve better performance on energy efficiency and the lifetime of WSN","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115380123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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