We present a platform for implementing low power self-tuning analog proportional-integral-derivative controllers. By using a model-free tuning method, the platform overcomes problems typically associated with reconfigurable analog arrays. Unlike a self-tuning digital PID controller, our prototype controller combines the advantages of low power, no quantization noise, high bandwidth and high speed. The prototype hardware uses a commercially available field programmable analog array and particle swarm optimization as the tuning method. We show that a self-tuned analog PID controller can outperform a hand-tuned solution and demonstrate adaptability to plant drift
{"title":"A Self-Tuning Analog Proportional-Integral-Derivative (PID) Controller","authors":"V. Aggarwal, Meng Mao, Una-May O’Reilly","doi":"10.1109/AHS.2006.12","DOIUrl":"https://doi.org/10.1109/AHS.2006.12","url":null,"abstract":"We present a platform for implementing low power self-tuning analog proportional-integral-derivative controllers. By using a model-free tuning method, the platform overcomes problems typically associated with reconfigurable analog arrays. Unlike a self-tuning digital PID controller, our prototype controller combines the advantages of low power, no quantization noise, high bandwidth and high speed. The prototype hardware uses a commercially available field programmable analog array and particle swarm optimization as the tuning method. We show that a self-tuned analog PID controller can outperform a hand-tuned solution and demonstrate adaptability to plant drift","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134464539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Trefzer, Jörg Langeheine, K. Meier, J. Schemmel
This paper gives an overview over the progress that has been made by the Heidelberg FPTA group within the field of analog evolvable hardware. Achievements are the design of a CMOS configurable transistor array (FPTA), the development of evolutionary algorithms (EAs) for analog circuit synthesis and the implementation of a modular framework, which makes it possible to use various substrates and simulation models for evolution experiments. The improvement of the EA is shown by comparing the performance of three implementations in evolving comparators. Additionally, results, obtained from the FPTA for the evolution of oscillators from scratch, are presented as an example for the successful application of the multi-objective Turtle GA. Finally, it is shown that a simplified software model of the Heidelberg FPTA is suitable to assess the real hardware, indicated by the fact that both substrates perform equally well in finding good solutions for comparators. This work aims at creating a customizable, modular framework that facilitates research on the performance and evolvability of possible FPTA topologies in the future
{"title":"A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures.","authors":"M. Trefzer, Jörg Langeheine, K. Meier, J. Schemmel","doi":"10.1109/AHS.2006.8","DOIUrl":"https://doi.org/10.1109/AHS.2006.8","url":null,"abstract":"This paper gives an overview over the progress that has been made by the Heidelberg FPTA group within the field of analog evolvable hardware. Achievements are the design of a CMOS configurable transistor array (FPTA), the development of evolutionary algorithms (EAs) for analog circuit synthesis and the implementation of a modular framework, which makes it possible to use various substrates and simulation models for evolution experiments. The improvement of the EA is shown by comparing the performance of three implementations in evolving comparators. Additionally, results, obtained from the FPTA for the evolution of oscillators from scratch, are presented as an example for the successful application of the multi-objective Turtle GA. Finally, it is shown that a simplified software model of the Heidelberg FPTA is suitable to assess the real hardware, indicated by the fact that both substrates perform equally well in finding good solutions for comparators. This work aims at creating a customizable, modular framework that facilitates research on the performance and evolvability of possible FPTA topologies in the future","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128820065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Distributed satellite systems are considered a promising new direction in spacecraft architecture design. Pico-satellite constellations flying in low Earth orbit (LEO) could become an efficient and low-cost solution to Earth observation and remote sensing in the future. There is a pressing need for condition-based maintenance, self-repair and upgrade capabilities on-board satellites in order to enable future space applications. In this paper we present a methodology for onboard partial run-time reconfiguration to enable onboard system-level functional changes ensuring correct operation, longer life and higher quality of service. The technique of partial run-time reconfiguration is introduced and a remote reconfiguration methodology is described. The architecture of an FPGA-based reconfigurable SoC design for on-board computing is outlined. A case study, which demonstrates the feasibility of the approach, is presented
{"title":"On-Board Partial Run-Time Reconfiguration for Pico-Satellite Constellations","authors":"T. Vladimirova, Xiaofeng Wu","doi":"10.1109/AHS.2006.54","DOIUrl":"https://doi.org/10.1109/AHS.2006.54","url":null,"abstract":"Distributed satellite systems are considered a promising new direction in spacecraft architecture design. Pico-satellite constellations flying in low Earth orbit (LEO) could become an efficient and low-cost solution to Earth observation and remote sensing in the future. There is a pressing need for condition-based maintenance, self-repair and upgrade capabilities on-board satellites in order to enable future space applications. In this paper we present a methodology for onboard partial run-time reconfiguration to enable onboard system-level functional changes ensuring correct operation, longer life and higher quality of service. The technique of partial run-time reconfiguration is introduced and a remote reconfiguration methodology is described. The architecture of an FPGA-based reconfigurable SoC design for on-board computing is outlined. A case study, which demonstrates the feasibility of the approach, is presented","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130489054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The application of evolutionary techniques to the design of custom processing elements bears a strong relation to the natural process that led to the co-evolution of cells and genomes in biological organisms. As such, it is an interesting avenue for an effective application of evolutionary approaches in the domain of hardware design. The architecture of conventional non-configurable processors, however, is ill-adapted to this kind of approach, as evolution can operate exclusively on the software (the genome) and not on the hardware that executes it, leading to scalability issues that seem very difficult to overcome. Building on a family of configurable processors we developed in the past years, in this article we introduce a design methodology that allows the architecture of the processor to co-evolve together with the code to be executed
{"title":"Hardware/Software Coevolution of Genome Programs and Cellular Processors","authors":"G. Tempesti, Pierre-André Mudry, G. Zufferey","doi":"10.1109/AHS.2006.51","DOIUrl":"https://doi.org/10.1109/AHS.2006.51","url":null,"abstract":"The application of evolutionary techniques to the design of custom processing elements bears a strong relation to the natural process that led to the co-evolution of cells and genomes in biological organisms. As such, it is an interesting avenue for an effective application of evolutionary approaches in the domain of hardware design. The architecture of conventional non-configurable processors, however, is ill-adapted to this kind of approach, as evolution can operate exclusively on the software (the genome) and not on the hardware that executes it, leading to scalability issues that seem very difficult to overcome. Building on a family of configurable processors we developed in the past years, in this article we introduce a design methodology that allows the architecture of the processor to co-evolve together with the code to be executed","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116345220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Ismailoglu, O. Benderli, S. Yesil, R. Sever, B. Okcan, O. Sengul, R. Öktem
GEZGIN and GEZGIN-2 are real-time multi-spectral image processing subsystems developed for BILSAT-1 and RASAT satellites respectively, the first two Earth observing small satellites of Turkey. Main functionality of these subsystems is to compress in real-time multi-spectral images received concurrently from imagers, using JPEG2000 image compression algorithm. The compression features are controlled through user-supplied parameters uploaded in-orbit, so that the compression rate could be adapted to bandwidth, image quality and other mission requirements. GEZGIN employs both reconfigurable hardware and a DSP processor for image processing, where as the more advanced GEZGIN-2 contains full integration of the JPEG2000 processing path plus other image pre-processing features on reconfigurable hardware, hence offering increased performance and full reconfigurability in orbit. Both systems demonstrate space-tailored architectures for implementing image processing functions where adaptability becomes the crucial issue determining robustness, flexibility and survivability of the system
{"title":"GEZGIN & GEZGIN-2: Adaptive Real-Time Image Processing Subsystems for Earth Observing Small Satellites","authors":"A. Ismailoglu, O. Benderli, S. Yesil, R. Sever, B. Okcan, O. Sengul, R. Öktem","doi":"10.1109/AHS.2006.49","DOIUrl":"https://doi.org/10.1109/AHS.2006.49","url":null,"abstract":"GEZGIN and GEZGIN-2 are real-time multi-spectral image processing subsystems developed for BILSAT-1 and RASAT satellites respectively, the first two Earth observing small satellites of Turkey. Main functionality of these subsystems is to compress in real-time multi-spectral images received concurrently from imagers, using JPEG2000 image compression algorithm. The compression features are controlled through user-supplied parameters uploaded in-orbit, so that the compression rate could be adapted to bandwidth, image quality and other mission requirements. GEZGIN employs both reconfigurable hardware and a DSP processor for image processing, where as the more advanced GEZGIN-2 contains full integration of the JPEG2000 processing path plus other image pre-processing features on reconfigurable hardware, hence offering increased performance and full reconfigurability in orbit. Both systems demonstrate space-tailored architectures for implementing image processing functions where adaptability becomes the crucial issue determining robustness, flexibility and survivability of the system","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"77 17","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131472401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A low power VLSI implementation of reconfigurable complex continuous wavelet transform (CWT) algorithm to generate the two dimensional time scale representation of a one dimensional signal is introduced. The CWT is computationally intensive process. The CWT processor presented in this paper employs a bank of correlators. The correlators which are not needed in a certain transform are disabled to save power. So power consumption of the CWT processor depends on the number of scales. The processor has been implemented and synthesized using ALCATEL 035mu technology. Matlab, RTL and netlist simulation results verify that the implemented algorithm has the potential to be utilized as a wavelet coprocessor for fast time-scale analysis in real-time
{"title":"Power Driven Reconfigurable Complex Continuous Wavelet Transform","authors":"N. Aydin, T. Arslan","doi":"10.1109/AHS.2006.58","DOIUrl":"https://doi.org/10.1109/AHS.2006.58","url":null,"abstract":"A low power VLSI implementation of reconfigurable complex continuous wavelet transform (CWT) algorithm to generate the two dimensional time scale representation of a one dimensional signal is introduced. The CWT is computationally intensive process. The CWT processor presented in this paper employs a bank of correlators. The correlators which are not needed in a certain transform are disabled to save power. So power consumption of the CWT processor depends on the number of scales. The processor has been implemented and synthesized using ALCATEL 035mu technology. Matlab, RTL and netlist simulation results verify that the implemented algorithm has the potential to be utilized as a wavelet coprocessor for fast time-scale analysis in real-time","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130180292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. This paper argues that it is technologically possible to build artificial brains at relatively low cost. The proposed approach to doing this is to evolve large numbers (tens of thousands) of neural network modules, each with its own simple function, and then interconnect them inside a computer that would execute the neural signaling of the whole brain in real time, performing functions such as controlling the behaviors of a robot. The modules could be configured automatically using evolutionary algorithms, by a successive reconfiguration on field programmable gate arrays (FPGA), placed on commercially available boards such as those offered by Celoxica. These chips could be programmed using high level languages, such as "Handel-C", whose statements are "hardware compiled" into the chip configuring instructions to wire up the chip, speeding-up the execution of instructions. The major challenge of this approach is architecting the artificial brain - how to put 10,000s of evolved neural net modules together to perform a library of controllable behaviors. One potential concern of this approach relates to the anticipated unwanted synergy of inter module neural signaling. While most current artificial brain projects use supercomputers or PC clusters with 1000s of nodes, Moore's law facilitates increasingly larger computational power at low costs, making brain building technically and economically possible. Examples from our efforts in evolving neural modules are presented, along with a critical analysis of the state of the art and realistic assessment of the challenges ahead
{"title":"Hardware Accelerators for Evolving Building Block Modules for Artificial Brains","authors":"H. D. Garis","doi":"10.1109/AHS.2006.50","DOIUrl":"https://doi.org/10.1109/AHS.2006.50","url":null,"abstract":"Summary form only given. This paper argues that it is technologically possible to build artificial brains at relatively low cost. The proposed approach to doing this is to evolve large numbers (tens of thousands) of neural network modules, each with its own simple function, and then interconnect them inside a computer that would execute the neural signaling of the whole brain in real time, performing functions such as controlling the behaviors of a robot. The modules could be configured automatically using evolutionary algorithms, by a successive reconfiguration on field programmable gate arrays (FPGA), placed on commercially available boards such as those offered by Celoxica. These chips could be programmed using high level languages, such as \"Handel-C\", whose statements are \"hardware compiled\" into the chip configuring instructions to wire up the chip, speeding-up the execution of instructions. The major challenge of this approach is architecting the artificial brain - how to put 10,000s of evolved neural net modules together to perform a library of controllable behaviors. One potential concern of this approach relates to the anticipated unwanted synergy of inter module neural signaling. While most current artificial brain projects use supercomputers or PC clusters with 1000s of nodes, Moore's law facilitates increasingly larger computational power at low costs, making brain building technically and economically possible. Examples from our efforts in evolving neural modules are presented, along with a critical analysis of the state of the art and realistic assessment of the challenges ahead","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132363327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Optimal weight extraction of beamforming algorithms based on systolic structures have been the subject of various researches since the well-known article presented by Gentleman and Kung (1981) on recursive least squares systolic arrays. Systolic algorithms are parallel and fully pipelined structures, this feature improves the performance of the beamforming algorithms and the system. SystemC is a system design language, which was lately accepted by the IEEE as a standard. SystemC has the advantage of designing both the hardware and the software components together so that the design and simulation process of large systems become easier. This work is based on the simulation of the minimum variance distortionless response (MVDR) beamformer, proposed by Tang, Liu, and Tretter (1994), in SystemC environment and evaluate its performance
{"title":"Systolic Array Based Adaptive Beamformer Modeling in SystemC Environment","authors":"O. Tamer, Ahmet Özkurt","doi":"10.1109/AHS.2006.70","DOIUrl":"https://doi.org/10.1109/AHS.2006.70","url":null,"abstract":"Optimal weight extraction of beamforming algorithms based on systolic structures have been the subject of various researches since the well-known article presented by Gentleman and Kung (1981) on recursive least squares systolic arrays. Systolic algorithms are parallel and fully pipelined structures, this feature improves the performance of the beamforming algorithms and the system. SystemC is a system design language, which was lately accepted by the IEEE as a standard. SystemC has the advantage of designing both the hardware and the software components together so that the design and simulation process of large systems become easier. This work is based on the simulation of the minimum variance distortionless response (MVDR) beamformer, proposed by Tang, Liu, and Tretter (1994), in SystemC environment and evaluate its performance","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127147561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new approach in realizing virtual channels tailored for network on chip implementations. The technique makes use of a flow control mechanism based on adaptive input rate control where the required buffer size is independent of the number of channels and the packet size. The resulting implementation requires only 3% of the memory space used in a conventional implementation of virtual channels. The efficient use of memory storage does also deliver performance improvements that can be up to 15% for a normal network configuration
{"title":"Wormhole Routing with Virtual Channels using Adaptive Rate Control for Network-on-Chip (NoC)","authors":"I. Nousias, T. Arslan","doi":"10.1109/AHS.2006.79","DOIUrl":"https://doi.org/10.1109/AHS.2006.79","url":null,"abstract":"This paper presents a new approach in realizing virtual channels tailored for network on chip implementations. The technique makes use of a flow control mechanism based on adaptive input rate control where the required buffer size is independent of the number of channels and the packet size. The resulting implementation requires only 3% of the memory space used in a conventional implementation of virtual channels. The efficient use of memory storage does also deliver performance improvements that can be up to 15% for a normal network configuration","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128425515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an efficient hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264 video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. We use a novel edge filter ordering in a macroblock to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. The proposed architecture is implemented in VerilogHDL. The Verilog RTL code is verified to work at 72 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can code 30 GIF frames (352 times 288) per second
本文提出了H.264视频编码标准中自适应块化滤波算法实时实现的高效硬件架构。该硬件被设计为用于便携式应用程序的完整H.264视频编码系统的一部分。我们在宏块中使用了一种新的边缘过滤器排序，以防止去块过滤器硬件不必要地等待将要过滤的像素变得可用。该体系结构在VerilogHDL语言中实现。Verilog RTL代码在Xilinx Virtex II FPGA中工作在72 MHz。FPGA实现可以每秒编码30个GIF帧(352乘以288)
{"title":"An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter","authors":"M. Parlak, Ilker Hamzaoglu","doi":"10.1109/AHS.2006.20","DOIUrl":"https://doi.org/10.1109/AHS.2006.20","url":null,"abstract":"This paper presents an efficient hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264 video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. We use a novel edge filter ordering in a macroblock to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. The proposed architecture is implemented in VerilogHDL. The Verilog RTL code is verified to work at 72 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can code 30 GIF frames (352 times 288) per second","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123676883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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