In conventional avionics system design process, changing the avionics system architecture involves a large team of engineers and requires months to years of redesign time. This paper describes the avionics architecture tool (AST) developed by JPL that can automatically synthesize architecture for the avionics-system-on-a-chip. As the synthesis is based on genetic algorithm and driven by requirements that are imposed by the environment, the synthesized architecture can quickly adapt to environmental changes. Furthermore, the AST can also guarantee that the synthesized architecture is viable and workable through the use of viability tree
{"title":"An Automatic Technique to Synthesize Avionics Architecture","authors":"S. Chau, V. Dang, Joseph Xu, James F. Lu","doi":"10.1109/AHS.2006.19","DOIUrl":"https://doi.org/10.1109/AHS.2006.19","url":null,"abstract":"In conventional avionics system design process, changing the avionics system architecture involves a large team of engineers and requires months to years of redesign time. This paper describes the avionics architecture tool (AST) developed by JPL that can automatically synthesize architecture for the avionics-system-on-a-chip. As the synthesis is based on genetic algorithm and driven by requirements that are imposed by the environment, the synthesized architecture can quickly adapt to environmental changes. Furthermore, the AST can also guarantee that the synthesized architecture is viable and workable through the use of viability tree","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126278338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the high complexity of future system-on-chips, many aspects such as synchronization, system control and system test and validation will be difficult to manage. Clock signals stretching over the complete die suffers from delays and cause synchronization problems, a centralized system control becomes a bottle neck and the high number of system components causes further problems when verifying the system functional correctness. Self-adaptive systems are an important field of research in order to find solutions to these problems. In this paper, a concept for self-recovery from behavioural failures is presented. The proposed methods are based on earlier work in this area which exploits dynamic and partial hardware reconfiguration. Hardware reconfiguration is an important feature in self-adaptive systems since it offers a higher degree of freedom, and in this case it also offers the possibility for a system to recover from a failure during run-time
{"title":"Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration","authors":"K. Paulsson, M. Hübner, J. Becker","doi":"10.1109/AHS.2006.67","DOIUrl":"https://doi.org/10.1109/AHS.2006.67","url":null,"abstract":"With the high complexity of future system-on-chips, many aspects such as synchronization, system control and system test and validation will be difficult to manage. Clock signals stretching over the complete die suffers from delays and cause synchronization problems, a centralized system control becomes a bottle neck and the high number of system components causes further problems when verifying the system functional correctness. Self-adaptive systems are an important field of research in order to find solutions to these problems. In this paper, a concept for self-recovery from behavioural failures is presented. The proposed methods are based on earlier work in this area which exploits dynamic and partial hardware reconfiguration. Hardware reconfiguration is an important feature in self-adaptive systems since it offers a higher degree of freedom, and in this case it also offers the possibility for a system to recover from a failure during run-time","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125140361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new hardware developmental model that shows strong robust transient fault-tolerant abilities and is motivated by embryonic development and a honeycomb structure is presented. Cartesian genetic programming (CGP) is used to evolve the cell structure. A pattern formation problem is realised by cells with identical evolved structures. The pattern is shown to recover from various kinds of transient faults. The fault-tolerance of this structure is not designed, but evolved under selective pressure in an environment of chemicals and states. The increased interaction between cells, brought about by the honeycomb structure, speeds up the evolutionary process and simplifies the structure of the evolved circuits compared to previous embryonic systems
{"title":"A Honeycomb Development Architecture for Robust Fault-Tolerant Design","authors":"A. Tyrrell, Hong Sun","doi":"10.1109/AHS.2006.5","DOIUrl":"https://doi.org/10.1109/AHS.2006.5","url":null,"abstract":"A new hardware developmental model that shows strong robust transient fault-tolerant abilities and is motivated by embryonic development and a honeycomb structure is presented. Cartesian genetic programming (CGP) is used to evolve the cell structure. A pattern formation problem is realised by cells with identical evolved structures. The pattern is shown to recover from various kinds of transient faults. The fault-tolerance of this structure is not designed, but evolved under selective pressure in an environment of chemicals and states. The increased interaction between cells, brought about by the honeycomb structure, speeds up the evolutionary process and simplifies the structure of the evolved circuits compared to previous embryonic systems","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122418224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Genomes for a cellular developmental system include some form of gene regulation. As such, evolution searches for genomes that are evaluated by properties emerging in the interplay between the genome and the emerging phenotype. In this paper an experimental approach is taken to show that information from this iterative process can be used to provide the evaluation process with information of the emerging phenotype. Experiments show that evaluation of gene regulation network can indirectly give information on growth, differentiation and self-regulation in the phenotype. An experiment exploiting these properties towards development of stable self-regulation functional circuits is presented. All experiments are carried out using hardware cellular development and phenotypes that emerge in hardware
{"title":"Gene Regulation Mechanisms Introduced in the Evaluation Criteria for a Hardware Cellular Development System","authors":"G. Tufte","doi":"10.1109/AHS.2006.46","DOIUrl":"https://doi.org/10.1109/AHS.2006.46","url":null,"abstract":"Genomes for a cellular developmental system include some form of gene regulation. As such, evolution searches for genomes that are evaluated by properties emerging in the interplay between the genome and the emerging phenotype. In this paper an experimental approach is taken to show that information from this iterative process can be used to provide the evaluation process with information of the emerging phenotype. Experiments show that evaluation of gene regulation network can indirectly give information on growth, differentiation and self-regulation in the phenotype. An experiment exploiting these properties towards development of stable self-regulation functional circuits is presented. All experiments are carried out using hardware cellular development and phenotypes that emerge in hardware","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"1764 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116750580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Randomly connecting networks have proven to be universal computing machines. By interconnecting a set of nodes in a random way one can model very complicated non-linear dynamic systems. Although random Boolean networks (RBN) use Boolean functions as their basic component, there are not hardware implementations of such systems. The absence of implementations is mainly due to the arbitrary connectionism exhibited by the network, and connection flexibility use to be very expensive in terms of hardware resources. In this paper we present an on-chip self-reconfigurable approach for providing a flexible connectionism at very low resource cost by partially reconfiguring Virtex II FPGAs
随机连接的网络已被证明是通用的计算机器。通过以随机方式连接一组节点，可以对非常复杂的非线性动态系统进行建模。尽管随机布尔网络(RBN)使用布尔函数作为其基本组成部分，但目前还没有这种系统的硬件实现。实现的缺失主要是由于网络表现出的任意连接主义，并且连接灵活性在硬件资源方面非常昂贵。在本文中，我们提出了一种片上自重构方法，通过部分重新配置Virtex II fpga，以非常低的资源成本提供灵活的连接主义
{"title":"Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAs","authors":"A. Upegui, E. Sanchez","doi":"10.1109/AHS.2006.38","DOIUrl":"https://doi.org/10.1109/AHS.2006.38","url":null,"abstract":"Randomly connecting networks have proven to be universal computing machines. By interconnecting a set of nodes in a random way one can model very complicated non-linear dynamic systems. Although random Boolean networks (RBN) use Boolean functions as their basic component, there are not hardware implementations of such systems. The absence of implementations is mainly due to the arbitrary connectionism exhibited by the network, and connection flexibility use to be very expensive in terms of hardware resources. In this paper we present an on-chip self-reconfigurable approach for providing a flexible connectionism at very low resource cost by partially reconfiguring Virtex II FPGAs","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116383100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Keymeulen, R. Zebulum, R. Ramesham, A. Stoica, S. Katkoori, S. Graves, F. Novak, C. Antill
Space missions often require radiation and extreme-temperature hardened electronics to survive the harsh environments beyond earth's atmosphere. Traditional approaches to preserve electronics incorporate radiation shielding, insulation and redundancy at the expense of power and weight. In this work, we report the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC). Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120 degC down to -180degC). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on commercial-off-the-shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180degC) demonstrate the feasibility of this approach
{"title":"Self-Adaptive System Based on Field Programmable Gate Array for Extreme Temperature Electronics","authors":"D. Keymeulen, R. Zebulum, R. Ramesham, A. Stoica, S. Katkoori, S. Graves, F. Novak, C. Antill","doi":"10.1109/AHS.2006.64","DOIUrl":"https://doi.org/10.1109/AHS.2006.64","url":null,"abstract":"Space missions often require radiation and extreme-temperature hardened electronics to survive the harsh environments beyond earth's atmosphere. Traditional approaches to preserve electronics incorporate radiation shielding, insulation and redundancy at the expense of power and weight. In this work, we report the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC). Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120 degC down to -180degC). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on commercial-off-the-shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180degC) demonstrate the feasibility of this approach","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125095279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Vladimirova, Xiaofeng Wu, K. Sidibeh, David Barnhart, A. Jallad
Picosatellites are very small satellites with a mass of less than 1 kg. A number of picosatellite projects have been undertaken by University and government research teams. Constellations of picosatellites could prove to be a low-cost and efficient solution to remote sensing in LEO. Reconfiguration and adaptation are capabilities, which are of critical importance to such constellations. A conceptual model of a constellation consisting of heterogeneous picosatellite nodes with a payload function distributed among the nodes will be outlined. Enabling technologies for picosatellite constellations such as wireless intersatellite links, reconfigurable onboard computing and distributed processing will be discussed. A proposal for a test-bed to demonstrate a reconfigurable distributed computing platform will be outlined
{"title":"Enabling Technologies for Distributed Picosatellite Missions in LEO","authors":"T. Vladimirova, Xiaofeng Wu, K. Sidibeh, David Barnhart, A. Jallad","doi":"10.1109/AHS.2006.33","DOIUrl":"https://doi.org/10.1109/AHS.2006.33","url":null,"abstract":"Picosatellites are very small satellites with a mass of less than 1 kg. A number of picosatellite projects have been undertaken by University and government research teams. Constellations of picosatellites could prove to be a low-cost and efficient solution to remote sensing in LEO. Reconfiguration and adaptation are capabilities, which are of critical importance to such constellations. A conceptual model of a constellation consisting of heterogeneous picosatellite nodes with a payload function distributed among the nodes will be outlined. Enabling technologies for picosatellite constellations such as wireless intersatellite links, reconfigurable onboard computing and distributed processing will be discussed. A proposal for a test-bed to demonstrate a reconfigurable distributed computing platform will be outlined","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124441156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these heterogeneous arrays is a labour intensive process. Furthermore, the manual creation of the array architecture could not have been fully optimised, hence limiting their performance. This paper presents a placement technique for mapping logic elements into heterogeneous reconfigurable arrays. At its core, it implements a genetic algorithm, which was used to reduce the span of all the interconnections as well as critical delay. It therefore minimises the amount of routing resource required in the architecture. The algorithm was tested on two arrays implementing DCT and speech coding. The resulting architecture achieves optimal close to that of an expert designer in a fraction of the time
{"title":"Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays","authors":"Wing On Fung, T. Arslan, S. Khawam","doi":"10.1109/AHS.2006.48","DOIUrl":"https://doi.org/10.1109/AHS.2006.48","url":null,"abstract":"Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these heterogeneous arrays is a labour intensive process. Furthermore, the manual creation of the array architecture could not have been fully optimised, hence limiting their performance. This paper presents a placement technique for mapping logic elements into heterogeneous reconfigurable arrays. At its core, it implements a genetic algorithm, which was used to reduce the span of all the interconnections as well as critical delay. It therefore minimises the amount of routing resource required in the architecture. The algorithm was tested on two arrays implementing DCT and speech coding. The resulting architecture achieves optimal close to that of an expert designer in a fraction of the time","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127341076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a unique SEU (single event upset) mitigation technique based upon temporal data sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (single event transients) induced errors that can result in data loss for any synchronous and reconfigurable architecture. The proposed scheme may be employed in circuits to eliminate all SEUs and SETs for performance critical applications.. This approach permits FPGAs and other microcircuits with deep submicron feature size to be used in hostile space environments. Results included show that the proposed scheme is approximately 55% area and 63% power efficient than previously introduced schemes
{"title":"An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable Architectures","authors":"S. Baloch, T. Arslan, A. Stoica","doi":"10.1109/AHS.2006.22","DOIUrl":"https://doi.org/10.1109/AHS.2006.22","url":null,"abstract":"This paper presents a unique SEU (single event upset) mitigation technique based upon temporal data sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (single event transients) induced errors that can result in data loss for any synchronous and reconfigurable architecture. The proposed scheme may be employed in circuits to eliminate all SEUs and SETs for performance critical applications.. This approach permits FPGAs and other microcircuits with deep submicron feature size to be used in hostile space environments. Results included show that the proposed scheme is approximately 55% area and 63% power efficient than previously introduced schemes","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"28 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133685995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper presents a novel integrated system in which a number of image processing algorithm are embedded within a genetic algorithm (GA) based framework in order to provide an adaptation and better quality analysis with less computational complexity while maintaining flexibility to a broad range of defects. A specially tailored hybrid GA (HGA) is used to estimate geometric transformation of arbitrarily placed printed circuit boards (PCBs) on a conveyor belt without any prior information such as CAD data. A library of image processing functions is accessed by the HGA within an intelligent framework. These functions include operations such as fixed multi-thresholding, Sobel edge-detection, image subtraction and noise filters. The proposed framework allows novel composition of tasks such as edge-detection and thresholding in order to increase defect detection accuracy with low computational time. Our simulations on real PCB images demonstrate that the HGA is robust enough to detect any missing components and cut solder joint with any size and shape with significant reduction in computational time compared to conventional approaches
{"title":"Automatic Hybrid Genetic Algorithm Based Printed Circuit Board Inspection","authors":"S. Mashohor, J. Evans, A. Erdogan","doi":"10.1109/AHS.2006.28","DOIUrl":"https://doi.org/10.1109/AHS.2006.28","url":null,"abstract":"The paper presents a novel integrated system in which a number of image processing algorithm are embedded within a genetic algorithm (GA) based framework in order to provide an adaptation and better quality analysis with less computational complexity while maintaining flexibility to a broad range of defects. A specially tailored hybrid GA (HGA) is used to estimate geometric transformation of arbitrarily placed printed circuit boards (PCBs) on a conveyor belt without any prior information such as CAD data. A library of image processing functions is accessed by the HGA within an intelligent framework. These functions include operations such as fixed multi-thresholding, Sobel edge-detection, image subtraction and noise filters. The proposed framework allows novel composition of tasks such as edge-detection and thresholding in order to increase defect detection accuracy with low computational time. Our simulations on real PCB images demonstrate that the HGA is robust enough to detect any missing components and cut solder joint with any size and shape with significant reduction in computational time compared to conventional approaches","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130297112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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