Face recognition is a challenging field of research not only because of the complexity of this subject, but also because of its numerous practical applications. Much progress has been made towards recognising faces under controlled conditions, especially under normalised pose and lighting conditions and with neutral expression. However, the recognition of face images acquired in an outdoor environment with changes in illumination and/or pose remains a largely unsolved problem. This is due to the fact that most of face recognition methods assume that the pose of the face is known. In this paper, we propose the use of a Gabor Filter Bank to extract an augmented Gabor-face vector to solve the pose estimation problem, extract some statistical features such as means and variances. And then the classification is performed using the nearest neighbour algorithm with the Euclidean distance. Finally, experimental results are reported to show the robustness of the extracted feature vectors for the recognition problem
{"title":"Face Recognition Using a Gabor Filter Bank Approach","authors":"Walid Riad Boukabou, L. Ghouti, A. Bouridane","doi":"10.1109/AHS.2006.39","DOIUrl":"https://doi.org/10.1109/AHS.2006.39","url":null,"abstract":"Face recognition is a challenging field of research not only because of the complexity of this subject, but also because of its numerous practical applications. Much progress has been made towards recognising faces under controlled conditions, especially under normalised pose and lighting conditions and with neutral expression. However, the recognition of face images acquired in an outdoor environment with changes in illumination and/or pose remains a largely unsolved problem. This is due to the fact that most of face recognition methods assume that the pose of the face is known. In this paper, we propose the use of a Gabor Filter Bank to extract an augmented Gabor-face vector to solve the pose estimation problem, extract some statistical features such as means and variances. And then the classification is performed using the nearest neighbour algorithm with the Euclidean distance. Finally, experimental results are reported to show the robustness of the extracted feature vectors for the recognition problem","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128439184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes the architecture of our dynamically reconfigurable network-on-chip (NoC) architecture that has been proposed for reconfigurable multiprocessor system-on-chip (MPSoC), as a solution to the increased communication needs, low silicon cost, quality of service and scalability of network in mind. The novelty of the proposed NoC lies in the fact that it dynamically configures itself with respect to routing, switching and data packet size with the changing communication requirements of the system at run time, thus aiming to provide low latency, low power and high data throughput. Simulation results and a prototype implementation of the idea have shown its efficiency when simulated under different traffic condition at a negligible area overhead
{"title":"Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC","authors":"Balal Ahmad, A. Erdogan, S. Khawam","doi":"10.1109/AHS.2006.25","DOIUrl":"https://doi.org/10.1109/AHS.2006.25","url":null,"abstract":"This paper describes the architecture of our dynamically reconfigurable network-on-chip (NoC) architecture that has been proposed for reconfigurable multiprocessor system-on-chip (MPSoC), as a solution to the increased communication needs, low silicon cost, quality of service and scalability of network in mind. The novelty of the proposed NoC lies in the fact that it dynamically configures itself with respect to routing, switching and data packet size with the changing communication requirements of the system at run time, thus aiming to provide low latency, low power and high data throughput. Simulation results and a prototype implementation of the idea have shown its efficiency when simulated under different traffic condition at a negligible area overhead","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127203921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Keskin, P. Hampton, R. Conan, C. Bradley, A. Hilton, C. Blain
This paper describes the status of a Woofer-Tweeter (W/T) adaptive optics (AO) test bench that is developed at the University of Victoria, BC, Canada. The purpose of the UVic W/T AO bench with regards to the thirty meter telescope (TMT) project, the description of the W/T AO bench components, the hot air turbulence generator, the working principle and performance estimates from the system model of the W/T AO system are presented. The research concept of having dual deformable mirrors (DM) allows the W/T AO system to have a high degree of correction over a large amplitude wavefront distortion. The role of the UVic AO bench is to demonstrate the closed-loop wavefront control feasibility for a W/T AO concept to be used on the science instruments of the TMT
{"title":"Woofer-Tweeter Adaptive Optics Test Bench","authors":"O. Keskin, P. Hampton, R. Conan, C. Bradley, A. Hilton, C. Blain","doi":"10.1109/AHS.2006.78","DOIUrl":"https://doi.org/10.1109/AHS.2006.78","url":null,"abstract":"This paper describes the status of a Woofer-Tweeter (W/T) adaptive optics (AO) test bench that is developed at the University of Victoria, BC, Canada. The purpose of the UVic W/T AO bench with regards to the thirty meter telescope (TMT) project, the description of the W/T AO bench components, the hot air turbulence generator, the working principle and performance estimates from the system model of the W/T AO system are presented. The research concept of having dual deformable mirrors (DM) allows the W/T AO system to have a high degree of correction over a large amplitude wavefront distortion. The role of the UVic AO bench is to demonstrate the closed-loop wavefront control feasibility for a W/T AO concept to be used on the science instruments of the TMT","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131774337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Al-Khaleel, C. Papachristou, F. Wolff, K. Pekmestzi
Large multipliers are important for cryptographic applications because they need large keys. The ability to modify key lengths, for security reasons, suggests adaptability in multiplication bit-length. However, reconfigurability of multiplication is a difficult task, especially when bit-lengths are large, say over 500 bits. For fixed bit-lengths, much work has been done in the range of 32, 64 or even 128 bits for advanced microprocessors and DSPs. The objective of this work is to design large adaptable bit-length multipliers that can be employed in cryptographic systems. We present a multiplication scheme for higher radix multiplexer-based array multipliers and we suggest a parallelization of the scheme within a single FPGA based implementation. We also suggest a novel partition of the multiplier into folded pipeline stages such that each stage can be instantiated by reconfiguration from its preceding stage during the multiplication operation. The number of partition stages is flexible to meet the FPGA resource constraints. The rationale for pipeline folding is that the multiplier size may preclude a monolithic implementation within one FPGA chip. Using additional FPGAs reduces performance due to interchip communication. Results of large reconfigurable multipliers for 256-bits and over implemented in Xilinx Virtex4 are provided
{"title":"A Large Scale Adaptable Multiplier for Cryptographic Applications","authors":"O. Al-Khaleel, C. Papachristou, F. Wolff, K. Pekmestzi","doi":"10.1109/AHS.2006.6","DOIUrl":"https://doi.org/10.1109/AHS.2006.6","url":null,"abstract":"Large multipliers are important for cryptographic applications because they need large keys. The ability to modify key lengths, for security reasons, suggests adaptability in multiplication bit-length. However, reconfigurability of multiplication is a difficult task, especially when bit-lengths are large, say over 500 bits. For fixed bit-lengths, much work has been done in the range of 32, 64 or even 128 bits for advanced microprocessors and DSPs. The objective of this work is to design large adaptable bit-length multipliers that can be employed in cryptographic systems. We present a multiplication scheme for higher radix multiplexer-based array multipliers and we suggest a parallelization of the scheme within a single FPGA based implementation. We also suggest a novel partition of the multiplier into folded pipeline stages such that each stage can be instantiated by reconfiguration from its preceding stage during the multiplication operation. The number of partition stages is flexible to meet the FPGA resource constraints. The rationale for pipeline folding is that the multiplier size may preclude a monolithic implementation within one FPGA chip. Using additional FPGAs reduces performance due to interchip communication. Results of large reconfigurable multipliers for 256-bits and over implemented in Xilinx Virtex4 are provided","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133571468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
By sharing building blocks between different applications and standards, portable wireless devices gain advantage over their predecessors: they use a smaller chip area, consume less power, and have a potential for lower overall cost. This requires the development of adaptive circuits and systems that are able to trade off power consumption for performance on the fly. Realization of the adaptivity function requires scaling of circuit parameters to the demands of the signal-processing task. Basic aspects of the mechanisms underlying the operation of adaptive receivers and adaptive circuits are examined in this paper, and methodologies for their synthesis discussed
{"title":"Adaptive Multifunctional Circuits and Systems for Future Generations of Wireless Communications","authors":"A. Tasic","doi":"10.1109/AHS.2006.16","DOIUrl":"https://doi.org/10.1109/AHS.2006.16","url":null,"abstract":"By sharing building blocks between different applications and standards, portable wireless devices gain advantage over their predecessors: they use a smaller chip area, consume less power, and have a potential for lower overall cost. This requires the development of adaptive circuits and systems that are able to trade off power consumption for performance on the fly. Realization of the adaptivity function requires scaling of circuit parameters to the demands of the signal-processing task. Basic aspects of the mechanisms underlying the operation of adaptive receivers and adaptive circuits are examined in this paper, and methodologies for their synthesis discussed","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131875325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xuesong Yan, Wei Wei, R. Liu, Sanyou Zeng, Lishan Kang
This work investigates the application of gene expression programming (GEP) in the field of evolutionary electronics. GEP is a genetic algorithm as it uses populations of individuals, selects them according to fitness, and introduces genetic variation using one or more genetic operators. We propose the new means for designing electronic circuits and introduce the encoding of the circuit as a chromosome, the genetic operators and the fitness function. For the case studies this means has proved to be efficient, experiments show that we have better results
{"title":"Designing Electronic Circuits by Means of Gene Expression Programming","authors":"Xuesong Yan, Wei Wei, R. Liu, Sanyou Zeng, Lishan Kang","doi":"10.1109/AHS.2006.31","DOIUrl":"https://doi.org/10.1109/AHS.2006.31","url":null,"abstract":"This work investigates the application of gene expression programming (GEP) in the field of evolutionary electronics. GEP is a genetic algorithm as it uses populations of individuals, selects them according to fitness, and introduces genetic variation using one or more genetic operators. We propose the new means for designing electronic circuits and introduce the encoding of the circuit as a chromosome, the genetic operators and the fitness function. For the case studies this means has proved to be efficient, experiments show that we have better results","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133391821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The possibility of using switchable glass (also called smart windows) technology for evolvable hardware tasks is suggested in this paper. Switchable glass technology basically means controlling the transmission of light through windows by using electrical power. By applying a variable voltage to the window we can continuously vary the amount of transmitted light. Three existing technologies are reviewed in this paper: electrochromic devices, suspended particle devices and liquid crystal devices. An evolvable hardware application for a light-based device is described. The proposed device can be used for solving an entire class of problems, instead of one problem only as in the case of other dedicated hardware
{"title":"Switchable Glass: A Possible Medium for Evolvable Hardware","authors":"Mihai Oltean","doi":"10.1109/AHS.2006.69","DOIUrl":"https://doi.org/10.1109/AHS.2006.69","url":null,"abstract":"The possibility of using switchable glass (also called smart windows) technology for evolvable hardware tasks is suggested in this paper. Switchable glass technology basically means controlling the transmission of light through windows by using electrical power. By applying a variable voltage to the window we can continuously vary the amount of transmitted light. Three existing technologies are reviewed in this paper: electrochromic devices, suspended particle devices and liquid crystal devices. An evolvable hardware application for a light-based device is described. The proposed device can be used for solving an entire class of problems, instead of one problem only as in the case of other dedicated hardware","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114995483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a multi-objective algorithm for on-line adaptation of a multi-carrier code-division multiple access (MC-CDMA) receiver. A specially tailored genetic algorithm (GA) is developed in order to adapt the complete receiver while dynamically optimizing the critical fast Fourier transform (FFT) section of the receiver for both error value and power consumption. The results obtained, through evaluation within complete receiver architecture, demonstrate that the algorithm can find results optimized for both objectives. Results also show that there are significant reductions in error value and power consumption as compared to the reference solution
{"title":"A Multi-Objective Genetic Algorithm for On-Chip Real-time Adaptation of a Multi-Carrier Based Telecommunications Receiver","authors":"N. Sulaiman, A. Erdogan","doi":"10.1109/AHS.2006.9","DOIUrl":"https://doi.org/10.1109/AHS.2006.9","url":null,"abstract":"This paper presents a multi-objective algorithm for on-line adaptation of a multi-carrier code-division multiple access (MC-CDMA) receiver. A specially tailored genetic algorithm (GA) is developed in order to adapt the complete receiver while dynamically optimizing the critical fast Fourier transform (FFT) section of the receiver for both error value and power consumption. The results obtained, through evaluation within complete receiver architecture, demonstrate that the algorithm can find results optimized for both objectives. Results also show that there are significant reductions in error value and power consumption as compared to the reference solution","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115479192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advanced sensors coupled with exponential improvements in computer technology have enabled sensors to be deployed in a wide range of applications, ranging from environmental monitoring to improved biomedical devices. However, to be useful in real-life applications - in the industrial or medical environment - a sensor has to be able to autonomously adapt in response to unusual events. The purpose of this paper is to develop a mathematical model that will enable a waveguide-based sensor - with a particular emphasis on biosensors - to autonomously implement self-test, control and repair
{"title":"Analytical Modelling of Power Attenuation under Parameter Fluctuations with Applications to Self-Test and Repair","authors":"H. Kadim","doi":"10.1109/AHS.2006.24","DOIUrl":"https://doi.org/10.1109/AHS.2006.24","url":null,"abstract":"Advanced sensors coupled with exponential improvements in computer technology have enabled sensors to be deployed in a wide range of applications, ranging from environmental monitoring to improved biomedical devices. However, to be useful in real-life applications - in the industrial or medical environment - a sensor has to be able to autonomously adapt in response to unusual events. The purpose of this paper is to develop a mathematical model that will enable a waveguide-based sensor - with a particular emphasis on biosensors - to autonomously implement self-test, control and repair","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124343331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The increasing use of new Earth-observation and communication technologies coupled with rapidly changing customer needs require a high performance and flexible processing technology for on-board data processing. Currently available processors for space cannot handle processing such a large magnitude. An alternative approach would be the development of application specific ICs (ASICs) which offer high processing power, but the lack of flexibility for adaptation to emerging standards and improvements is a major disadvantage. The extreme processing platform (XPP) developed by PACT AG offers a solution to this dilemma by providing the flexibility of a processor kernel along with the performance similar to an ASIC. The XPP is a runtime reconfigurable data processing technology built using a scalable array of arithmetic processing units, embedded memories, high bandwidth I/O, a packet oriented internal network and designed to support parallelism. This paper gives an overview of the XPP core architecture, compares the technology with currently available space processors, and assesses the implementation of wavelet transformation algorithm on XPP and the transfer of XPP architecture to a radiation tolerant semiconductor technology
{"title":"Reconfigurable Parallel Computing Architecture for On-Board Data Processing","authors":"M. Syed, Eberhard Schüler","doi":"10.1109/AHS.2006.62","DOIUrl":"https://doi.org/10.1109/AHS.2006.62","url":null,"abstract":"The increasing use of new Earth-observation and communication technologies coupled with rapidly changing customer needs require a high performance and flexible processing technology for on-board data processing. Currently available processors for space cannot handle processing such a large magnitude. An alternative approach would be the development of application specific ICs (ASICs) which offer high processing power, but the lack of flexibility for adaptation to emerging standards and improvements is a major disadvantage. The extreme processing platform (XPP) developed by PACT AG offers a solution to this dilemma by providing the flexibility of a processor kernel along with the performance similar to an ASIC. The XPP is a runtime reconfigurable data processing technology built using a scalable array of arithmetic processing units, embedded memories, high bandwidth I/O, a packet oriented internal network and designed to support parallelism. This paper gives an overview of the XPP core architecture, compares the technology with currently available space processors, and assesses the implementation of wavelet transformation algorithm on XPP and the transfer of XPP architecture to a radiation tolerant semiconductor technology","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121171099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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