Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing circuit and FPGA complexity. To overcome this there have been moves towards encoding a growth process, known as morphogenesis, however existing approaches have tended to abstract away the underlying FPGA architecture. Although currently commercially available FPGAs are not the most evolution-friendly platforms, having complex architectures and issues with potentially damaging configurations, evolving circuits on commercially available devices without requiring a move to high-level building blocks is a necessary prerequisite for the adoption of EHW to solving real problems in electronic design, repair and adaptation. In this paper we present a morphogenetic EHW model where growth is directed by the gate-level state of the FPGA. We demonstrate that this approach consistently outperforms a traditional EHW approach using a direct encoding, in the number of generations required to find an optimal solution, and in its ability to scale to increases in circuit size and complexity. Issues in EHW problem solvability are also identified, and preliminary work is presented showing that a morphogenetic approach to EHW may be well suited to correcting damaged circuits
{"title":"Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs","authors":"Justin Lee, J. Sitte","doi":"10.1109/AHS.2006.45","DOIUrl":"https://doi.org/10.1109/AHS.2006.45","url":null,"abstract":"Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing circuit and FPGA complexity. To overcome this there have been moves towards encoding a growth process, known as morphogenesis, however existing approaches have tended to abstract away the underlying FPGA architecture. Although currently commercially available FPGAs are not the most evolution-friendly platforms, having complex architectures and issues with potentially damaging configurations, evolving circuits on commercially available devices without requiring a move to high-level building blocks is a necessary prerequisite for the adoption of EHW to solving real problems in electronic design, repair and adaptation. In this paper we present a morphogenetic EHW model where growth is directed by the gate-level state of the FPGA. We demonstrate that this approach consistently outperforms a traditional EHW approach using a direct encoding, in the number of generations required to find an optimal solution, and in its ability to scale to increases in circuit size and complexity. Issues in EHW problem solvability are also identified, and preliminary work is presented showing that a morphogenetic approach to EHW may be well suited to correcting damaged circuits","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130892667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Adaptive antenna technology represents the most advanced smart antenna approach to date. Using a variety of new signal-processing algorithms, the adaptive system takes advantage of its ability to effectively locate and track various types of signals to dynamically minimize interference and maximize intended signal reception. This paper presents the design and development of a micro-antenna for SoC, working at 43.763 GHz and controlled by independent MEMS based DMTL phase shifters which are low power in nature. We have also explored other required low power SoC devices which would also have the ability to reconfigure to the demands of our communication device. This in turn will enhance the desirability of our adaptive antenna for future low power mobile devices. The criteria for such a device must be its small size, a functionality that must make it possible to use over a wide variety of applications and similar fabrication techniques as with the rest of the SoC design. Our MEMS based design allows us to have all the communication and control circuitry on a single silicon substrate; enabling easy fabrication
{"title":"Adaptive Micro-Antenna on Silicon Substrate","authors":"N. Haridas, A. Erdogan, T. Arslan, M. Begbie","doi":"10.1109/AHS.2006.15","DOIUrl":"https://doi.org/10.1109/AHS.2006.15","url":null,"abstract":"Adaptive antenna technology represents the most advanced smart antenna approach to date. Using a variety of new signal-processing algorithms, the adaptive system takes advantage of its ability to effectively locate and track various types of signals to dynamically minimize interference and maximize intended signal reception. This paper presents the design and development of a micro-antenna for SoC, working at 43.763 GHz and controlled by independent MEMS based DMTL phase shifters which are low power in nature. We have also explored other required low power SoC devices which would also have the ability to reconfigure to the demands of our communication device. This in turn will enhance the desirability of our adaptive antenna for future low power mobile devices. The criteria for such a device must be its small size, a functionality that must make it possible to use over a wide variety of applications and similar fabrication techniques as with the rest of the SoC design. Our MEMS based design allows us to have all the communication and control circuitry on a single silicon substrate; enabling easy fabrication","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133213471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sharing intellectual property (IP) blocks in today's competitive market poses significant high security risks. In this paper, we present a tutorial for a watermarking approach based on the embedding of the ownership proof as part of the IP design's finite state machine (FSM). It utilizes coinciding as well as unused transitions in the state transition graph of the design. Based on this approach, we have developed a robust watermarking framework, used for copyright protection. The developed technique increases the robustness of the watermark and allows a secure implementation, hence enabling the development of the first public-key IP watermarking scheme at the FSM level. In order to integrate these algorithms in the design cycle of industrial projects, we extend the above techniques to enable the watermarking of hierarchical finite state machines (HFSMs)
{"title":"Finite State Machine IP Watermarking: A Tutorial","authors":"A. T. Abdel-Hamid, S. Tahar, E. Aboulhamid","doi":"10.1109/AHS.2006.40","DOIUrl":"https://doi.org/10.1109/AHS.2006.40","url":null,"abstract":"Sharing intellectual property (IP) blocks in today's competitive market poses significant high security risks. In this paper, we present a tutorial for a watermarking approach based on the embedding of the ownership proof as part of the IP design's finite state machine (FSM). It utilizes coinciding as well as unused transitions in the state transition graph of the design. Based on this approach, we have developed a robust watermarking framework, used for copyright protection. The developed technique increases the robustness of the watermark and allows a secure implementation, hence enabling the development of the first public-key IP watermarking scheme at the FSM level. In order to integrate these algorithms in the design cycle of industrial projects, we extend the above techniques to enable the watermarking of hierarchical finite state machines (HFSMs)","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116607592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recovery from fault (or malfunction) and maintaining constant performance in the presence of unusual events is a major concern in a wide range of applications. Therefore, there is a need for hardware that is capable of changing (or adjusting) its behaviour dynamically and autonomously. In this paper, a state-space analytical model for the real-time detection of unusual events and repair is proposed
{"title":"State-Space Based Analytical Modelling for Real-Time Fault Recovery and Self-Repair with Applications to Biosensors","authors":"H. Kadim","doi":"10.1109/AHS.2006.66","DOIUrl":"https://doi.org/10.1109/AHS.2006.66","url":null,"abstract":"Recovery from fault (or malfunction) and maintaining constant performance in the presence of unusual events is a major concern in a wide range of applications. Therefore, there is a need for hardware that is capable of changing (or adjusting) its behaviour dynamically and autonomously. In this paper, a state-space analytical model for the real-time detection of unusual events and repair is proposed","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130086176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Self-reconfigurable adaptive systems have the possibility of adapting their own hardware configuration. This feature provides enhanced performance and flexibility, reflected in computational cost reductions. Self-reconfigurable adaptation requires powerful optimization algorithms in order to search in a space of possible hardware configurations. If such algorithms are to be implemented on chip, they must also be as simple as possible, so the best performance can be achieved with the less cost in terms of logic resources, convergence speed, and power consumption. This paper presents hybrid bio-inspired optimization technique that introduces the concept of discrete recombination in a particle swarm optimizer, obtaining a simple and powerful algorithm, well suited for embedded applications. The proposed algorithm is validated using standard benchmark functions and used for training a neural network-based adaptive equalizer for communications systems
{"title":"Particle Swarm Optimization with Discrete Recombination: An Online Optimizer for Evolvable Hardware","authors":"Jorge Peña, A. Upegui, E. Sanchez","doi":"10.1109/AHS.2006.56","DOIUrl":"https://doi.org/10.1109/AHS.2006.56","url":null,"abstract":"Self-reconfigurable adaptive systems have the possibility of adapting their own hardware configuration. This feature provides enhanced performance and flexibility, reflected in computational cost reductions. Self-reconfigurable adaptation requires powerful optimization algorithms in order to search in a space of possible hardware configurations. If such algorithms are to be implemented on chip, they must also be as simple as possible, so the best performance can be achieved with the less cost in terms of logic resources, convergence speed, and power consumption. This paper presents hybrid bio-inspired optimization technique that introduces the concept of discrete recombination in a particle swarm optimizer, obtaining a simple and powerful algorithm, well suited for embedded applications. The proposed algorithm is validated using standard benchmark functions and used for training a neural network-based adaptive equalizer for communications systems","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114951107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A self-configurable system is one that is designed primarily for the purpose of reconfigurable control and adaptive signal processing. It evolves by restructures and readjustments back and forth which can track the environment and the system variation in time. Processing methods and application areas include but not limited to transmission enhancement such as filtering, equalization, and noise cancellation. The performance of our proposed self-configurable neural network processor (SCNNP) for finite impulse response (FIR) filter are compared with those of the classical FIR filters and the traditional adaptive FIR filters. The SCNNP is an autonomous system which does not need human design knowledge of the FIR filter
{"title":"Self-Configurable Neural Network Processor for FIR Filter Applications","authors":"Gorn Tepvorachai, C. Papachristou","doi":"10.1109/AHS.2006.65","DOIUrl":"https://doi.org/10.1109/AHS.2006.65","url":null,"abstract":"A self-configurable system is one that is designed primarily for the purpose of reconfigurable control and adaptive signal processing. It evolves by restructures and readjustments back and forth which can track the environment and the system variation in time. Processing methods and application areas include but not limited to transmission enhancement such as filtering, equalization, and noise cancellation. The performance of our proposed self-configurable neural network processor (SCNNP) for finite impulse response (FIR) filter are compared with those of the classical FIR filters and the traditional adaptive FIR filters. The SCNNP is an autonomous system which does not need human design knowledge of the FIR filter","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"558 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124686899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The stochastic Bernstein method (not to be confused with the Bernstein polynomials) is a novel and significantly improved non-polynomial global method of signal processing that is proving very useful for interpolating and for approximating data. It arose as an obvious extension of the work of Bernstein (it preserves some of the remarkable properties of the Bernstein polynomials). However, this extension means that stochastic interpolation takes on its own properties and additionally can replace the error function by other functions such as the arctangent. The method has a free parameter sigma known as its diffusivity that can be easily optimized with adaptivity and can interpolate or approximate non-uniformly distributed input data - something that is very awkward to set up with other methods. Adaptivity can also reverse engineer the non-uniformly distributed input data that best recovers a function. This short paper provides an introduction to the new mathematical method that should find wide application in many areas of science and engineering
{"title":"The Novel Stochastic Bernstein Method of Functional Approximation","authors":"J. Kolibal, Daniel Howard","doi":"10.1109/AHS.2006.73","DOIUrl":"https://doi.org/10.1109/AHS.2006.73","url":null,"abstract":"The stochastic Bernstein method (not to be confused with the Bernstein polynomials) is a novel and significantly improved non-polynomial global method of signal processing that is proving very useful for interpolating and for approximating data. It arose as an obvious extension of the work of Bernstein (it preserves some of the remarkable properties of the Bernstein polynomials). However, this extension means that stochastic interpolation takes on its own properties and additionally can replace the error function by other functions such as the arctangent. The method has a free parameter sigma known as its diffusivity that can be easily optimized with adaptivity and can interpolate or approximate non-uniformly distributed input data - something that is very awkward to set up with other methods. Adaptivity can also reverse engineer the non-uniformly distributed input data that best recovers a function. This short paper provides an introduction to the new mathematical method that should find wide application in many areas of science and engineering","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130008015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Trefzer, Jörg Langeheine, K. Meier, J. Schemmel
This paper gives an overview over the progress that has been made by the Heidelberg FPTA group within the field of analog evolvable hardware. Achievements are the design of a CMOS configurable transistor array (FPTA), the development of evolutionary algorithms (EAs) for analog circuit synthesis and the implementation of a modular framework, which makes it possible to use various substrates and simulation models for evolution experiments. The improvement of the EA is shown by comparing the performance of three implementations in evolving comparators. Additionally, results, obtained from the FPTA for the evolution of oscillators from scratch, are presented as an example for the successful application of the multi-objective Turtle GA. Finally, it is shown that a simplified software model of the Heidelberg FPTA is suitable to assess the real hardware, indicated by the fact that both substrates perform equally well in finding good solutions for comparators. This work aims at creating a customizable, modular framework that facilitates research on the performance and evolvability of possible FPTA topologies in the future
{"title":"A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures.","authors":"M. Trefzer, Jörg Langeheine, K. Meier, J. Schemmel","doi":"10.1109/AHS.2006.8","DOIUrl":"https://doi.org/10.1109/AHS.2006.8","url":null,"abstract":"This paper gives an overview over the progress that has been made by the Heidelberg FPTA group within the field of analog evolvable hardware. Achievements are the design of a CMOS configurable transistor array (FPTA), the development of evolutionary algorithms (EAs) for analog circuit synthesis and the implementation of a modular framework, which makes it possible to use various substrates and simulation models for evolution experiments. The improvement of the EA is shown by comparing the performance of three implementations in evolving comparators. Additionally, results, obtained from the FPTA for the evolution of oscillators from scratch, are presented as an example for the successful application of the multi-objective Turtle GA. Finally, it is shown that a simplified software model of the Heidelberg FPTA is suitable to assess the real hardware, indicated by the fact that both substrates perform equally well in finding good solutions for comparators. This work aims at creating a customizable, modular framework that facilitates research on the performance and evolvability of possible FPTA topologies in the future","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128820065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Liu, Sanyou Zeng, L. Ding, Lishan Kang, Hui Li, Yuping Chen, Yong Liu, Yueping Han
In this paper we introduce an efficient multi-objective evolutionary algorithm (EMOEA) to design circuits. The algorithm is based on non-dominated set for keeping diversity of the population and therefore, avoids trapping in local optimal. Encoding of the chromosome is based on J. F. Miller's implementation, but we use efficient methods to evaluate and evolve circuits for speeding up the convergence of the algorithm. This algorithm evolves complex combinational circuits (such as 3-bit multiplier and 4 bit full adder) without too much long time evolution (commonly less than 5,000,000)
{"title":"An Efficient Multi-Objective Evolutionary Algorithm for Combinational Circuit Design","authors":"R. Liu, Sanyou Zeng, L. Ding, Lishan Kang, Hui Li, Yuping Chen, Yong Liu, Yueping Han","doi":"10.1109/AHS.2006.21","DOIUrl":"https://doi.org/10.1109/AHS.2006.21","url":null,"abstract":"In this paper we introduce an efficient multi-objective evolutionary algorithm (EMOEA) to design circuits. The algorithm is based on non-dominated set for keeping diversity of the population and therefore, avoids trapping in local optimal. Encoding of the chromosome is based on J. F. Miller's implementation, but we use efficient methods to evaluate and evolve circuits for speeding up the convergence of the algorithm. This algorithm evolves complex combinational circuits (such as 3-bit multiplier and 4 bit full adder) without too much long time evolution (commonly less than 5,000,000)","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128944559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wireless sensor networks require the design of highly energy-efficient and yet flexible sensor nodes, which is very difficult to realize with classical architectures. In this paper we propose a new approach based on the tight coupling of a small processor with a dynamically reconfigurable function unit that is optimized for wireless sensor network applications. Dynamic reconfiguration is part of the regular operation mode and the key concept to achieve a small design that provides sufficient performance, high adaptivity and good energy-efficiency
{"title":"Design Concepts for a Dynamically ReconfigurableWireless Sensor Node","authors":"H. Hinkelmann, P. Zipf, M. Glesner","doi":"10.1109/AHS.2006.30","DOIUrl":"https://doi.org/10.1109/AHS.2006.30","url":null,"abstract":"Wireless sensor networks require the design of highly energy-efficient and yet flexible sensor nodes, which is very difficult to realize with classical architectures. In this paper we propose a new approach based on the tight coupling of a small processor with a dynamically reconfigurable function unit that is optimized for wireless sensor network applications. Dynamic reconfiguration is part of the regular operation mode and the key concept to achieve a small design that provides sufficient performance, high adaptivity and good energy-efficiency","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114721540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：