We propose a novel type of dynamically reconfigurable system-on-chip architecture, the Gannet service-based architecture. This novel concept addresses the issue of system-level reconfigurability of heterogeneous multi-core SoCs. The Gannet architecture introduces the "processing core as service" paradigm: the processing cores interface with the system in a similar manner to services on a network. The functionality of the system is defined by specifying the set of services and their interaction patterns. As both the set of services and the interaction patterns can be changed at run time, the system is dynamically reconfigurable at two levels. The service paradigm results in a decoupling of processing and communication, thus facilitating large-scale parallelism and self-managed distributed processing
{"title":"The Gannet Service-Based SoC: A Service-level Reconfigurable Architecture","authors":"W. Vanderbauwhede","doi":"10.1109/AHS.2006.72","DOIUrl":"https://doi.org/10.1109/AHS.2006.72","url":null,"abstract":"We propose a novel type of dynamically reconfigurable system-on-chip architecture, the Gannet service-based architecture. This novel concept addresses the issue of system-level reconfigurability of heterogeneous multi-core SoCs. The Gannet architecture introduces the \"processing core as service\" paradigm: the processing cores interface with the system in a similar manner to services on a network. The functionality of the system is defined by specifying the set of services and their interaction patterns. As both the set of services and the interaction patterns can be changed at run time, the system is dynamically reconfigurable at two levels. The service paradigm results in a decoupling of processing and communication, thus facilitating large-scale parallelism and self-managed distributed processing","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115172312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Arslan, N. Haridas, Erfu Yang, A. Erdogan, Nick Barton, A. Walton, J. Thompson, A. Stoica, T. Vladimirova, K. Mcdonald-Maier, W. Howells
There is an increasing need to develop flexible, reconfigurable, and intelligent multi-spacecraft sensing networks for aerospace-based monitoring and diagnostics. Technical advancements in ad hoc networking, MEMS devices, low-power electronics, adaptive and reconfigurable hardware, micro-spacecraft, and micro-sensors have enabled the design and development of such highly integrated space wireless sensor networks. This paper proposes the framework for an evolvable sensor network architecture, investigated as part of the ESPACENET project, collocated at the University of Edinburgh, Essex, Kent and Surrey. The aim is to design a flexible and intelligent embedded network of reconfigurable piconodes optimised by a hierarchical multi-objective algorithm. Although the project is targeted at aerospace applications, the same intelligent network can be used for many earth bound applications such as environmental and medical diagnostics
{"title":"ESPACENET: A Framework of Evolvable and Reconfigurable Sensor Networks for Aerospace–Based Monitoring and Diagnostics","authors":"T. Arslan, N. Haridas, Erfu Yang, A. Erdogan, Nick Barton, A. Walton, J. Thompson, A. Stoica, T. Vladimirova, K. Mcdonald-Maier, W. Howells","doi":"10.1109/AHS.2006.34","DOIUrl":"https://doi.org/10.1109/AHS.2006.34","url":null,"abstract":"There is an increasing need to develop flexible, reconfigurable, and intelligent multi-spacecraft sensing networks for aerospace-based monitoring and diagnostics. Technical advancements in ad hoc networking, MEMS devices, low-power electronics, adaptive and reconfigurable hardware, micro-spacecraft, and micro-sensors have enabled the design and development of such highly integrated space wireless sensor networks. This paper proposes the framework for an evolvable sensor network architecture, investigated as part of the ESPACENET project, collocated at the University of Edinburgh, Essex, Kent and Surrey. The aim is to design a flexible and intelligent embedded network of reconfigurable piconodes optimised by a hierarchical multi-objective algorithm. Although the project is targeted at aerospace applications, the same intelligent network can be used for many earth bound applications such as environmental and medical diagnostics","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125251602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a background mismatch-calibration method for a capacitive digital-to-analog-converter (CDAC). The linearity of a CDAC depends on the mismatch of the capacitors. In a CDAC, every bit activates the corresponding capacitor-bank (CB). Therefore, there are the same number of CBs as the number of bits. In reality, it is very important to match the current CB with the rest least-significant CBs. The mismatch values of individual capacitors in CBs from the unit sized-capacitor are not important since the voltage division is defined by capacitor banks as whole. If perfect matching among CBs are provided then the correct analog voltage output is defined by the ratio between the particular CB and total capacitance-value of CDAC considering the most-significant CBs tuned earlier. The method used in this paper is based on eliminating the mismatch between CBs rather than tuning each individual elements of CDAC. Adjusting each capacitor bank is much simpler and powerful technique to eliminate nonlinearities
{"title":"A Background Mismatch Calibration For Capacitive Digitial-To-Analog Converters RTERS","authors":"M. Keskin","doi":"10.1109/AHS.2006.1","DOIUrl":"https://doi.org/10.1109/AHS.2006.1","url":null,"abstract":"This paper presents a background mismatch-calibration method for a capacitive digital-to-analog-converter (CDAC). The linearity of a CDAC depends on the mismatch of the capacitors. In a CDAC, every bit activates the corresponding capacitor-bank (CB). Therefore, there are the same number of CBs as the number of bits. In reality, it is very important to match the current CB with the rest least-significant CBs. The mismatch values of individual capacitors in CBs from the unit sized-capacitor are not important since the voltage division is defined by capacitor banks as whole. If perfect matching among CBs are provided then the correct analog voltage output is defined by the ratio between the particular CB and total capacitance-value of CDAC considering the most-significant CBs tuned earlier. The method used in this paper is based on eliminating the mismatch between CBs rather than tuning each individual elements of CDAC. Adjusting each capacitor bank is much simpler and powerful technique to eliminate nonlinearities","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128553757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The objective of this paper is to classify the approaches proposed to the evolutionary digital circuit design in the recent years and to identify the levels of complexity and innovation that can be obtained by means of these approaches. In particular, gate-level evolution, circuit evolution in PLAs, functional-level evolution, incremental evolution, evolution utilizing developmental schemes and some application-specific schemes are analyzed. It is shown that we are able to effectively explore the search spaces not much larger than 21000 points and that the innovative solutions can be produced independently of the utilized method
{"title":"Evolutionary Design of Digital Circuits: Where Are Current Limits?","authors":"L. Sekanina","doi":"10.1109/AHS.2006.36","DOIUrl":"https://doi.org/10.1109/AHS.2006.36","url":null,"abstract":"The objective of this paper is to classify the approaches proposed to the evolutionary digital circuit design in the recent years and to identify the levels of complexity and innovation that can be obtained by means of these approaches. In particular, gate-level evolution, circuit evolution in PLAs, functional-level evolution, incremental evolution, evolution utilizing developmental schemes and some application-specific schemes are analyzed. It is shown that we are able to effectively explore the search spaces not much larger than 21000 points and that the innovative solutions can be produced independently of the utilized method","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"56 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133651427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. F. Stefatos, T. Arslan, D. Keymeulen, I. Ferguson
This paper presents an autonomous architecture for the implementation of the JPL/Boeing gyroscope. The central point of the architecture is a unified reconfigurable fabric, which integrates two custom especially tailored reconfigurable units. The former fabric enables the reconfiguration of integer based computations, whereas the later deals with those requiring fractional accuracy. The architecture employs a number of other techniques such as primitive operators and a hybrid evolutionary strategy in order to allow the real-time adaptation of high quality circuits with low power consumption and high degree of fault-tolerance. Simulation results prove that our proposed architecture is able to adapt, in the presence of single-hard-errors, the functionality of high-order finite-impulse-response filters and proportional-integral controllers very efficiently in terms of speed, accuracy and hardware utilization. Power analysis demonstrates the near ASIC performance of our architecture
{"title":"Towards the Integration of Drive Control Loop Electronics of the JPL/Boeing Gyroscope within an Autonomous Robust Custom-Reconfigurable Platform","authors":"E. F. Stefatos, T. Arslan, D. Keymeulen, I. Ferguson","doi":"10.1109/AHS.2006.75","DOIUrl":"https://doi.org/10.1109/AHS.2006.75","url":null,"abstract":"This paper presents an autonomous architecture for the implementation of the JPL/Boeing gyroscope. The central point of the architecture is a unified reconfigurable fabric, which integrates two custom especially tailored reconfigurable units. The former fabric enables the reconfiguration of integer based computations, whereas the later deals with those requiring fractional accuracy. The architecture employs a number of other techniques such as primitive operators and a hybrid evolutionary strategy in order to allow the real-time adaptation of high quality circuits with low power consumption and high degree of fault-tolerance. Simulation results prove that our proposed architecture is able to adapt, in the presence of single-hard-errors, the functionality of high-order finite-impulse-response filters and proportional-integral controllers very efficiently in terms of speed, accuracy and hardware utilization. Power analysis demonstrates the near ASIC performance of our architecture","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133449395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, state-of-the-art reconfigurable architectures are reviewed and their main drawback in reaching TeraByte per second bandwidth is identified. A concept of new adaptable architecture for signal processing applications is proposed that will enable TB/s processing in the future. Current prototypes of smaller scale modules show groundbreaking benefits in reaching the targeted goal
{"title":"Adaptable Architectures for Signal Processing Applications","authors":"M. Margala","doi":"10.1109/AHS.2006.14","DOIUrl":"https://doi.org/10.1109/AHS.2006.14","url":null,"abstract":"In this paper, state-of-the-art reconfigurable architectures are reviewed and their main drawback in reaching TeraByte per second bandwidth is identified. A concept of new adaptable architecture for signal processing applications is proposed that will enable TB/s processing in the future. Current prototypes of smaller scale modules show groundbreaking benefits in reaching the targeted goal","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124735105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose in this paper a novel adaptive approach inspired by fluid dynamics as a distributed, scalable, and robust solution to the deployment problem of mobile sensor networks in unknown environments. Our approach is based on the physical principles of fluids through which we model a mobile sensor network as a fluid body and individual nodes as fluid elements. We achieve desirable properties of effective coverage, scalability, and robustness by virtue of the diffusive and self-spreading behavior of compressible fluids as modeled in our deployment approach. Simulation of our deployment strategy shows that the approach is scalable in terms of environment and network size. It is also robust against localization uncertainty, partial operational failure, and dynamic changes in the landscape. In truly unknown environments where the number of nodes to be deployed cannot be determined a priori, our adaptive deployment scheme guarantees thorough coverage of the environment
{"title":"Towards Fluent Sensor Networks: A Scalable and Robust Self-Deployment Approach","authors":"Muhammed R. Pac, A. Erkmen, I. Erkmen","doi":"10.1109/AHS.2006.74","DOIUrl":"https://doi.org/10.1109/AHS.2006.74","url":null,"abstract":"We propose in this paper a novel adaptive approach inspired by fluid dynamics as a distributed, scalable, and robust solution to the deployment problem of mobile sensor networks in unknown environments. Our approach is based on the physical principles of fluids through which we model a mobile sensor network as a fluid body and individual nodes as fluid elements. We achieve desirable properties of effective coverage, scalability, and robustness by virtue of the diffusive and self-spreading behavior of compressible fluids as modeled in our deployment approach. Simulation of our deployment strategy shows that the approach is scalable in terms of environment and network size. It is also robust against localization uncertainty, partial operational failure, and dynamic changes in the landscape. In truly unknown environments where the number of nodes to be deployed cannot be determined a priori, our adaptive deployment scheme guarantees thorough coverage of the environment","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124579539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present an adaptive heuristic algorithm for data filtering aimed to measurements of accelerations for probes entering a planetary atmosphere. The filter is based on properties of the median and the quantiles, and its design takes into account the presupposed properties of the signal, in order to achieve a higher precision of the recovered signal. The adaptive parameter is the filtering window width. The adaptation is based on the statistical properties of the signal and on heuristic rules
{"title":"An Adaptive Heuristic Filter for Acceleration","authors":"H. Teodorescu","doi":"10.1109/AHS.2006.18","DOIUrl":"https://doi.org/10.1109/AHS.2006.18","url":null,"abstract":"We present an adaptive heuristic algorithm for data filtering aimed to measurements of accelerations for probes entering a planetary atmosphere. The filter is based on properties of the median and the quantiles, and its design takes into account the presupposed properties of the signal, in order to achieve a higher precision of the recovered signal. The adaptive parameter is the filtering window width. The adaptation is based on the statistical properties of the signal and on heuristic rules","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115740294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This invited paper overviews the low level debug support hardware required for an on-chip pre-deployment debugging system for sensor networks. The solution provides significant program and data trace compression using a low complexity messaging framework. The architecture targets system-on-chip designs with multiple processor cores. The novel debug support is attached through defined interfaces making intellectual property re-use more practical. Synthesis to standard cells shows that the approach is more compact than conventional solutions. Extensions to the overviewed architecture are then proposed to allow support for both reconfigurable circuits and hybrid circuits that contain a mixture of reconfigurable and static cores
{"title":"A Generic On-Chip Debugger for Wireless Sensor Networks","authors":"Andrew B. T. Hopkins, K. Mcdonald-Maier","doi":"10.1109/AHS.2006.4","DOIUrl":"https://doi.org/10.1109/AHS.2006.4","url":null,"abstract":"This invited paper overviews the low level debug support hardware required for an on-chip pre-deployment debugging system for sensor networks. The solution provides significant program and data trace compression using a low complexity messaging framework. The architecture targets system-on-chip designs with multiple processor cores. The novel debug support is attached through defined interfaces making intellectual property re-use more practical. Synthesis to standard cells shows that the approach is more compact than conventional solutions. Extensions to the overviewed architecture are then proposed to allow support for both reconfigurable circuits and hybrid circuits that contain a mixture of reconfigurable and static cores","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114454808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The discrete wavelet transform (DWT), as defined by the image compression standard JPEG-2000, is one of the most time-consuming computations which cannot be efficiently executed on current hardware architectures. This paper presents and compares a number of new, different architectures for domain-specific arrays to efficiently implement various DWT algorithms. A number of different algorithms are mapped to demonstrate the flexibility of these new embedded configurable SoC architectures and their ability to support different implementations having different performance characteristics. Our results demonstrate up to 59 percent improvement to the previous work in literature
{"title":"Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression Techniques","authors":"S. Baloch, T. Arslan, A. Stoica","doi":"10.1109/AHS.2006.32","DOIUrl":"https://doi.org/10.1109/AHS.2006.32","url":null,"abstract":"The discrete wavelet transform (DWT), as defined by the image compression standard JPEG-2000, is one of the most time-consuming computations which cannot be efficiently executed on current hardware architectures. This paper presents and compares a number of new, different architectures for domain-specific arrays to efficiently implement various DWT algorithms. A number of different algorithms are mapped to demonstrate the flexibility of these new embedded configurable SoC architectures and their ability to support different implementations having different performance characteristics. Our results demonstrate up to 59 percent improvement to the previous work in literature","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129726407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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