Pub Date : 2003-06-15DOI: 10.1109/PESC.2003.1218296
O. Ojo, P. Kshirsagar
A new carrier-based discontinuous pulse-width modulation (PWM) scheme anchored on a novel space vector modulation methodology is proposed in this paper for four-leg converters. Using a space vector definition that includes the zero sequence voltage component and partitioning the feasible sixteen modes into three separate sets, the expressions for the modulation signals for the discontinuous carrier based PWM scheme are set forth. Significantly, the switching devices can be clamped either to the positive or negative rail for 120 degrees under all operating conditions of unbalanced three-phase voltages; ensuring the reduction of switching losses and the effective switching frequency of the inverters. The discontinuous PWM modulation methodology proposed which is shown by experimental results to synthesise desirable balanced or unbalanced three-phase voltage sets complements and further clarifies the results of the 3-dimensional space vector modulation scheme (3-D SVM) for four-leg converters reported in the literature.
{"title":"A new carrier-based discontinuous PWM modulation methodology for four-leg voltage source inverters","authors":"O. Ojo, P. Kshirsagar","doi":"10.1109/PESC.2003.1218296","DOIUrl":"https://doi.org/10.1109/PESC.2003.1218296","url":null,"abstract":"A new carrier-based discontinuous pulse-width modulation (PWM) scheme anchored on a novel space vector modulation methodology is proposed in this paper for four-leg converters. Using a space vector definition that includes the zero sequence voltage component and partitioning the feasible sixteen modes into three separate sets, the expressions for the modulation signals for the discontinuous carrier based PWM scheme are set forth. Significantly, the switching devices can be clamped either to the positive or negative rail for 120 degrees under all operating conditions of unbalanced three-phase voltages; ensuring the reduction of switching losses and the effective switching frequency of the inverters. The discontinuous PWM modulation methodology proposed which is shown by experimental results to synthesise desirable balanced or unbalanced three-phase voltage sets complements and further clarifies the results of the 3-dimensional space vector modulation scheme (3-D SVM) for four-leg converters reported in the literature.","PeriodicalId":236199,"journal":{"name":"IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC '03.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130612242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/PESC.2003.1218113
Zhao Dongyuan, Yu Xinjie, C. Jianye, Wang Zanji, L. Bin
How to eliminate the harmonics is one of the key technologies of high-voltage direct current HVDC transmission systems. A hybrid filter, consisting of a double tune passive filter and an active filter, can take full advantage of these performances and is applied in some existing projects. This paper compare the operation of three control schemes due to adopting different harmonic measurement schemes.
{"title":"Novel control schemes for the hybrid filter applied in HVDC according to the different harmonic measurement schemes","authors":"Zhao Dongyuan, Yu Xinjie, C. Jianye, Wang Zanji, L. Bin","doi":"10.1109/PESC.2003.1218113","DOIUrl":"https://doi.org/10.1109/PESC.2003.1218113","url":null,"abstract":"How to eliminate the harmonics is one of the key technologies of high-voltage direct current HVDC transmission systems. A hybrid filter, consisting of a double tune passive filter and an active filter, can take full advantage of these performances and is applied in some existing projects. This paper compare the operation of three control schemes due to adopting different harmonic measurement schemes.","PeriodicalId":236199,"journal":{"name":"IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC '03.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131933720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/PESC.2003.1218163
A. Bryant, P. Palmer, J. Hudgins, E. Santi, X. Kang
A procedure for automatic parameter extraction is outlined, based on accurate physics-based models of the diode, IGBT and associated circuitry. A formal optimisation method is used to refine initial parameter estimates, and is coupled with a hardware testing system to obtain device waveform measurements.
{"title":"The use of a formal optimisation procedure in automatic parameter extraction of power semiconductor devices","authors":"A. Bryant, P. Palmer, J. Hudgins, E. Santi, X. Kang","doi":"10.1109/PESC.2003.1218163","DOIUrl":"https://doi.org/10.1109/PESC.2003.1218163","url":null,"abstract":"A procedure for automatic parameter extraction is outlined, based on accurate physics-based models of the diode, IGBT and associated circuitry. A formal optimisation method is used to refine initial parameter estimates, and is coupled with a hardware testing system to obtain device waveform measurements.","PeriodicalId":236199,"journal":{"name":"IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC '03.","volume":"464 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133835230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/PESC.2003.1218293
M. Lafoz, I. Iglesias, S. Portillo, D. Ugena
This paper presents the experimental results of a diode-clamped three-level inverter used for driving electrical machines. Two different control techniques have been tested for this power converter: a hybrid PWM-SVM voltage control strategy and a double hysteresis-band current control strategy. After checking the good behaviour of these control strategies by simulation results, a small line current THD for a low switching frequency is achieved. Then, a three-level voltage inverter prototype has been developed and both control strategies have been tested upon it. The first one is chosen due to its simplicity, robustness and best ability to filter the current and the second one because a faster and more simple current control can be accomplished. Some simulation results which compare both strategies and some experimental results in the three-level VSI prototype are to be shown in this paper.
{"title":"Experimental results of a three-level voltage source inverter with hysteresis-band current control and hybrid PWM-SVM voltage control","authors":"M. Lafoz, I. Iglesias, S. Portillo, D. Ugena","doi":"10.1109/PESC.2003.1218293","DOIUrl":"https://doi.org/10.1109/PESC.2003.1218293","url":null,"abstract":"This paper presents the experimental results of a diode-clamped three-level inverter used for driving electrical machines. Two different control techniques have been tested for this power converter: a hybrid PWM-SVM voltage control strategy and a double hysteresis-band current control strategy. After checking the good behaviour of these control strategies by simulation results, a small line current THD for a low switching frequency is achieved. Then, a three-level voltage inverter prototype has been developed and both control strategies have been tested upon it. The first one is chosen due to its simplicity, robustness and best ability to filter the current and the second one because a faster and more simple current control can be accomplished. Some simulation results which compare both strategies and some experimental results in the three-level VSI prototype are to be shown in this paper.","PeriodicalId":236199,"journal":{"name":"IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC '03.","volume":"183 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124021157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/PESC.2003.1216590
P. Tan, P. Loh, D. G. Holmes
On many electrified railway systems with single-phase 25 kV industrial frequency supply, the power quality can be particularly poor when conventional SCR-based locomotives are operating, and this constrains the amount of power that can be delivered to the locomotives. This paper presents a shunt compensation system consisting of alternatively a cascaded or a reduced topology multilevel active power filter, and a low rating damping filter. The active filter is controlled by a novel hysteresis current regulation strategy, and both mitigate low order voltage harmonic distortion along the feeder and provides RMS voltage support. The passive filter damps harmonic resonances that are typical in such 25 kV traction systems. The results show that the filter system can significantly increase traction system power transfer capacity with only a relatively small capital investment, allowing older thyristor based locomotives and increased traffic levels to be supported without necessarily requiring a complete system upgrade. Simulation and experimental results are included showing the performance of the filter for both steady state and transient conditions.
{"title":"A robust multilevel hybrid compensation system for 25 kV electrified railway applications","authors":"P. Tan, P. Loh, D. G. Holmes","doi":"10.1109/PESC.2003.1216590","DOIUrl":"https://doi.org/10.1109/PESC.2003.1216590","url":null,"abstract":"On many electrified railway systems with single-phase 25 kV industrial frequency supply, the power quality can be particularly poor when conventional SCR-based locomotives are operating, and this constrains the amount of power that can be delivered to the locomotives. This paper presents a shunt compensation system consisting of alternatively a cascaded or a reduced topology multilevel active power filter, and a low rating damping filter. The active filter is controlled by a novel hysteresis current regulation strategy, and both mitigate low order voltage harmonic distortion along the feeder and provides RMS voltage support. The passive filter damps harmonic resonances that are typical in such 25 kV traction systems. The results show that the filter system can significantly increase traction system power transfer capacity with only a relatively small capital investment, allowing older thyristor based locomotives and increased traffic levels to be supported without necessarily requiring a complete system upgrade. Simulation and experimental results are included showing the performance of the filter for both steady state and transient conditions.","PeriodicalId":236199,"journal":{"name":"IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC '03.","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116981657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/PESC.2003.1218162
T. Tanaka, T. Mizoshiri, E. Suekawa, I. Umesaki, Y. Kawaguchi, J. Donlon
A high voltage intelligent power module (HVIPM) rated at 600 A, 6.5 kV has been developed using an optimized punch through IGBT chip, coordinated free-wheel diode, high quality manufacturing processes, and high performance gate control technology.
{"title":"Development of a high voltage intelligent power module (HVIPM)","authors":"T. Tanaka, T. Mizoshiri, E. Suekawa, I. Umesaki, Y. Kawaguchi, J. Donlon","doi":"10.1109/PESC.2003.1218162","DOIUrl":"https://doi.org/10.1109/PESC.2003.1218162","url":null,"abstract":"A high voltage intelligent power module (HVIPM) rated at 600 A, 6.5 kV has been developed using an optimized punch through IGBT chip, coordinated free-wheel diode, high quality manufacturing processes, and high performance gate control technology.","PeriodicalId":236199,"journal":{"name":"IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC '03.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116778800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/PESC.2003.1218108
S. Berto, S. Bolognani, M. Ceschia, A. Paccagnella, M. Zigliotto
This paper presents the implementation on a field programmable gate array (FPGA) of a space vector modulator (SVM) for a voltage inverter, as an approach to the design of reusable and reconfigurable control software for electric drives. In electric drives control, a traditional "main-program-and-subroutine" architecture involves several software issues that must be re-considered at any hardware platform change. The paper describes the first step of a process whose target is the creation of a library of optimised VHDL modules that incorporates the best expertise on each part of the drive. Due to FPGA structure, the portability is intrinsic and also the flexibility will be preserved, since all new solutions can be evaluated and included in the library. Experimental results, carried on a three-phase voltage inverter, are used to highlight potentials and pitfalls of the proposed approach.
{"title":"FPGA-based random PWM with real-time dead time compensation","authors":"S. Berto, S. Bolognani, M. Ceschia, A. Paccagnella, M. Zigliotto","doi":"10.1109/PESC.2003.1218108","DOIUrl":"https://doi.org/10.1109/PESC.2003.1218108","url":null,"abstract":"This paper presents the implementation on a field programmable gate array (FPGA) of a space vector modulator (SVM) for a voltage inverter, as an approach to the design of reusable and reconfigurable control software for electric drives. In electric drives control, a traditional \"main-program-and-subroutine\" architecture involves several software issues that must be re-considered at any hardware platform change. The paper describes the first step of a process whose target is the creation of a library of optimised VHDL modules that incorporates the best expertise on each part of the drive. Due to FPGA structure, the portability is intrinsic and also the flexibility will be preserved, since all new solutions can be evaluated and included in the library. Experimental results, carried on a three-phase voltage inverter, are used to highlight potentials and pitfalls of the proposed approach.","PeriodicalId":236199,"journal":{"name":"IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC '03.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117342973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/PESC.2003.1218311
D. Vasić, F. Costa, E. Sarraute
This paper is situated in the continuity of our works focused on the use of piezoelectric transformer (PT) in MOSFET/IGBT gate drives. In this paper, a new design method for a gate drive PT is presented. We have previously demonstrated that this kind of transformer can be successfully used in insulated MOSFETs/IGBT's gate drive circuits. An optimized multi-layered PT working in the second thickness mode has been studied for transmitting signal and energy in a gate drive circuit. Based on an analytical Mason model, the design method gives the minimal size of the multi-layer PT. Thickness of the PT is given by its mechanical resonance frequency and by maximum electrical field in the material. This method takes into account mechanical losses and heating of the piezoelectric material. Area of the PT is calculated considering the required secondary power P/sub 2/ and heating of the material. This analytical design method can be extended to predict the characteristics of the PT: gain, transmitted power, efficiency and heating of piezoelectric materials according to load resistance. A prototype of a PT based on this design process was fabricated and tested experimentally. Piezoelectric material used for primary and secondary layers is lead titanate, PbTiO/sub 3/, polarized along the thickness. Insulation between the primary and the secondary is achieved by a 300 /spl mu/m thickness layer of alumina, Al/sub 2/O/sub 3/. All calculated characteristics have been confirmed by measurements.
{"title":"A new method to design piezoelectric transformer used in MOSFET and IGBT gate drive circuits","authors":"D. Vasić, F. Costa, E. Sarraute","doi":"10.1109/PESC.2003.1218311","DOIUrl":"https://doi.org/10.1109/PESC.2003.1218311","url":null,"abstract":"This paper is situated in the continuity of our works focused on the use of piezoelectric transformer (PT) in MOSFET/IGBT gate drives. In this paper, a new design method for a gate drive PT is presented. We have previously demonstrated that this kind of transformer can be successfully used in insulated MOSFETs/IGBT's gate drive circuits. An optimized multi-layered PT working in the second thickness mode has been studied for transmitting signal and energy in a gate drive circuit. Based on an analytical Mason model, the design method gives the minimal size of the multi-layer PT. Thickness of the PT is given by its mechanical resonance frequency and by maximum electrical field in the material. This method takes into account mechanical losses and heating of the piezoelectric material. Area of the PT is calculated considering the required secondary power P/sub 2/ and heating of the material. This analytical design method can be extended to predict the characteristics of the PT: gain, transmitted power, efficiency and heating of piezoelectric materials according to load resistance. A prototype of a PT based on this design process was fabricated and tested experimentally. Piezoelectric material used for primary and secondary layers is lead titanate, PbTiO/sub 3/, polarized along the thickness. Insulation between the primary and the secondary is achieved by a 300 /spl mu/m thickness layer of alumina, Al/sub 2/O/sub 3/. All calculated characteristics have been confirmed by measurements.","PeriodicalId":236199,"journal":{"name":"IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC '03.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114307282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/PESC.2003.1218118
C. Klumpner, F. Blaabjerg, P. Thogersen
This paper analyses possible converter topologies suitable for the next generation of integrated motor drives and analyzes them in respect to their performance, hardware requirements (both semiconductors and passive devices) and efficiency, which determines the cooling requirements. Because in all the converter topologies an IGBT bridge inversion stage is used, similar performance is expected on the motor side and only analysis of the input side is carried out. These topologies are evaluated for a 4 kW power level and two topologies are proposed, one for low-cost and another for high-performance.
{"title":"Converter topologies with low passive components usage for the next generation of integrated motor drives","authors":"C. Klumpner, F. Blaabjerg, P. Thogersen","doi":"10.1109/PESC.2003.1218118","DOIUrl":"https://doi.org/10.1109/PESC.2003.1218118","url":null,"abstract":"This paper analyses possible converter topologies suitable for the next generation of integrated motor drives and analyzes them in respect to their performance, hardware requirements (both semiconductors and passive devices) and efficiency, which determines the cooling requirements. Because in all the converter topologies an IGBT bridge inversion stage is used, similar performance is expected on the motor side and only analysis of the input side is carried out. These topologies are evaluated for a 4 kW power level and two topologies are proposed, one for low-cost and another for high-performance.","PeriodicalId":236199,"journal":{"name":"IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC '03.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116147743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/PESC.2003.1216798
Y. Xing, Lipei Huang, Yangguang Yan
A distributed control for redundant parallel inverters, based on current regulation, with instantaneous current sharing is proposed. The voltage and current references are the only two shared bus signals among the modules, which generated from all the individual inverters in parallel operation. It is proved mathematically that the parallel system, without extra current deviation control loop, operates with the equivalent transfer function (therefore the same control property) of the individuals and presents load balance performance as good as master-slave method. Simulated and experimental results are given to verify the analysis.
{"title":"Redundant parallel control for current regulated inverters with instantaneous current sharing","authors":"Y. Xing, Lipei Huang, Yangguang Yan","doi":"10.1109/PESC.2003.1216798","DOIUrl":"https://doi.org/10.1109/PESC.2003.1216798","url":null,"abstract":"A distributed control for redundant parallel inverters, based on current regulation, with instantaneous current sharing is proposed. The voltage and current references are the only two shared bus signals among the modules, which generated from all the individual inverters in parallel operation. It is proved mathematically that the parallel system, without extra current deviation control loop, operates with the equivalent transfer function (therefore the same control property) of the individuals and presents load balance performance as good as master-slave method. Simulated and experimental results are given to verify the analysis.","PeriodicalId":236199,"journal":{"name":"IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC '03.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127320600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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