Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957337
S. Sridhara, Naresh R Shanbhag
We propose a technique for designing low-power fast Fourier transform (FFT) processors with applications in next generation wireless LAN and wireless access systems. The proposed low-power technique is based on the general principle of soft digital signal processing where voltage overscaling (VOS) (scaling the supply voltage beyond the critical voltage V/sub dd-crit/ required for correct operation) is applied in conjunction with algorithmic noise-tolerance (ANT) techniques. We propose an ANT technique referred to as reduced precision redundancy for compensating the degradation in the signal-to-noise ratio (SNR) at an FFT output due to VOS. Simulation results using the proposed scheme with 0.25 /spl mu/m standard CMOS technology show that the power consumption in a butterfly functional unit of an FFT processor can be reduced by 44% over a conventional voltage-scaled system without any SNR loss in the context of a typical orthogonal frequency division multiplexing (OFDM) based WLAN system.
{"title":"Low-power FFT via reduced precision redundancy","authors":"S. Sridhara, Naresh R Shanbhag","doi":"10.1109/SIPS.2001.957337","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957337","url":null,"abstract":"We propose a technique for designing low-power fast Fourier transform (FFT) processors with applications in next generation wireless LAN and wireless access systems. The proposed low-power technique is based on the general principle of soft digital signal processing where voltage overscaling (VOS) (scaling the supply voltage beyond the critical voltage V/sub dd-crit/ required for correct operation) is applied in conjunction with algorithmic noise-tolerance (ANT) techniques. We propose an ANT technique referred to as reduced precision redundancy for compensating the degradation in the signal-to-noise ratio (SNR) at an FFT output due to VOS. Simulation results using the proposed scheme with 0.25 /spl mu/m standard CMOS technology show that the power consumption in a butterfly functional unit of an FFT processor can be reduced by 44% over a conventional voltage-scaled system without any SNR loss in the context of a typical orthogonal frequency division multiplexing (OFDM) based WLAN system.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126297742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957344
Tim Kogel, Andreas Wieferink, H. Meyr, A. Kroll
We propose a system level design and refinement methodology based on the SystemC class library. We address design space exploration and performance profiling at the highest possible level of abstraction. System level design starts with the initial functional specification and validation of the system behavior in SystemC. The refinement methodology covers architecture exploration and results in an executable system architecture model, which is able to generate the relevant profiling data and to verify if the chosen architecture meets the performance requirements. We have applied this methodology to a 100 million gate design of a 3D graphic processor. We were able to demonstrate the feasibility and define the final system architecture within 2 months. This 3D processor implements the ray-tracing rendering paradigm on one chip allowing real time rendering of 3D scenes with photo-realistic quality. Based on the results of this case study, we present the benefits of our methodology to define successively a feasible system architecture coping with the processing and memory bandwidth requirements.
{"title":"SystemC based architecture exploration of a 3D graphic processor","authors":"Tim Kogel, Andreas Wieferink, H. Meyr, A. Kroll","doi":"10.1109/SIPS.2001.957344","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957344","url":null,"abstract":"We propose a system level design and refinement methodology based on the SystemC class library. We address design space exploration and performance profiling at the highest possible level of abstraction. System level design starts with the initial functional specification and validation of the system behavior in SystemC. The refinement methodology covers architecture exploration and results in an executable system architecture model, which is able to generate the relevant profiling data and to verify if the chosen architecture meets the performance requirements. We have applied this methodology to a 100 million gate design of a 3D graphic processor. We were able to demonstrate the feasibility and define the final system architecture within 2 months. This 3D processor implements the ray-tracing rendering paradigm on one chip allowing real time rendering of 3D scenes with photo-realistic quality. Based on the results of this case study, we present the benefits of our methodology to define successively a feasible system architecture coping with the processing and memory bandwidth requirements.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129995251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957348
J. Kang, B. G. Jo, M. Sunwoo
This paper proposes a low power and area efficient FIR filter chip for partial-response maximum likelihood (PRML) disk drive read channels, which is a 6-b, 8-tap digital FIR filter. The proposed filter employs a parallel processing architecture and consists of four pipeline stages. It uses the modified Booth algorithm for multiplication and compressor logic for addition. CMOS pass-transistor logic is used for low power consumption and single-rail logic is used to reduce the chip area. The proposed filter chip, using the 0.65 /spl mu/m technology, dissipates 120 mW at 100 Hz, uses the 3.3 V power supply and occupies 1.88/spl times/1.38 mm/sup 2/. The chip shows about 11% power reduction and about 15% area reduction compared with existing architectures. This chip was fabricated by Hyundai Semiconductor.
{"title":"Implementation of an efficient FIR filter chip for PRML read channels","authors":"J. Kang, B. G. Jo, M. Sunwoo","doi":"10.1109/SIPS.2001.957348","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957348","url":null,"abstract":"This paper proposes a low power and area efficient FIR filter chip for partial-response maximum likelihood (PRML) disk drive read channels, which is a 6-b, 8-tap digital FIR filter. The proposed filter employs a parallel processing architecture and consists of four pipeline stages. It uses the modified Booth algorithm for multiplication and compressor logic for addition. CMOS pass-transistor logic is used for low power consumption and single-rail logic is used to reduce the chip area. The proposed filter chip, using the 0.65 /spl mu/m technology, dissipates 120 mW at 100 Hz, uses the 3.3 V power supply and occupies 1.88/spl times/1.38 mm/sup 2/. The chip shows about 11% power reduction and about 15% area reduction compared with existing architectures. This chip was fabricated by Hyundai Semiconductor.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133139156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957336
N. Sakamoto, W. Kobayashi, T. Onoye, I. Shirakawa
This paper describes a DSP implementation of a real-time 3D sound localization algorithm. A distinctive feature of this implementation is that the audible frequency band is divided into three on the basis of the analysis of the effects of sound diffraction, such that in these three subbands specific schemes of the 3D sound localization are devised with the use of an IIR filter, three parametric equalizers, and a comb filter, respectively, so as to be run real-time on a 16-bit fixed-point DSP at a low frequency of 50 MHz, maintaining the high-quality sound localization. As a result, this 3D sound localization scheme can be applied to mobile applications such as headphones and a handy-phone with the use of an embedded DSP.
{"title":"DSP implementation of low computational 3D sound localization algorithm","authors":"N. Sakamoto, W. Kobayashi, T. Onoye, I. Shirakawa","doi":"10.1109/SIPS.2001.957336","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957336","url":null,"abstract":"This paper describes a DSP implementation of a real-time 3D sound localization algorithm. A distinctive feature of this implementation is that the audible frequency band is divided into three on the basis of the analysis of the effects of sound diffraction, such that in these three subbands specific schemes of the 3D sound localization are devised with the use of an IIR filter, three parametric equalizers, and a comb filter, respectively, so as to be run real-time on a 16-bit fixed-point DSP at a low frequency of 50 MHz, maintaining the high-quality sound localization. As a result, this 3D sound localization scheme can be applied to mobile applications such as headphones and a handy-phone with the use of an embedded DSP.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130479462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957351
Y. Hwang, Yun-Chiang Wang, Shi-Shen Wang
Shape coding is essential for video object based video compression such as MPEG-4. The shape mask specifies a video object's transparency and opaque characteristics during the video composition process. With shape information, we may perform shape-adaptive processing, e.g. shape adaptive DWT, to save both computation and communication overheads. We propose an efficient shape coding scheme called differential chain coding. Experimental results show that it can outperform all existing shape coding methods, including the well-known CAE method. In the decoding phase, we employ the concepts of change pixels and devise a new scheme to construct the binary alpha plane (shape mask) from the shape contour. Based on the proposed scheme, a novel VLSI architecture design for the shape decoder is developed. Synthesis and simulation results also indicate the design can process over 1,800 QCIF frames per second with very little hardware complexity.
{"title":"An efficient shape coding scheme and its codec design","authors":"Y. Hwang, Yun-Chiang Wang, Shi-Shen Wang","doi":"10.1109/SIPS.2001.957351","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957351","url":null,"abstract":"Shape coding is essential for video object based video compression such as MPEG-4. The shape mask specifies a video object's transparency and opaque characteristics during the video composition process. With shape information, we may perform shape-adaptive processing, e.g. shape adaptive DWT, to save both computation and communication overheads. We propose an efficient shape coding scheme called differential chain coding. Experimental results show that it can outperform all existing shape coding methods, including the well-known CAE method. In the decoding phase, we employ the concepts of change pixels and devise a new scheme to construct the binary alpha plane (shape mask) from the shape contour. Based on the proposed scheme, a novel VLSI architecture design for the shape decoder is developed. Synthesis and simulation results also indicate the design can process over 1,800 QCIF frames per second with very little hardware complexity.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122048956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957345
M. Boyle, A. Fagan
The use of a linear equaliser to shorten the impulse response of a channel to a shorter desired impulse response (DIR) prior to a Viterbi algorithm (VA) detection of the data is a well-known technique. Also OFDM systems often require channel truncation. It has previously been shown that for dynamic channels it is beneficial to operate a number of equalisers in parallel, each targeted on a different DIR. Each equaliser is followed by an individual VA. A simple decision rule is used to select which of the VA outputs is presented as the actual decision. We refer to this strategy as switched DIR equalisation. A catastrophic error mode is observed in the operation of adaptive DIR systems in slowly varying channels. This error mode causes the equaliser to become severely maladjusted. The system cannot spontaneously recover from this situation. This paper reviews the switched DIR equalisation system and explains the mechanism underlying the error mode in the adaptive DIR system. Simulation results are presented that indicate the efficacy of the dual switched DIR MLSE-VA to operate successfully in comparison to adaptive DIR MLSE-VA systems in time varying frequency selective Rayleigh fading channels.
{"title":"A catastrophic error mode in adaptive predictive DIR equalisation of dynamic channels","authors":"M. Boyle, A. Fagan","doi":"10.1109/SIPS.2001.957345","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957345","url":null,"abstract":"The use of a linear equaliser to shorten the impulse response of a channel to a shorter desired impulse response (DIR) prior to a Viterbi algorithm (VA) detection of the data is a well-known technique. Also OFDM systems often require channel truncation. It has previously been shown that for dynamic channels it is beneficial to operate a number of equalisers in parallel, each targeted on a different DIR. Each equaliser is followed by an individual VA. A simple decision rule is used to select which of the VA outputs is presented as the actual decision. We refer to this strategy as switched DIR equalisation. A catastrophic error mode is observed in the operation of adaptive DIR systems in slowly varying channels. This error mode causes the equaliser to become severely maladjusted. The system cannot spontaneously recover from this situation. This paper reviews the switched DIR equalisation system and explains the mechanism underlying the error mode in the adaptive DIR system. Simulation results are presented that indicate the efficacy of the dual switched DIR MLSE-VA to operate successfully in comparison to adaptive DIR MLSE-VA systems in time varying frequency selective Rayleigh fading channels.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122225729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957361
P. Mogensen
Summary form only given, as follows. High speed downlink packet access (HSDPA) is currently being standardized in 3GPP for R5 and R6. HSDPA offers peak data rates exceeding 10 Mbit/s and significantly enhances the spectral efficiency of UMTS for packet services compared to R99. The draft HSDPA specifications includes advanced concepts of: adaptive modulation and coding schemes (up to 64 QAM); fast SAW hybrid ARQ; fast packet scheduling; potentially, also, fast cell selection and MIMO channel concepts.
{"title":"High speed downlink packet access (HSDPA)-the path towards 3.5G","authors":"P. Mogensen","doi":"10.1109/SIPS.2001.957361","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957361","url":null,"abstract":"Summary form only given, as follows. High speed downlink packet access (HSDPA) is currently being standardized in 3GPP for R5 and R6. HSDPA offers peak data rates exceeding 10 Mbit/s and significantly enhances the spectral efficiency of UMTS for packet services compared to R99. The draft HSDPA specifications includes advanced concepts of: adaptive modulation and coding schemes (up to 64 QAM); fast SAW hybrid ARQ; fast packet scheduling; potentially, also, fast cell selection and MIMO channel concepts.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123182100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957343
Han-Chiang Chen
The cost-effective hardware architecture of a low bit rate 1.6 Kbit/s LPC (linear predictive coefficient)-based vocoder is proposed. The proposed architecture integrates both algorithms of the encoder and decoder. In the encoder, a simple finite state machine is presented to compute the autocorrelation function of speech. At the decoder side, efficient circuits are designed to transfer LSP (lne spectrum pair) to LPC. Only 29000 gate counts of XILINX XC4036XL FPGA are used to implement the vocoder.
{"title":"Efficient implementation of low bit rate 1.6 Kbps speech coder using field programmable gate arrays","authors":"Han-Chiang Chen","doi":"10.1109/SIPS.2001.957343","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957343","url":null,"abstract":"The cost-effective hardware architecture of a low bit rate 1.6 Kbit/s LPC (linear predictive coefficient)-based vocoder is proposed. The proposed architecture integrates both algorithms of the encoder and decoder. In the encoder, a simple finite state machine is presented to compute the autocorrelation function of speech. At the decoder side, efficient circuits are designed to transfer LSP (lne spectrum pair) to LPC. Only 29000 gate counts of XILINX XC4036XL FPGA are used to implement the vocoder.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128603925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2001.957328
Tong Zhang, K. Parhi
In the past few years, Gallager's low-density parity-check (LDPC) codes received a lot of attention and many efforts have been devoted to analyzing and improving their error-correcting performance. However, little consideration has been given to the LDPC decoder VLSI implementation. The straightforward fully parallel decoder architecture usually incurs too high complexity for many practical purposes and should be transformed to a partly parallel realization. Unfortunately, due to the randomness of LDPC codes, it is nearly impossible to develop an effective transformation for an arbitrarily given LDPC code. We propose a joint code and decoder design approach to construct a class of (3, k)-regular LDPC codes which exactly fit a partly parallel decoder implementation and have a very good performance. Moreover, for such LDPC codes, we propose a systematic, efficient encoding scheme by effectively exploiting the sparseness of its parity check matrix.
{"title":"VLSI implementation-oriented (3, k)-regular low-density parity-check codes","authors":"Tong Zhang, K. Parhi","doi":"10.1109/SIPS.2001.957328","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957328","url":null,"abstract":"In the past few years, Gallager's low-density parity-check (LDPC) codes received a lot of attention and many efforts have been devoted to analyzing and improving their error-correcting performance. However, little consideration has been given to the LDPC decoder VLSI implementation. The straightforward fully parallel decoder architecture usually incurs too high complexity for many practical purposes and should be transformed to a partly parallel realization. Unfortunately, due to the randomness of LDPC codes, it is nearly impossible to develop an effective transformation for an arbitrarily given LDPC code. We propose a joint code and decoder design approach to construct a class of (3, k)-regular LDPC codes which exactly fit a partly parallel decoder implementation and have a very good performance. Moreover, for such LDPC codes, we propose a systematic, efficient encoding scheme by effectively exploiting the sparseness of its parity check matrix.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"8 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124344869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2001.957355
Y. Andreopoulos, P. Schelkens, J. Cornelis
This paper compares various software implementations of the 2D binary-tree wavelet decomposition by analyzing the data-related cache penalties in processor-based platforms. Such penalties appear to be the dominant factors that determine performance in this type of application. The comparisons include various image-scanning techniques, from the classical row-column approach to the local wavelet transform and the line-based wavelet transform, which are proposed in the framework of multimedia coding standards. For a conflict-free cache model, a theoretical framework is constructed allowing for predictions of the data-cache penalties that are expected to diminish the system performance. The theoretical results are verified with measurements from simulations and also from a real platform.
{"title":"Analysis of wavelet transform implementations for image and texture coding applications in programmable platforms","authors":"Y. Andreopoulos, P. Schelkens, J. Cornelis","doi":"10.1109/SIPS.2001.957355","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957355","url":null,"abstract":"This paper compares various software implementations of the 2D binary-tree wavelet decomposition by analyzing the data-related cache penalties in processor-based platforms. Such penalties appear to be the dominant factors that determine performance in this type of application. The comparisons include various image-scanning techniques, from the classical row-column approach to the local wavelet transform and the line-based wavelet transform, which are proposed in the framework of multimedia coding standards. For a conflict-free cache model, a theoretical framework is constructed allowing for predictions of the data-cache penalties that are expected to diminish the system performance. The theoretical results are verified with measurements from simulations and also from a real platform.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129198922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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