Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721208
J. Woodall, P. Kirchner, D. Rogers, M. Chisholm, J. Rosenberg
Until about five years ago, nearly all optoelectronic and high speed devices with heterojunction structures were made with materials which were lattice-matched, i.e. the unstrained lattice constant of the materials is approximately equal. A large portion of these devices were made from either the GaAs/GaAlAs or InP/InGaAsP system. Early attempts to form devices such as lasers and superlattices using mismatched systems, e.g. GaAs/GaAsP, were disappointing (l), presumably due to the large density of defects at optoelectronically active interfaces needed to accommodate the misfit. This negative result lead to "conventional wisdom'' that active heterojunctions needed to be lattice-matched. Thus, for over a decade, research on such devices as lasers, HEMTs, LEDs, HBTs, and solar cells was restricted to mainly lattice-matched systems. '
{"title":"So Who Needs Lattice Matched Heterojunctions Anyway?","authors":"J. Woodall, P. Kirchner, D. Rogers, M. Chisholm, J. Rosenberg","doi":"10.1109/CORNEL.1987.721208","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721208","url":null,"abstract":"Until about five years ago, nearly all optoelectronic and high speed devices with heterojunction structures were made with materials which were lattice-matched, i.e. the unstrained lattice constant of the materials is approximately equal. A large portion of these devices were made from either the GaAs/GaAlAs or InP/InGaAsP system. Early attempts to form devices such as lasers and superlattices using mismatched systems, e.g. GaAs/GaAsP, were disappointing (l), presumably due to the large density of defects at optoelectronically active interfaces needed to accommodate the misfit. This negative result lead to \"conventional wisdom'' that active heterojunctions needed to be lattice-matched. Thus, for over a decade, research on such devices as lasers, HEMTs, LEDs, HBTs, and solar cells was restricted to mainly lattice-matched systems. '","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125164803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721228
D. Allee, P. de la Houssaye, D. Schlom, B. Langley, J. Harris, R. Pease
Ultra-high resolution electron beam lithography (UHREBL) has been used for many years to write nanometer scale patterns in various materials. In 1960, sub-100 nm features were made in thin membranes1. Only recently has UHREBL been applied to fabrication of electronic devices2. Our laboratory is very interested in investigating the device physics of traditional electronic devices with nanometer features and novel devices that depend on the nanometer features for proper operation. Here we describe the fabrication and the device characterization of the former, specifically MESFETs with recessed gates as short as 65 nm. The high frequency performance of MESFETs is improved primarily by reducing the gate length, parasitic source and gate resistances, and the gate capacitance. An optimized short gate length device will reduce the noise figure and increase fmax for microwave amplifiers. In this paper, we also discuss the advantages of using a high Tc superconducting gate electrode for ultra-submicron FETs as a means to reduce the gate resistance.
{"title":"Sub-100 nm Gate Length GaAs MESFETs Fabricated By Molecular Beam Epitaxy And Electron Beam Lithography","authors":"D. Allee, P. de la Houssaye, D. Schlom, B. Langley, J. Harris, R. Pease","doi":"10.1109/CORNEL.1987.721228","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721228","url":null,"abstract":"Ultra-high resolution electron beam lithography (UHREBL) has been used for many years to write nanometer scale patterns in various materials. In 1960, sub-100 nm features were made in thin membranes1. Only recently has UHREBL been applied to fabrication of electronic devices2. Our laboratory is very interested in investigating the device physics of traditional electronic devices with nanometer features and novel devices that depend on the nanometer features for proper operation. Here we describe the fabrication and the device characterization of the former, specifically MESFETs with recessed gates as short as 65 nm. The high frequency performance of MESFETs is improved primarily by reducing the gate length, parasitic source and gate resistances, and the gate capacitance. An optimized short gate length device will reduce the noise figure and increase fmax for microwave amplifiers. In this paper, we also discuss the advantages of using a high Tc superconducting gate electrode for ultra-submicron FETs as a means to reduce the gate resistance.","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114561329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721217
C. S. Lam, C. Fonstad
The performance of MODFET's as microwave power devices6v7 is limited by the relatively low sheet carrier density in the 2-dimensional electron gas and the low drain breakdown voltage due to the highly doped Alo.3 Gao7 As. In conventional modulation-doped structures, there is always a tradeoff between the gate breakdown voltage and the doping level in the AlGaAs. A higher doping level implies higher sheet carrier concentration but reduced gate breakdown voltage. To circumvent this problem, several research groups have fabricated multiplechannel MODFET'S.~.~ Such devices not only have a higher sheet carrier concentration in the 2-dimensional electron gas, they also have a lower output conductance and a higher drain breakdown voltage. This is due to the confinement by the Si-AIGaAs layers underneath each channel. In this work, a new approach was used to improve the performance of MODFETs. A very shallow, low-dose p-type implantation was performed under the gate region, directly above the 2dimensional electron gas of the channel. Significant improvements were observed in the source-drain breakdown voltage and the gate-channel forward turn-on and reverse breakdown volatges. In addition, extremely low output conductance and very high &1 to gd ratios were obtained. To clearly understand the effect of implantation and high temperature annealings on device performance, the dependence of VDS,max, gd, gm and V, on annealing temperatures ranging from 78OOC to 93OOC was studied. EXPERIMENTAL METHODS
{"title":"Improvements In Modfet Performance Realized Through ION Implantation In The Gate Region","authors":"C. S. Lam, C. Fonstad","doi":"10.1109/CORNEL.1987.721217","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721217","url":null,"abstract":"The performance of MODFET's as microwave power devices6v7 is limited by the relatively low sheet carrier density in the 2-dimensional electron gas and the low drain breakdown voltage due to the highly doped Alo.3 Gao7 As. In conventional modulation-doped structures, there is always a tradeoff between the gate breakdown voltage and the doping level in the AlGaAs. A higher doping level implies higher sheet carrier concentration but reduced gate breakdown voltage. To circumvent this problem, several research groups have fabricated multiplechannel MODFET'S.~.~ Such devices not only have a higher sheet carrier concentration in the 2-dimensional electron gas, they also have a lower output conductance and a higher drain breakdown voltage. This is due to the confinement by the Si-AIGaAs layers underneath each channel. In this work, a new approach was used to improve the performance of MODFETs. A very shallow, low-dose p-type implantation was performed under the gate region, directly above the 2dimensional electron gas of the channel. Significant improvements were observed in the source-drain breakdown voltage and the gate-channel forward turn-on and reverse breakdown volatges. In addition, extremely low output conductance and very high &1 to gd ratios were obtained. To clearly understand the effect of implantation and high temperature annealings on device performance, the dependence of VDS,max, gd, gm and V, on annealing temperatures ranging from 78OOC to 93OOC was studied. EXPERIMENTAL METHODS","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123637424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721242
R. C. Clarke, M. Driver, T. O’Keeffe, R. A. Wickstrom
Monolithic gallium arsenide vertical FETs have been fabricated with a suspended gate, 0.7 /spl mu/m long, and a drain on top of a vertical pillar 4 /spl mu/m high and 0.3 /spl mu/m thick with a doping concentration of 2 x 10 /sup 17/ cm/sup -3/. VFET channels were combined with air bridges attached to bond pads situated on a semi-insulating substrate. A computer-generated VFET equivalent circuit based on s-parameters indicated a source-drain feedback capacitance of 0.008 pF at 240 /spl mu/m, which is an order of magnitude lower than has been observed in planar MESFETs, with an associated VFET output impedance of 1230 ohm at 240 /spl mu/m. Under RF test, VFETs yielded 11.3 dB maximum stable gain at 18 GHz with an F/sub t/ of 13 GHz and an extrapolated F /sub max/of 67 GHz.
{"title":"Fabrication Technology For Monolithic GaAs VFETs*","authors":"R. C. Clarke, M. Driver, T. O’Keeffe, R. A. Wickstrom","doi":"10.1109/CORNEL.1987.721242","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721242","url":null,"abstract":"Monolithic gallium arsenide vertical FETs have been fabricated with a suspended gate, 0.7 /spl mu/m long, and a drain on top of a vertical pillar 4 /spl mu/m high and 0.3 /spl mu/m thick with a doping concentration of 2 x 10 /sup 17/ cm/sup -3/. VFET channels were combined with air bridges attached to bond pads situated on a semi-insulating substrate. A computer-generated VFET equivalent circuit based on s-parameters indicated a source-drain feedback capacitance of 0.008 pF at 240 /spl mu/m, which is an order of magnitude lower than has been observed in planar MESFETs, with an associated VFET output impedance of 1230 ohm at 240 /spl mu/m. Under RF test, VFETs yielded 11.3 dB maximum stable gain at 18 GHz with an F/sub t/ of 13 GHz and an extrapolated F /sub max/of 67 GHz.","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126980738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721233
W. Goodhue, S. Pang, M. Hollis, J. Donnelly
Angled ion beam assisted etching (IBAE) has been used in conjunction with a variety of lithographic techniques to produce structures in GaAs and GaAlAs with controlled side-wall geometries. In the IBAE process an argon ion beam and a jet of chlorine gas are simultaneously incident on the sample. The etching occurs due to a chemical process involving chlorine, but is highly anisotropic because of the argon ion beam. In fact, the slope of the etched wall is determined by the angle at which the sample is tilted with respect to the ion beam. A number of different side-wall contours have been generated by using fixed tilt angles and computer-controlled dynamic tilting. We are currently utilizing this technology to fabricate vertical field effect transistors (FETs), resonant tunneling transistors, surface emmitting laser arrays and quantum-wire structures. This article describes the angled IBAE technique and its use to fabricate novel devices and structures. The basic chlorine IBAE and angled chlorine IBAE processes and equipment have been described elsewhere. 1-3 A schematic drawingof the etching geometry and computer-controlled sample stage used for angled etching is shown in Fig. 1. The tilt angle of the wafer is defined as the angle formed by the normal of the wafer surface to the axis of the argon ion beam, shown as 6 in Fig. 1. In angled chlorine IBAE the tilt angle is also the angle that the etched sidewall makes with the normal of the wafer surface. Figure 2 shows a scanning electron microscope (SEM) micrograph of etched walls in (100) GaAs with the edge alignment along the (01 1) cleavage plane. The first micrograph shows a sidewall etched at four different tilt angles for four different time intervals. The tilt angle schedule was 30° for 20 min, 40° for 10 min, 50° for 5 min, and 60° for 2.5 min. The second micrograph shows a curved sidewall obtained by computer-controlled etching using 800 discrete tilt angles. Etching was initiated with the ion beam 35O from the normal to the sample, and the angular motion of the sample holder was accelerated during the run. As the angle between the ion beam and the sample normal increases, the top edge of the mask shadows areas with more vertical sidewalls so that virtually any concave shape can be generated. For this work we adjusted the system operating parameters to give a normal-incident etch rate of 40 to 50 nm min-l in GaAs. We operated the system with a 500-eV argon ion beam at a current density of 0.02 rnA cm-2 which gave an argon ion beam pressure of 0.1 mTorr at the sample surface. The chlorine beam pressure at the sample surface was 2.8 mTorr. With these parameters the normal-incidence etch rates for A Ga As with x from 0.08 to 0.80 were 40 nm mine' to within 10%. No roughness was observed atbakA1GaAs heterointerfaces. The masking materials were baked AZ- 1470 photoresist, pyrolytically deposited phosphosilicate glass and evaporated nickel. The respective etch rates for these materials were 4.7
{"title":"Advanced Device Fabrication With Angled Chlorine Ion Beam Assisted Etching","authors":"W. Goodhue, S. Pang, M. Hollis, J. Donnelly","doi":"10.1109/CORNEL.1987.721233","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721233","url":null,"abstract":"Angled ion beam assisted etching (IBAE) has been used in conjunction with a variety of lithographic techniques to produce structures in GaAs and GaAlAs with controlled side-wall geometries. In the IBAE process an argon ion beam and a jet of chlorine gas are simultaneously incident on the sample. The etching occurs due to a chemical process involving chlorine, but is highly anisotropic because of the argon ion beam. In fact, the slope of the etched wall is determined by the angle at which the sample is tilted with respect to the ion beam. A number of different side-wall contours have been generated by using fixed tilt angles and computer-controlled dynamic tilting. We are currently utilizing this technology to fabricate vertical field effect transistors (FETs), resonant tunneling transistors, surface emmitting laser arrays and quantum-wire structures. This article describes the angled IBAE technique and its use to fabricate novel devices and structures. The basic chlorine IBAE and angled chlorine IBAE processes and equipment have been described elsewhere. 1-3 A schematic drawingof the etching geometry and computer-controlled sample stage used for angled etching is shown in Fig. 1. The tilt angle of the wafer is defined as the angle formed by the normal of the wafer surface to the axis of the argon ion beam, shown as 6 in Fig. 1. In angled chlorine IBAE the tilt angle is also the angle that the etched sidewall makes with the normal of the wafer surface. Figure 2 shows a scanning electron microscope (SEM) micrograph of etched walls in (100) GaAs with the edge alignment along the (01 1) cleavage plane. The first micrograph shows a sidewall etched at four different tilt angles for four different time intervals. The tilt angle schedule was 30° for 20 min, 40° for 10 min, 50° for 5 min, and 60° for 2.5 min. The second micrograph shows a curved sidewall obtained by computer-controlled etching using 800 discrete tilt angles. Etching was initiated with the ion beam 35O from the normal to the sample, and the angular motion of the sample holder was accelerated during the run. As the angle between the ion beam and the sample normal increases, the top edge of the mask shadows areas with more vertical sidewalls so that virtually any concave shape can be generated. For this work we adjusted the system operating parameters to give a normal-incident etch rate of 40 to 50 nm min-l in GaAs. We operated the system with a 500-eV argon ion beam at a current density of 0.02 rnA cm-2 which gave an argon ion beam pressure of 0.1 mTorr at the sample surface. The chlorine beam pressure at the sample surface was 2.8 mTorr. With these parameters the normal-incidence etch rates for A Ga As with x from 0.08 to 0.80 were 40 nm mine' to within 10%. No roughness was observed atbakA1GaAs heterointerfaces. The masking materials were baked AZ- 1470 photoresist, pyrolytically deposited phosphosilicate glass and evaporated nickel. The respective etch rates for these materials were 4.7 ","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"24 Suppl 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114335371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721224
A. Kastalsky, A. Grinberg
{"title":"Novel High-speed Transistor Based On Charge Emission From A Quantum Well","authors":"A. Kastalsky, A. Grinberg","doi":"10.1109/CORNEL.1987.721224","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721224","url":null,"abstract":"","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":" 121","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120834629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721247
A. Al‐Omar, J. Krusius, Z. Greenwald, D. Woodard, A. Calawa, L. Eastman
A new transport formulation for large signal time-dependent hot electron transport in graded and abrupt heterostructures has been developed and implemented in a self-consistent ensemble Monte Carlo code. It has been used to explore the microscopic physics of Gunn diodes with a heterojunction launcher cathode. It is shown that previous frequency limits for Gunn diodes are too conservative and that a significant reduction of the dead zone at the cathode is possible with heterojunction designs.
{"title":"Space Charge Effects On Heterojunction Cathode (al-Ga)as Gunn Oscillators","authors":"A. Al‐Omar, J. Krusius, Z. Greenwald, D. Woodard, A. Calawa, L. Eastman","doi":"10.1109/CORNEL.1987.721247","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721247","url":null,"abstract":"A new transport formulation for large signal time-dependent hot electron transport in graded and abrupt heterostructures has been developed and implemented in a self-consistent ensemble Monte Carlo code. It has been used to explore the microscopic physics of Gunn diodes with a heterojunction launcher cathode. It is shown that previous frequency limits for Gunn diodes are too conservative and that a significant reduction of the dead zone at the cathode is possible with heterojunction designs.","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125720520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721211
K. Weingarten, M. Rodwell, D. Bloom
The principles of electrooptic sampling for high-speed testing of GaAs IC, its capabilities as both a time-domain sampling oscilloscope and a frequency-domain network analyzer, and recent measurements results are described. Applications of this system include measurements of internal-node switching signals and propagation delays in digital circuits with picosecond time resolution, small-signal and large-signal analysis of microwave circuits, and measurement of the one-port S-parameters on IC transmission lines to millimeter-wave frequencies. A method to measure two-port S-parameters using the optical probe is described. This technique defines an on-chip reference plane, reducing measurement errors and eliminating the calibration standards and routines required with conventional network analyzers.
{"title":"GaAs Integrated Circuit Testing Using Electrooptic Sampling","authors":"K. Weingarten, M. Rodwell, D. Bloom","doi":"10.1109/CORNEL.1987.721211","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721211","url":null,"abstract":"The principles of electrooptic sampling for high-speed testing of GaAs IC, its capabilities as both a time-domain sampling oscilloscope and a frequency-domain network analyzer, and recent measurements results are described. Applications of this system include measurements of internal-node switching signals and propagation delays in digital circuits with picosecond time resolution, small-signal and large-signal analysis of microwave circuits, and measurement of the one-port S-parameters on IC transmission lines to millimeter-wave frequencies. A method to measure two-port S-parameters using the optical probe is described. This technique defines an on-chip reference plane, reducing measurement errors and eliminating the calibration standards and routines required with conventional network analyzers.","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129426761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721240
M. Svilans, D. Day
The integration of photonic devices (diode lasers, photodiodes) with electronic gain elements (transistors) is particularly interesting on InP. The band-gap of InGaAsP in this system is compatible with the commonly used 1300nm and 1550nm optical transmission wavelengths, a semi-insulating substrate is available for inter-device electrical isolation and multi-layer processing is easily controlled with accessible materialselective wet chemical etchants.
{"title":"High Gain At Low Power in InGaAsP Double-Heterostructure Bipolar Transistors","authors":"M. Svilans, D. Day","doi":"10.1109/CORNEL.1987.721240","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721240","url":null,"abstract":"The integration of photonic devices (diode lasers, photodiodes) with electronic gain elements (transistors) is particularly interesting on InP. The band-gap of InGaAsP in this system is compatible with the commonly used 1300nm and 1550nm optical transmission wavelengths, a semi-insulating substrate is available for inter-device electrical isolation and multi-layer processing is easily controlled with accessible materialselective wet chemical etchants.","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131500066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721219
S. Bedair
{"title":"Atomic Layer Epitaxy","authors":"S. Bedair","doi":"10.1109/CORNEL.1987.721219","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721219","url":null,"abstract":"","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122093800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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