Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990935
C. Urano, T. Irimatsugawa, Takahiro Yamada
We have been developing a Johnson noise thermometer using an integrated quantum voltage noise source (IQVNS) as a reference signal source. IQVNS is a superconducting integrated circuit that generates pseudo random signals. The power spectral density of output signal of IQVNS can be described with quantum accuracy by fundamental physical constants $e$ and h, the clock frequency of the circuit, and a numerical coefficient. In the previous version of IQVNS the numerical coefficient was fixed by the circuit design. However, to cope with the measurement of thermodynamic temperature in a wide temperature range, it is desirable to make the output of IQVNS variable. In this study, we improved part of the design of the device to be able to change the power spectral density of the output signal and confirmed by measurement that the output signal can be variable as designed.
{"title":"Development of Programmable Integrated Quantum Voltage Noise Source","authors":"C. Urano, T. Irimatsugawa, Takahiro Yamada","doi":"10.1109/ISEC46533.2019.8990935","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990935","url":null,"abstract":"We have been developing a Johnson noise thermometer using an integrated quantum voltage noise source (IQVNS) as a reference signal source. IQVNS is a superconducting integrated circuit that generates pseudo random signals. The power spectral density of output signal of IQVNS can be described with quantum accuracy by fundamental physical constants $e$ and h, the clock frequency of the circuit, and a numerical coefficient. In the previous version of IQVNS the numerical coefficient was fixed by the circuit design. However, to cope with the measurement of thermodynamic temperature in a wide temperature range, it is desirable to make the output of IQVNS variable. In this study, we improved part of the design of the device to be able to change the power spectral density of the output signal and confirmed by measurement that the output signal can be variable as designed.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127531069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990927
H. F. Herbst, P. Le Roux, Kyle Jackman, C. Fourie
The FLOOXS technology CAD (TCAD) process modeling tools developed at the University of Florida have been adapted under the IARPA SuperTools program to support the MIT Lincoln Laboratory SFQ5ee fabrication process. We use FLOOXS to build meshed models of passive transmission lines from superconductor integrated circuit layouts. We have previously developed a numerical solver that extracts transmission line parameters from the meshed model. In this work, we convert a layout slice to FLOOXS inputs, generate 2D meshes of cross-sectional geometries from simulated process steps, and then extract the transmission line parameters from the meshes. Results are shown compared against the results for simplified transmission lines that do not utilize process modeling. We conclude with a discussion on the application of TCAD process modeling for parameter extraction of structures in superconductor integrated circuits beyond the device level and make a recommendation on the necessity of process modeling for high-quality parameter extraction.
{"title":"Improved Transmission Line Parameter Calculation through TCAD Process Modeling for Superconductor Integrated Circuit Interconnects","authors":"H. F. Herbst, P. Le Roux, Kyle Jackman, C. Fourie","doi":"10.1109/ISEC46533.2019.8990927","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990927","url":null,"abstract":"The FLOOXS technology CAD (TCAD) process modeling tools developed at the University of Florida have been adapted under the IARPA SuperTools program to support the MIT Lincoln Laboratory SFQ5ee fabrication process. We use FLOOXS to build meshed models of passive transmission lines from superconductor integrated circuit layouts. We have previously developed a numerical solver that extracts transmission line parameters from the meshed model. In this work, we convert a layout slice to FLOOXS inputs, generate 2D meshes of cross-sectional geometries from simulated process steps, and then extract the transmission line parameters from the meshes. Results are shown compared against the results for simplified transmission lines that do not utilize process modeling. We conclude with a discussion on the application of TCAD process modeling for parameter extraction of structures in superconductor integrated circuits beyond the device level and make a recommendation on the necessity of process modeling for high-quality parameter extraction.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130455084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990907
N. Pokhrel, T. Weingartner, Robert J. Burwell, E. Patrick, M. Law
Josephson junction devices enable computation of binary data by switching between superconductive and resistive states. The switching is triggered by a current flowing through the junction below or above the critical limit $(I_{c})$, which is sensitive to the physical features of the junction. Modeling the variation in the physical properties of these tunnel junctions due to processing conditions is crucial to understanding the variation in $I_{c}$ across the chip and simulating the electrical characteristics of the device. The aim of this research is to model the steps involved in the fabrication of Nb/Al-O/Nb Josephson Junction for large scale integrated superconductive circuits, which consists of mainly: (i) sputter deposition of Al on top of the Nb base electrode (ii) oxidation of the Al layer to form Al-O tunnel barrier (~1nm] and (iii) anodization of the junction. Developing a process TCAD tool by implementing the fabrication steps from the base layer will ultimately complement device simulation and offer useful insights for optimization.
约瑟夫森结器件通过在超导和电阻状态之间切换来实现二进制数据的计算。开关是由流过结的电流低于或高于临界极限$(I_{c})$触发的，这对结的物理特性很敏感。模拟这些隧道结的物理性质随加工条件的变化，对于理解芯片上$I_{c}$的变化和模拟器件的电气特性至关重要。本研究的目的是模拟用于大规模集成超导电路的Nb/Al- o /Nb约瑟夫森结的制造步骤，主要包括:(i)在Nb基电极上溅射沉积Al (ii)氧化Al层形成Al- o隧道势垒(~1nm)和(iii)阳极氧化结。通过从基础层实现制造步骤来开发过程TCAD工具将最终补充器件仿真并为优化提供有用的见解。
{"title":"Simulating the Fabrication of Nb/Al-O/Nb Josephson Junction for Superconductive Electronics Application","authors":"N. Pokhrel, T. Weingartner, Robert J. Burwell, E. Patrick, M. Law","doi":"10.1109/ISEC46533.2019.8990907","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990907","url":null,"abstract":"Josephson junction devices enable computation of binary data by switching between superconductive and resistive states. The switching is triggered by a current flowing through the junction below or above the critical limit $(I_{c})$, which is sensitive to the physical features of the junction. Modeling the variation in the physical properties of these tunnel junctions due to processing conditions is crucial to understanding the variation in $I_{c}$ across the chip and simulating the electrical characteristics of the device. The aim of this research is to model the steps involved in the fabrication of Nb/Al-O/Nb Josephson Junction for large scale integrated superconductive circuits, which consists of mainly: (i) sputter deposition of Al on top of the Nb base electrode (ii) oxidation of the Al layer to form Al-O tunnel barrier (~1nm] and (iii) anodization of the junction. Developing a process TCAD tool by implementing the fabrication steps from the base layer will ultimately complement device simulation and offer useful insights for optimization.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130898360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990942
A. Weis, N. Flowers-Jacobs, E. Cho, H. Li, J. LeFebvre, S. Cybart, S. Berkowitz, H. Rogalla, S. Benz
Josephson junction arrays are the basis for quantum-accurate dc and ac voltage standards, including artificial voltage-noise references used in noise thermometry. I will describe our recent progress towards voltage synthesis using high-transition-temperature YBCO junctions.
{"title":"Pulse-Driven High- TC Josephson Junctions for Quantum Voltage Devices","authors":"A. Weis, N. Flowers-Jacobs, E. Cho, H. Li, J. LeFebvre, S. Cybart, S. Berkowitz, H. Rogalla, S. Benz","doi":"10.1109/ISEC46533.2019.8990942","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990942","url":null,"abstract":"Josephson junction arrays are the basis for quantum-accurate dc and ac voltage standards, including artificial voltage-noise references used in noise thermometry. I will describe our recent progress towards voltage synthesis using high-transition-temperature YBCO junctions.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133271207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990964
Haolin Cong, N. Katam, M. Pedram
This paper presents the design of a one-bit full adder with sum and carry outputs as two single-stage gates, which could save the JJ count and the area compared with the conventional design of a full-adder. The schematics of both the Sum and Carry cells are shown in this paper along with their input and output waveforms of JSIM simulations in the time domain. The circuit cost is compared between the conventional full adder and the new single-stage adder design in terms of the area and the time. Integer dividers of several sizes are synthesized with conventional full-adder and the proposed single-stage adder to illustrate the advantages of the new design.
{"title":"Design of an SFQ Full Adder as a Single-Stage Gate","authors":"Haolin Cong, N. Katam, M. Pedram","doi":"10.1109/ISEC46533.2019.8990964","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990964","url":null,"abstract":"This paper presents the design of a one-bit full adder with sum and carry outputs as two single-stage gates, which could save the JJ count and the area compared with the conventional design of a full-adder. The schematics of both the Sum and Carry cells are shown in this paper along with their input and output waveforms of JSIM simulations in the time domain. The circuit cost is compared between the conventional full adder and the new single-stage adder design in terms of the area and the time. Integer dividers of several sizes are synthesized with conventional full-adder and the proposed single-stage adder to illustrate the advantages of the new design.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122154007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990924
Ji Wang, E. Cho, Hao Li, J. LeFebvre, Kevin Pratt, S. Cybart
In this work we present a miniature solid nitrogen cooling system designed for 45 K operation of $(mathrm{high}-T_{mathrm{C}})$ superconductor Josephson devices. The system utilizes a small 100mL fiberglass Dewar and external pump to solidify nitrogen in thermal contact with a circuit board insert. Cooling tests reveal that the system holds at its base temperature of 45 K for over 12 hours. This can provide a low power, low weight system for ultra-portable superconductive electronics and other cryogenic sensors.
{"title":"Portable Solid Nitrogen Cooling System for High Transition Temperature Superconductive Electronics","authors":"Ji Wang, E. Cho, Hao Li, J. LeFebvre, Kevin Pratt, S. Cybart","doi":"10.1109/ISEC46533.2019.8990924","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990924","url":null,"abstract":"In this work we present a miniature solid nitrogen cooling system designed for 45 K operation of $(mathrm{high}-T_{mathrm{C}})$ superconductor Josephson devices. The system utilizes a small 100mL fiberglass Dewar and external pump to solidify nitrogen in thermal contact with a circuit board insert. Cooling tests reveal that the system holds at its base temperature of 45 K for over 12 hours. This can provide a low power, low weight system for ultra-portable superconductive electronics and other cryogenic sensors.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131812813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990959
Jia-Hong Yang, Guangming Tang, Pei-Yao Qu, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun
An 8-bit bit-parallel RSFQ microprocessor, named HUTU, is proposed. It can execute 28 different instructions. Each instruction consists of eight bits. Harvard-type architecture is adopted for parallel processing between the control unit and the datapath. The control unit uses an asynchronous timing method to avoid pipeline flushing and to reduce the area. Concurrent-flow clocking is adopted in the datapath for high performance. The simulation result shows that the elements of HUTU run correctly.
{"title":"Logic Design of an 8-bit RSFQ Microprocessor","authors":"Jia-Hong Yang, Guangming Tang, Pei-Yao Qu, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun","doi":"10.1109/ISEC46533.2019.8990959","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990959","url":null,"abstract":"An 8-bit bit-parallel RSFQ microprocessor, named HUTU, is proposed. It can execute 28 different instructions. Each instruction consists of eight bits. Harvard-type architecture is adopted for parallel processing between the control unit and the datapath. The control unit uses an asynchronous timing method to avoid pipeline flushing and to reduce the area. Concurrent-flow clocking is adopted in the datapath for high performance. The simulation result shows that the elements of HUTU run correctly.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"5 17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124529882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990954
Bo Zhang, Fangzhou Wang, S. Gupta, M. Pedram
As a beyond-CMOS technology, superconducting single-flux-quantum (SFQ) technology promises fast processing speed and excellent energy efficiency. With the increasing complexity of SFQ circuits, the accurate and fast estimation of the workable clock period under process variation becomes more urgent. However, the estimation of the minimum workable clock period is difficult due to the spatial correlation of physical parameters and the non-normal distribution of timing parameters (propagation delay, setup time, and hold time). Therefore, a good statistical timing analysis (SSTA) tool for SFQ circuits is necessary. This paper presents a bootstrap-based statistical static timing analysis tool called qSSTA. qSSTA can reasonably estimate a minimum workable clock period by executing a large amount of bootstrap iterations from the discrete sampling spaces of all gates under a certain correlation specification. By applying path pruning methods, qSSTA skips the calculations on unimportant paths and hence reduce run time and memory. Experimental results show that the size of important paths could be small. Among 19114 paths of the 16-bit integer divider, only 73 paths are important to estimate minimum workable clock period. We only need 84.21 seconds to run 10,000 iterations.
{"title":"A Statistical Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits","authors":"Bo Zhang, Fangzhou Wang, S. Gupta, M. Pedram","doi":"10.1109/ISEC46533.2019.8990954","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990954","url":null,"abstract":"As a beyond-CMOS technology, superconducting single-flux-quantum (SFQ) technology promises fast processing speed and excellent energy efficiency. With the increasing complexity of SFQ circuits, the accurate and fast estimation of the workable clock period under process variation becomes more urgent. However, the estimation of the minimum workable clock period is difficult due to the spatial correlation of physical parameters and the non-normal distribution of timing parameters (propagation delay, setup time, and hold time). Therefore, a good statistical timing analysis (SSTA) tool for SFQ circuits is necessary. This paper presents a bootstrap-based statistical static timing analysis tool called qSSTA. qSSTA can reasonably estimate a minimum workable clock period by executing a large amount of bootstrap iterations from the discrete sampling spaces of all gates under a certain correlation specification. By applying path pruning methods, qSSTA skips the calculations on unimportant paths and hence reduce run time and memory. Experimental results show that the size of important paths could be small. Among 19114 paths of the 16-bit integer divider, only 73 paths are important to estimate minimum workable clock period. We only need 84.21 seconds to run 10,000 iterations.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121764570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-25DOI: 10.1109/ISEC46533.2019.8990934
E. Cho, Hao Li, S. Cybart
We highlight the reproducibility and level of control over the electrical properties of YBa2Cu3O7 Josephson junctions fabricated with irradiation from a focused helium ion beam. Specifically we show the results of electrical transport properties for several junctions fabricated using a large range of irradiation doses. At the lower end of this range, junctions exhibit superconductor-normal metal-superconductor (SNS) Josephson junction properties. However, as dose increases there is a transition to electrical characteristics consistent with superconductor-insulator-superconductor (SIS) junctions. To investigate the uniformity of large numbers of helium ion Josephson junctions we fabricate arrays of both SNS and SIS Josephson junctions containing 20 connected in series. Electrical transport properties for these arrays reveal very uniform junctions with no appreciable spread in critical current or resistance.
{"title":"Direct-Write Ion Beam Irradiated Josephson Junctions","authors":"E. Cho, Hao Li, S. Cybart","doi":"10.1109/ISEC46533.2019.8990934","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990934","url":null,"abstract":"We highlight the reproducibility and level of control over the electrical properties of YBa2Cu3O7 Josephson junctions fabricated with irradiation from a focused helium ion beam. Specifically we show the results of electrical transport properties for several junctions fabricated using a large range of irradiation doses. At the lower end of this range, junctions exhibit superconductor-normal metal-superconductor (SNS) Josephson junction properties. However, as dose increases there is a transition to electrical characteristics consistent with superconductor-insulator-superconductor (SIS) junctions. To investigate the uniformity of large numbers of helium ion Josephson junctions we fabricate arrays of both SNS and SIS Josephson junctions containing 20 connected in series. Electrical transport properties for these arrays reveal very uniform junctions with no appreciable spread in critical current or resistance.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129380267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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