Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990958
T. Filippov, A. Sahu, M. E. Çelik, D. Kirichenko, D. Gupta
The Josephson balanced comparator is the key component of Single Flux Quantum logic devices because it is the decision making element. It is formed by two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured. Its noise properties are crucial for the performance of logic devices. The balanced comparator can also be used to monitor the fab process and design implementation as an indicator of excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure the comparator gray zone at different fabrication process nodes at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies. An analog testbed was used to perform high-frequency characterization. Experimental results for different current densities, sheet resistances, damping and clock frequencies are presented.
{"title":"The Josephson Balanced Comparator and its Gray Zone Measurements","authors":"T. Filippov, A. Sahu, M. E. Çelik, D. Kirichenko, D. Gupta","doi":"10.1109/ISEC46533.2019.8990958","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990958","url":null,"abstract":"The Josephson balanced comparator is the key component of Single Flux Quantum logic devices because it is the decision making element. It is formed by two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured. Its noise properties are crucial for the performance of logic devices. The balanced comparator can also be used to monitor the fab process and design implementation as an indicator of excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure the comparator gray zone at different fabrication process nodes at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies. An analog testbed was used to perform high-frequency characterization. Experimental results for different current densities, sheet resistances, damping and clock frequencies are presented.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131110313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990903
Takashi Dejima, K. Takagi, N. Takagi
We propose placement and routing methods integrated in automated layout design flow for rapid single-flux-quantum (RSFQ) circuits. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering proper use of JTLs and PTLs. The placement problem is divided into subproblems in order to reduce the computational cost. The placement method is composed of three steps, i.e., (i) Cell clustering, (ii) Cell placement and JTL routing in each cluster, and (iii) Cluster placement. Routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed with the proposed methods are smaller than those of the circuits designed manually.
{"title":"Placement and Routing Methods Based on Mixed Wiring of JTLs and PTLs for RSFQ circuits","authors":"Takashi Dejima, K. Takagi, N. Takagi","doi":"10.1109/ISEC46533.2019.8990903","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990903","url":null,"abstract":"We propose placement and routing methods integrated in automated layout design flow for rapid single-flux-quantum (RSFQ) circuits. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering proper use of JTLs and PTLs. The placement problem is divided into subproblems in order to reduce the computational cost. The placement method is composed of three steps, i.e., (i) Cell clustering, (ii) Cell placement and JTL routing in each cluster, and (iii) Cluster placement. Routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed with the proposed methods are smaller than those of the circuits designed manually.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122707609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990923
M. E. Çelik, T. Filippov, A. Sahu, D. Kirichenko, S. Sarwana, A. E. Lehmann, D. Gupta
Historically one of the most challenging high-speed RSFQ circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums 7 inputs has been designed and tested at clock frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output was designed using two flavors of 8-to-4 summing circuits. The first (8-to-4a), based on the 7-to-3 parallel counter, sums 8 unweighted inputs whereas the second (8-to-4b) sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights from two 8-to-4a blocks. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.
历史上最具挑战性的高速RSFQ电路之一是一个并行计数器，它对一组未加权输入求和，并以相同的时钟速率产生二进制加权单词。设计了一个7对3并行计数器，该计数器将7个输入加起来，并使用自己的专用测试平台在时钟频率高达50 GHz的情况下进行测试。使用麻省理工学院林肯实验室的铸造厂，以10和20 ka /cm2的电流密度生产，这种7比3的求和电路已成为数字电路的基准。最近，一个具有15个并行输入产生4位输出的版本使用两种8对4求和电路设计。第一个(8-to-4a)基于7-to-3并行计数器，对8个未加权输入求和，而第二个(8-to-4b)通过对两个8-to-4a块中权重相等的位进行成对求和，对两个4位二进制加权单词求和。我们将在讨论电路性能和良率的同时，讨论该电路的设计考虑因素。
{"title":"Fast RSFQ and ERSFQ Parallel Counters","authors":"M. E. Çelik, T. Filippov, A. Sahu, D. Kirichenko, S. Sarwana, A. E. Lehmann, D. Gupta","doi":"10.1109/ISEC46533.2019.8990923","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990923","url":null,"abstract":"Historically one of the most challenging high-speed RSFQ circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums 7 inputs has been designed and tested at clock frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output was designed using two flavors of 8-to-4 summing circuits. The first (8-to-4a), based on the 7-to-3 parallel counter, sums 8 unweighted inputs whereas the second (8-to-4b) sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights from two 8-to-4a blocks. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121891115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990950
Bernard H. Venter, C. Fourie
Localized heating has the potential to create undesired effects in the operation of the superconducting circuits, such as thermal noise and its influence on the SFQ pulse. Left unchecked, it could form into heat zones that could destroy the superconductivity in the circuit. Heat zones only become apparent during the testing phase after manufacture. This process wastes time and materials on a problem that could have been prevented. It is, therefore, crucial to provide a method to simulate the heat propagation before manufacture. We investigate a method to simulate the heat generated by a superconducting circuit during the design process. It will help circuit designers see potential failures beforehand caused by trapped heat zones. The algorithm takes in an object generated by FEniCS as an input and a basis for the heat conduction calculation. The heat conduction is calculated by making use of the electron conduction and lattice vibrations of the material under investigation.
{"title":"Initial Numerical Simulation of the Thermodynamic Behaviour of a Superconducting Circuit","authors":"Bernard H. Venter, C. Fourie","doi":"10.1109/ISEC46533.2019.8990950","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990950","url":null,"abstract":"Localized heating has the potential to create undesired effects in the operation of the superconducting circuits, such as thermal noise and its influence on the SFQ pulse. Left unchecked, it could form into heat zones that could destroy the superconductivity in the circuit. Heat zones only become apparent during the testing phase after manufacture. This process wastes time and materials on a problem that could have been prevented. It is, therefore, crucial to provide a method to simulate the heat propagation before manufacture. We investigate a method to simulate the heat generated by a superconducting circuit during the design process. It will help circuit designers see potential failures beforehand caused by trapped heat zones. The algorithm takes in an object generated by FEniCS as an input and a basis for the heat conduction calculation. The heat conduction is calculated by making use of the electron conduction and lattice vibrations of the material under investigation.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126904186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990936
Gaowei Xu, W. Gai, L. Luo, Jie Ren
In this paper, we reported a laser melting/jetting bumping technology for flip-chip interconnection, which will provide a flexible interconnection solution for high-speed superconducting MCM (Multi-chip modules). We adopted In-Sn eutectic alloy (with low-melt-point about 117°C) to fabricate flip-chip bump array of SCE-MCM. The effects of the key process parameters (such as laser energy, nitrogen pressure etc.) on interconnection strength were also discussed.
{"title":"In-Sn Bumping Design and Fabrication for High Speed Interconnects of Superconducting MCM via Laser Melting/Jetting and Distribution","authors":"Gaowei Xu, W. Gai, L. Luo, Jie Ren","doi":"10.1109/ISEC46533.2019.8990936","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990936","url":null,"abstract":"In this paper, we reported a laser melting/jetting bumping technology for flip-chip interconnection, which will provide a flexible interconnection solution for high-speed superconducting MCM (Multi-chip modules). We adopted In-Sn eutectic alloy (with low-melt-point about 117°C) to fabricate flip-chip bump array of SCE-MCM. The effects of the key process parameters (such as laser energy, nitrogen pressure etc.) on interconnection strength were also discussed.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122353063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990899
I. Nevirkovets, T. Kojima, Y. Uzawa, O. Mukhanov
We report on the measurement results of the superconducting-ferromagnetic transistors (SFTs) made at Northwestern University and Hypres, Inc. [IEEE Trans. Appl. Supercond. vol. 24, 1800506 (2014); vol. 25, 1800705 (2015)]. SFT is a multi-terminal device with the SIS'FIFS structure (where S, I, and F denote a superconductor, an insulator, and a ferromagnetic material, respectively) exploiting intense quasiparticle injection in order to modify the non-linear I-V curve of a superconducting tunnel junction. Potentially, SFT is capable of providing voltage, current and power amplification while having good input/output isolation. We characterized the devices at frequencies up to 5 MHz at 4 K. Our setup did not allow for accurate measurement of the voltage gain of low-impedance SFT devices because of contribution of resistance of the bias-T connected in series with the SFT. Nevertheless we observed a voltage gain above unity for some measurement configurations. It is very interesting that we confirmed that the isolation between the input and output of the device is quite good. We suggest that further improvement of the SFT device parameters is possible in optimized devices, so that the device potentially may serve as a preamplifier for readout of output signals of cryogenic detectors and be useful as an element of other superconductor-based circuits.
{"title":"Measurement Results of the Superconducting-Ferromagnetic Transistor","authors":"I. Nevirkovets, T. Kojima, Y. Uzawa, O. Mukhanov","doi":"10.1109/ISEC46533.2019.8990899","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990899","url":null,"abstract":"We report on the measurement results of the superconducting-ferromagnetic transistors (SFTs) made at Northwestern University and Hypres, Inc. [IEEE Trans. Appl. Supercond. vol. 24, 1800506 (2014); vol. 25, 1800705 (2015)]. SFT is a multi-terminal device with the SIS'FIFS structure (where S, I, and F denote a superconductor, an insulator, and a ferromagnetic material, respectively) exploiting intense quasiparticle injection in order to modify the non-linear I-V curve of a superconducting tunnel junction. Potentially, SFT is capable of providing voltage, current and power amplification while having good input/output isolation. We characterized the devices at frequencies up to 5 MHz at 4 K. Our setup did not allow for accurate measurement of the voltage gain of low-impedance SFT devices because of contribution of resistance of the bias-T connected in series with the SFT. Nevertheless we observed a voltage gain above unity for some measurement configurations. It is very interesting that we confirmed that the isolation between the input and output of the device is quite good. We suggest that further improvement of the SFT device parameters is possible in optimized devices, so that the device potentially may serve as a preamplifier for readout of output signals of cryogenic detectors and be useful as an element of other superconductor-based circuits.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129297692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990946
Aaron C. Lee, A. Przybysz, A. Marakov, J. Medford, A. Pesetski, J. Przybysz
A new technique was developed to measure noise and interference in a test stand for Josephson digital circuits. A spectrum analyzer measured the digital output of an RQL 10-bit shift register and found amplitude modulation sidebands due to bit errors generated by noise currents in the logic gate bias. The data pattern used was a simple 1010 … which produced a data tone at one half of the clock frequency. When the circuit was biased at the threshold between correct and incorrect operation, small noise tones modulated the bit error rate and were converted to AM sidebands of the data tone. Calibration tones were injected to measure the conversion ratio of sideband amplitude to interference amplitude, and showed a linear response over 4 decades of input tone power. The instrumentation noise floor was low enough to sense 20 nA of noise current on chip. The observation of AM sidebands was used to optimize filtering and identify defective cabling to eliminate noise and interference in the cryo-cooled test stand.
{"title":"Using Spectral Analysis of Output Data to Identify and Eliminate Noise on Control Lines","authors":"Aaron C. Lee, A. Przybysz, A. Marakov, J. Medford, A. Pesetski, J. Przybysz","doi":"10.1109/ISEC46533.2019.8990946","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990946","url":null,"abstract":"A new technique was developed to measure noise and interference in a test stand for Josephson digital circuits. A spectrum analyzer measured the digital output of an RQL 10-bit shift register and found amplitude modulation sidebands due to bit errors generated by noise currents in the logic gate bias. The data pattern used was a simple 1010 … which produced a data tone at one half of the clock frequency. When the circuit was biased at the threshold between correct and incorrect operation, small noise tones modulated the bit error rate and were converted to AM sidebands of the data tone. Calibration tones were injected to measure the conversion ratio of sideband amplitude to interference amplitude, and showed a linear response over 4 decades of input tone power. The instrumentation noise floor was low enough to sense 20 nA of noise current on chip. The observation of AM sidebands was used to optimize filtering and identify defective cabling to eliminate noise and interference in the cryo-cooled test stand.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127560127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990949
R. Su, J. Chen, P. Wu, Y. Zhang, X. Tu, X. Jia, C. H. Zhang, L. Kang, B. Jin, W. Xu, H. Wang
The properties of terahertz (THz) power detectors based on Superconducting NbN hot electron bolometer (HEB) with microwave (MW) readout are reported here. Features of relaxation oscillations probed with MW when the HEB is not pumped, pumped by THz source or heated by raising the bath temperature are studies. The periodic pulse in the reflected MW signals both in time and frequency domains show that the relaxation oscillation frequency increases with the bias voltage, incident THz power and/or bath temperature. The frequency count forms a quadratic polynomial fit to the bias voltage, a linear fit to the incident THz power and an exponential fit to the bath temperature. Based on the above results, incident THz power between 8–90 nW is measured using the HEB.
{"title":"Terahertz Power Detectors based on Superconducting HEBs with Microwave Readout","authors":"R. Su, J. Chen, P. Wu, Y. Zhang, X. Tu, X. Jia, C. H. Zhang, L. Kang, B. Jin, W. Xu, H. Wang","doi":"10.1109/ISEC46533.2019.8990949","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990949","url":null,"abstract":"The properties of terahertz (THz) power detectors based on Superconducting NbN hot electron bolometer (HEB) with microwave (MW) readout are reported here. Features of relaxation oscillations probed with MW when the HEB is not pumped, pumped by THz source or heated by raising the bath temperature are studies. The periodic pulse in the reflected MW signals both in time and frequency domains show that the relaxation oscillation frequency increases with the bias voltage, incident THz power and/or bath temperature. The frequency count forms a quadratic polynomial fit to the bias voltage, a linear fit to the incident THz power and an exponential fit to the bath temperature. Based on the above results, incident THz power between 8–90 nW is measured using the HEB.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"15 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120933307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990933
Han Cai, Hao Li, E. Cho, J. LeFebvre, Yan-Ting Wang, S. Cybart
The performance of Josephson based devices strongly depend on the inductance properties associated with the material and circuit design. Here we compare the inductance of $mathbf{YBa}_{2}mathbf{Cu}_{3}mathbf{O}_{7-delta}$ films with and without superconducting ground planes grown by reactive coevaporation. Specifically, we fabricated several superconducting quantum interference devices from single and multi-layer films with different geometries using a focused helium ion beam. Measurements of device electrical transport properties were analyzed to experimentally determine the sheet inductance. Additionally, measurements of the temperature dependence of the inductance was used to separate the contributions from geometric and kinetic inductance. We find that the presence of the ground plane in the multi-layer structure reduces the contribution of geometric inductance with no detectable change in the kinetic inductance.
{"title":"Inductance investigation of single layer and multilayer YBa2Cu3O7-δ thin films grown by reactive coevaporation","authors":"Han Cai, Hao Li, E. Cho, J. LeFebvre, Yan-Ting Wang, S. Cybart","doi":"10.1109/ISEC46533.2019.8990933","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990933","url":null,"abstract":"The performance of Josephson based devices strongly depend on the inductance properties associated with the material and circuit design. Here we compare the inductance of $mathbf{YBa}_{2}mathbf{Cu}_{3}mathbf{O}_{7-delta}$ films with and without superconducting ground planes grown by reactive coevaporation. Specifically, we fabricated several superconducting quantum interference devices from single and multi-layer films with different geometries using a focused helium ion beam. Measurements of device electrical transport properties were analyzed to experimentally determine the sheet inductance. Additionally, measurements of the temperature dependence of the inductance was used to separate the contributions from geometric and kinetic inductance. We find that the presence of the ground plane in the multi-layer structure reduces the contribution of geometric inductance with no detectable change in the kinetic inductance.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131824858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990929
Junliang Jiang, Yongchao Li, J. Pan, Hua-bing Wang, G. Sun, Peiheng Wu
Mechanical oscillators can be implemented to store and/or transfer information. In order to couple a mechanical oscillator to a superconducting qubit, we fabricate a superconducting capacitor using the diluted photoresist or electron beam photoresist as a sacrificial layer. The upper plate of the capacitor, a suspended membrane, acts as a mechanical oscillator. We obtain its mechanical resonant frequency and response to the input microwave. Such mechanical oscillator can be used as the capacitor of a superconducting qubit to form a coupled system. Another way to transfer information between a mechanical oscillator and a superconducting qubit is to take advantage of a superconducting microwave resonator such as a coplanar waveguide resonator. In order to control the resonant frequency of the resonators, we introduce a DC voltage bias between the upper and lower plates of the capacitor. We demonstrate the dependence of the resonant frequency on the applied DC voltage.
{"title":"Mechanical Oscillators Based on Superconducting Membranes","authors":"Junliang Jiang, Yongchao Li, J. Pan, Hua-bing Wang, G. Sun, Peiheng Wu","doi":"10.1109/ISEC46533.2019.8990929","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990929","url":null,"abstract":"Mechanical oscillators can be implemented to store and/or transfer information. In order to couple a mechanical oscillator to a superconducting qubit, we fabricate a superconducting capacitor using the diluted photoresist or electron beam photoresist as a sacrificial layer. The upper plate of the capacitor, a suspended membrane, acts as a mechanical oscillator. We obtain its mechanical resonant frequency and response to the input microwave. Such mechanical oscillator can be used as the capacitor of a superconducting qubit to form a coupled system. Another way to transfer information between a mechanical oscillator and a superconducting qubit is to take advantage of a superconducting microwave resonator such as a coplanar waveguide resonator. In order to control the resonant frequency of the resonators, we introduce a DC voltage bias between the upper and lower plates of the capacitor. We demonstrate the dependence of the resonant frequency on the applied DC voltage.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129334462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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