Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990941
N. Katam, Haolin Cong, M. Pedram
Field Programmable gate arrays (FPGAs) are one of the most successful circuits in the semiconductor industry. In the absence of a reliable three-terminal switch like MOSFET for rapid single flux quantum(RSFQ) technology, it was difficult to implement FPGA like reconfiguralbe circuits. However, a recently proposed superconducting magnetic FPGA (SMFPGA) implements a controllable switch by controlling the critical current of magnetic Josephson Junctions (MJJs) placed in energy-efficient RSFQ bias network. For implementing a configurable logic block (CLB) with a smaller area for the said FPGA, we designed a reconfigurable gate that can implement four basic logical functions: AND, OR, XOR and NOT. The programmability to implement the four functions is achieved by introducing MJJs in the circuit at specific locations and programming their critical current. The gate is made reconfigurable by having the ability to change both the bias current at different ports and the critical current of a JJ in the gate to two different values. This makes the size of CLB ten times smaller compared to the earlier design and simplifies the SMFPGA. We describe the design methodology and the simulation results of the reconfigurable gate.
{"title":"Reconfigurable Logic Cell for Superconducting Magnetic Field Programmable Gate Array","authors":"N. Katam, Haolin Cong, M. Pedram","doi":"10.1109/ISEC46533.2019.8990941","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990941","url":null,"abstract":"Field Programmable gate arrays (FPGAs) are one of the most successful circuits in the semiconductor industry. In the absence of a reliable three-terminal switch like MOSFET for rapid single flux quantum(RSFQ) technology, it was difficult to implement FPGA like reconfiguralbe circuits. However, a recently proposed superconducting magnetic FPGA (SMFPGA) implements a controllable switch by controlling the critical current of magnetic Josephson Junctions (MJJs) placed in energy-efficient RSFQ bias network. For implementing a configurable logic block (CLB) with a smaller area for the said FPGA, we designed a reconfigurable gate that can implement four basic logical functions: AND, OR, XOR and NOT. The programmability to implement the four functions is achieved by introducing MJJs in the circuit at specific locations and programming their critical current. The gate is made reconfigurable by having the ability to change both the bias current at different ports and the critical current of a JJ in the gate to two different values. This makes the size of CLB ten times smaller compared to the earlier design and simplifies the SMFPGA. We describe the design methodology and the simulation results of the reconfigurable gate.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126868483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990938
J. LeFebvre, E. Cho, Kevin Pratt, S. Cybart
We investigated series arrays of closely spaced, planar long Josephson junctions for magnetic flux transduction with a linear response and high dynamic range. The devices were fabricated from 30-nm thick high-temperature superconducting YBa2Cu3O7-δ(YBCO) thin films, using focused helium ion beam irradiation to create the Josephson barriers. Series arrays consisting of 600 long junctions, were fabricated and electrically tested. From fits of the current-voltage characteristics we estimate the standard deviation in critical current to be around 25%. Voltage-magnetic field measurements exhibit a sharp transfer function with a modulation depth of 11 mV over a range of 135μ $T$ at 71 K.
{"title":"Series Arrays of Long Josephson Junctions Fabricated with a Focused Helium Ion Beam in YBa2Cu3O7-δ","authors":"J. LeFebvre, E. Cho, Kevin Pratt, S. Cybart","doi":"10.1109/ISEC46533.2019.8990938","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990938","url":null,"abstract":"We investigated series arrays of closely spaced, planar long Josephson junctions for magnetic flux transduction with a linear response and high dynamic range. The devices were fabricated from 30-nm thick high-temperature superconducting YBa2Cu3O7-δ(YBCO) thin films, using focused helium ion beam irradiation to create the Josephson barriers. Series arrays consisting of 600 long junctions, were fabricated and electrically tested. From fits of the current-voltage characteristics we estimate the standard deviation in critical current to be around 25%. Voltage-magnetic field measurements exhibit a sharp transfer function with a modulation depth of 11 mV over a range of 135μ $T$ at 71 K.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116071512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990966
D. Richter, A. Fleischmann, C. Enss, S. Kempf
We present a novel dc-SQUID readout scheme that provides linearization of the relation between the input and output signal without using a conventional flux-locked loop circuit. It relies on applying a periodic, sawtooth-shaped magnetic flux signal to the modulation coil of the SQUID to continuously measure the flux-to-voltage SQUID characteristic within each period of the flux ramp. In case that the amplitude and repetition rate of the ramp are chosen such that multiple flux quanta are induced in the SQUID and that the input signal is quasistatic within one period of the flux ramp, the input signal adds a constant magnetic flux offset to the SQUID that leads to a phase shift of the SQUID characteristic being proportional to the input signal. We show that this scheme allows for significantly increasing the dynamic range and that it intrinsically allows for MHz frequency-division SQUID multiplexing.
{"title":"Dc-SQUID Readout with High Dynamic Range and Intrinsic MHz Frequency-Division Multiplexing Capability","authors":"D. Richter, A. Fleischmann, C. Enss, S. Kempf","doi":"10.1109/ISEC46533.2019.8990966","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990966","url":null,"abstract":"We present a novel dc-SQUID readout scheme that provides linearization of the relation between the input and output signal without using a conventional flux-locked loop circuit. It relies on applying a periodic, sawtooth-shaped magnetic flux signal to the modulation coil of the SQUID to continuously measure the flux-to-voltage SQUID characteristic within each period of the flux ramp. In case that the amplitude and repetition rate of the ramp are chosen such that multiple flux quanta are induced in the SQUID and that the input signal is quasistatic within one period of the flux ramp, the input signal adds a constant magnetic flux offset to the SQUID that leads to a phase shift of the SQUID characteristic being proportional to the input signal. We show that this scheme allows for significantly increasing the dynamic range and that it intrinsically allows for MHz frequency-division SQUID multiplexing.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128050799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990900
M. Frank, Rupert M. Lewis, N. Missert, M. Henry, M. Wolak, E. Debenedictis
In an ongoing project at Sandia National Laboratories, we are attempting to develop a novel style of superconducting digital processing, based on a new model of reversible computation called Asynchronous Ballistic Reversible Computing (ABRC). We envision an approach in which polarized flux-ons scatter elastically from near-lossless functional components, reversibly updating the local digital state of the circuit, while dissipating only a small fraction of the input fluxon energy. This approach to superconducting digital computation is sufficiently unconventional that an appropriate methodology for hand-design of such circuits is not immediately obvious. To gain insight into the design principles that are applicable in this new domain, we are creating a software tool to automatically enumerate possible topologies of reactive, undamped Josephson junction circuits, and sweep the parameter space of each circuit searching for designs exhibiting desired dynamical behaviors. But first, we identified by hand a circuit implementing the simplest possible nontrivial ABRC functional behavior with bits encoded as conserved polarized fluxons, namely, a one-bit reversible memory cell with one bidirectional I/O port. We expect the tool to be useful for designing more complex circuits.
{"title":"Semi-Automated Design of Functional Elements for a New Approach to Digital Superconducting Electronics: Methodology and Preliminary Results","authors":"M. Frank, Rupert M. Lewis, N. Missert, M. Henry, M. Wolak, E. Debenedictis","doi":"10.1109/ISEC46533.2019.8990900","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990900","url":null,"abstract":"In an ongoing project at Sandia National Laboratories, we are attempting to develop a novel style of superconducting digital processing, based on a new model of reversible computation called Asynchronous Ballistic Reversible Computing (ABRC). We envision an approach in which polarized flux-ons scatter elastically from near-lossless functional components, reversibly updating the local digital state of the circuit, while dissipating only a small fraction of the input fluxon energy. This approach to superconducting digital computation is sufficiently unconventional that an appropriate methodology for hand-design of such circuits is not immediately obvious. To gain insight into the design principles that are applicable in this new domain, we are creating a software tool to automatically enumerate possible topologies of reactive, undamped Josephson junction circuits, and sweep the parameter space of each circuit searching for designs exhibiting desired dynamical behaviors. But first, we identified by hand a circuit implementing the simplest possible nontrivial ABRC functional behavior with bits encoded as conserved polarized fluxons, namely, a one-bit reversible memory cell with one bidirectional I/O port. We expect the tool to be useful for designing more complex circuits.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"450 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124287560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990953
S. Uchaikin, Y. Urade, S. Kono, M. Schmelz, R. Stolz, Yasunobu Nakamura, A. Matlashov, Doyu Lee, W. Chung, Seonjeong Oh, Y. Semertzidis, V. Zakosarenko, Ç. Kutlu, A. V. van Loo
We report results of our development of two types of microwave amplifiers based on Superconducting quantum interference devices (SQUIDs) for CAPP (Center for Axion and Precision Physics Research) axion search experiments. The first amplifier, Microstrip SQUID Amplifier (MSA) has a wide bandwidth. Power dissipation in resistive shunts results in a device overheating and limits the MSA performances. A thermal models of shunt cooling processes is developed and recommendations for a future design is provided. The second amplifier, Josephson Parametric Amplifier (JPA), at limited bandwidth showed a low noise near the standard quantum limit (SQL) of 196 mK. Implementation of a JPA in CULTASK (CAPP's Ultra-Low Temperature Axion Search in Korea) experiment is planned in the end of 2019.
{"title":"Development of SQUID Amplifiers for Axion Search Experiments","authors":"S. Uchaikin, Y. Urade, S. Kono, M. Schmelz, R. Stolz, Yasunobu Nakamura, A. Matlashov, Doyu Lee, W. Chung, Seonjeong Oh, Y. Semertzidis, V. Zakosarenko, Ç. Kutlu, A. V. van Loo","doi":"10.1109/ISEC46533.2019.8990953","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990953","url":null,"abstract":"We report results of our development of two types of microwave amplifiers based on Superconducting quantum interference devices (SQUIDs) for CAPP (Center for Axion and Precision Physics Research) axion search experiments. The first amplifier, Microstrip SQUID Amplifier (MSA) has a wide bandwidth. Power dissipation in resistive shunts results in a device overheating and limits the MSA performances. A thermal models of shunt cooling processes is developed and recommendations for a future design is provided. The second amplifier, Josephson Parametric Amplifier (JPA), at limited bandwidth showed a low noise near the standard quantum limit (SQL) of 196 mK. Implementation of a JPA in CULTASK (CAPP's Ultra-Low Temperature Axion Search in Korea) experiment is planned in the end of 2019.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134506728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990931
S. Whiteley, J. Kawa
Synopsys is developing a complete design flow tool set for use with superconductive digital logic, initially focusing on ERSFQ and AQFP technologies. This flow begins with design synthesis of a high level logic description, automating cell placement, routing, and design validation. Circuit simulation and statistical analysis tools utilizing advanced TCAD techniques are also under development. The flow will provide a tool set to address all requirements culminating with a tape-out. The proposed flow will parallel the functionality used routinely in the semiconductor industry, but is still at a very early stage of development for superconductors.
{"title":"Progress Toward VLSI-Capable EDA Tools for Superconductive Digital Electronics","authors":"S. Whiteley, J. Kawa","doi":"10.1109/ISEC46533.2019.8990931","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990931","url":null,"abstract":"Synopsys is developing a complete design flow tool set for use with superconductive digital logic, initially focusing on ERSFQ and AQFP technologies. This flow begins with design synthesis of a high level logic description, automating cell placement, routing, and design validation. Circuit simulation and statistical analysis tools utilizing advanced TCAD techniques are also under development. The flow will provide a tool set to address all requirements culminating with a tape-out. The proposed flow will parallel the functionality used routinely in the semiconductor industry, but is still at a very early stage of development for superconductors.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122455566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990965
G. Datta, Haolin Cong, Souvik Kundu, P. Beerel
Digital single-flux quantum (SFQ) technology promises to meet the demands of ultra low power and high speed computing needed for future exascale supercomputing systems. The combination of ultra high clock frequencies, gate-level pipelines, and numerous sources of variability in SFQ circuits, however, make low-skew global clock distribution a challenge. This motivates the support of multiple independent clock domains and related clock domain crossing circuits that enable reliable communication across domains. Existing J-SIM simulation models indicate that setup violations can cause clock-to-Q increases of up to 100%. This paper first shows that naive SFQ clock domain crossing (CDC) first-in-first-out buffers (FIFOs) are vulnerable to these delay increases, motivating the need for more robust CDC FIFOs. Inspired by CMOS multi-flip-flop asynchronous FIFO synchronizers, we then propose a novel 1-bit metastability-resilient SFQ CDC FIFO that simulations show delivers over a 1000 reduction in logical error rate at 30 GHz. Moreover, for a 10-stage FIFO, the Josephson junction (JJ) area of our proposed design is only 7.5% larger than the non-resilient counterpart. Finally, we propose design guidelines that define the minimal FIFO depth subject to both throughput and burstiness constraints.
{"title":"qCDC: Metastability-Resilient Synchronization FIFO for SFQ Logic","authors":"G. Datta, Haolin Cong, Souvik Kundu, P. Beerel","doi":"10.1109/ISEC46533.2019.8990965","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990965","url":null,"abstract":"Digital single-flux quantum (SFQ) technology promises to meet the demands of ultra low power and high speed computing needed for future exascale supercomputing systems. The combination of ultra high clock frequencies, gate-level pipelines, and numerous sources of variability in SFQ circuits, however, make low-skew global clock distribution a challenge. This motivates the support of multiple independent clock domains and related clock domain crossing circuits that enable reliable communication across domains. Existing J-SIM simulation models indicate that setup violations can cause clock-to-Q increases of up to 100%. This paper first shows that naive SFQ clock domain crossing (CDC) first-in-first-out buffers (FIFOs) are vulnerable to these delay increases, motivating the need for more robust CDC FIFOs. Inspired by CMOS multi-flip-flop asynchronous FIFO synchronizers, we then propose a novel 1-bit metastability-resilient SFQ CDC FIFO that simulations show delivers over a 1000 reduction in logical error rate at 30 GHz. Moreover, for a 10-stage FIFO, the Josephson junction (JJ) area of our proposed design is only 7.5% larger than the non-resilient counterpart. Finally, we propose design guidelines that define the minimal FIFO depth subject to both throughput and burstiness constraints.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116981041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990937
N. Flowers-Jacobs, A. Rüfenacht, A. Fox, S. Waltman, R. Schwall, J. Brevik, P. Dresselhaus, S. Benz
We have recently created a 4 V rms cryocooled JAWS (Josephson Arbitrary Waveform Synthesizer) using 204,960 nearly identical Josephson junctions (JJs) that are embedded in coplanar-wave guides. The JJs are pulse-biased at repetition rates up to 16×109 pulses per second to create quantum-accurate, calculable AC waveforms at frequencies from DC to greater than 1 MHz. This system has metrological applications including in precision ac voltage calibrations, comparisons of arbitrary impedances, and ac power measurements.
我们最近创建了一个4 V rms的冷冻JAWS(约瑟夫森任意波形合成器)，使用204,960个几乎相同的约瑟夫森结(js)嵌入在共面波导中。JJs以每秒16×109脉冲的重复速率进行脉冲偏置，以在直流到大于1mhz的频率范围内创建量子精确的、可计算的交流波形。该系统具有计量应用，包括精密交流电压校准、任意阻抗比较和交流功率测量。
{"title":"Development and Applications of a Four-Volt Josephson Arbitrary Waveform Synthesizer","authors":"N. Flowers-Jacobs, A. Rüfenacht, A. Fox, S. Waltman, R. Schwall, J. Brevik, P. Dresselhaus, S. Benz","doi":"10.1109/ISEC46533.2019.8990937","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990937","url":null,"abstract":"We have recently created a 4 V rms cryocooled JAWS (Josephson Arbitrary Waveform Synthesizer) using 204,960 nearly identical Josephson junctions (JJs) that are embedded in coplanar-wave guides. The JJs are pulse-biased at repetition rates up to 16×109 pulses per second to create quantum-accurate, calculable AC waveforms at frequencies from DC to greater than 1 MHz. This system has metrological applications including in precision ac voltage calibrations, comparisons of arbitrary impedances, and ac power measurements.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122686370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990956
R. van Staden, J. Delport, J. A. Coetzee, C. Fourie
The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled inductors, all of which are not adequately supported by conventional semiconductor layout-versus-schematic verification (LVS) tools. Such circuits are also susceptible to failure in the presence of magnetic fields above about one tenth of the Earth's field strength and to magnetic flux trapped in layout structures during cool-down, so that magnetic rule checking (MRC) is essential. Under SuperTools we developed an open-source LVS framework, SPiRA, which allows for the parametric creation, alteration and verification of superconductor and quantum circuit layouts. SPiRA is a Python-based framework developed to aid the process of creating parameterized layouts while simultaneously taking into account design rule (DRC) as well as magnetic rule checking. SPiRA is designed to accept any process through a rule deck database (RDD) Python-based PDK schema from which cells are spawned as objects with inherent properties. This process allows rapid implementation of changes to layouts with the ability to extract an electrical netlist that can be simulated, and parameter extraction performed upon. SPiRA creates layouts in the GDSII layout format and allows quick visualization of the layout using the Gdspy library. We present extraction results for examples created parametrically with SPiRA, compare those to results for layouts created by hand and evaluate the capabilities of SPiRA. Finally we show how SPiRA improves models for inductance and compact model extraction with the inductance extraction tool InductEx.
{"title":"Layout versus Schematic with Design/Magnetic Rule Checking for Superconducting Integrated Circuit Layouts","authors":"R. van Staden, J. Delport, J. A. Coetzee, C. Fourie","doi":"10.1109/ISEC46533.2019.8990956","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990956","url":null,"abstract":"The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled inductors, all of which are not adequately supported by conventional semiconductor layout-versus-schematic verification (LVS) tools. Such circuits are also susceptible to failure in the presence of magnetic fields above about one tenth of the Earth's field strength and to magnetic flux trapped in layout structures during cool-down, so that magnetic rule checking (MRC) is essential. Under SuperTools we developed an open-source LVS framework, SPiRA, which allows for the parametric creation, alteration and verification of superconductor and quantum circuit layouts. SPiRA is a Python-based framework developed to aid the process of creating parameterized layouts while simultaneously taking into account design rule (DRC) as well as magnetic rule checking. SPiRA is designed to accept any process through a rule deck database (RDD) Python-based PDK schema from which cells are spawned as objects with inherent properties. This process allows rapid implementation of changes to layouts with the ability to extract an electrical netlist that can be simulated, and parameter extraction performed upon. SPiRA creates layouts in the GDSII layout format and allows quick visualization of the layout using the Gdspy library. We present extraction results for examples created parametrically with SPiRA, compare those to results for layouts created by hand and evaluate the capabilities of SPiRA. Finally we show how SPiRA improves models for inductance and compact model extraction with the inductance extraction tool InductEx.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129680665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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