Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990941
N. Katam, Haolin Cong, M. Pedram
Field Programmable gate arrays (FPGAs) are one of the most successful circuits in the semiconductor industry. In the absence of a reliable three-terminal switch like MOSFET for rapid single flux quantum(RSFQ) technology, it was difficult to implement FPGA like reconfiguralbe circuits. However, a recently proposed superconducting magnetic FPGA (SMFPGA) implements a controllable switch by controlling the critical current of magnetic Josephson Junctions (MJJs) placed in energy-efficient RSFQ bias network. For implementing a configurable logic block (CLB) with a smaller area for the said FPGA, we designed a reconfigurable gate that can implement four basic logical functions: AND, OR, XOR and NOT. The programmability to implement the four functions is achieved by introducing MJJs in the circuit at specific locations and programming their critical current. The gate is made reconfigurable by having the ability to change both the bias current at different ports and the critical current of a JJ in the gate to two different values. This makes the size of CLB ten times smaller compared to the earlier design and simplifies the SMFPGA. We describe the design methodology and the simulation results of the reconfigurable gate.
{"title":"Reconfigurable Logic Cell for Superconducting Magnetic Field Programmable Gate Array","authors":"N. Katam, Haolin Cong, M. Pedram","doi":"10.1109/ISEC46533.2019.8990941","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990941","url":null,"abstract":"Field Programmable gate arrays (FPGAs) are one of the most successful circuits in the semiconductor industry. In the absence of a reliable three-terminal switch like MOSFET for rapid single flux quantum(RSFQ) technology, it was difficult to implement FPGA like reconfiguralbe circuits. However, a recently proposed superconducting magnetic FPGA (SMFPGA) implements a controllable switch by controlling the critical current of magnetic Josephson Junctions (MJJs) placed in energy-efficient RSFQ bias network. For implementing a configurable logic block (CLB) with a smaller area for the said FPGA, we designed a reconfigurable gate that can implement four basic logical functions: AND, OR, XOR and NOT. The programmability to implement the four functions is achieved by introducing MJJs in the circuit at specific locations and programming their critical current. The gate is made reconfigurable by having the ability to change both the bias current at different ports and the critical current of a JJ in the gate to two different values. This makes the size of CLB ten times smaller compared to the earlier design and simplifies the SMFPGA. We describe the design methodology and the simulation results of the reconfigurable gate.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126868483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990938
J. LeFebvre, E. Cho, Kevin Pratt, S. Cybart
We investigated series arrays of closely spaced, planar long Josephson junctions for magnetic flux transduction with a linear response and high dynamic range. The devices were fabricated from 30-nm thick high-temperature superconducting YBa2Cu3O7-δ(YBCO) thin films, using focused helium ion beam irradiation to create the Josephson barriers. Series arrays consisting of 600 long junctions, were fabricated and electrically tested. From fits of the current-voltage characteristics we estimate the standard deviation in critical current to be around 25%. Voltage-magnetic field measurements exhibit a sharp transfer function with a modulation depth of 11 mV over a range of 135μ $T$ at 71 K.
{"title":"Series Arrays of Long Josephson Junctions Fabricated with a Focused Helium Ion Beam in YBa2Cu3O7-δ","authors":"J. LeFebvre, E. Cho, Kevin Pratt, S. Cybart","doi":"10.1109/ISEC46533.2019.8990938","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990938","url":null,"abstract":"We investigated series arrays of closely spaced, planar long Josephson junctions for magnetic flux transduction with a linear response and high dynamic range. The devices were fabricated from 30-nm thick high-temperature superconducting YBa2Cu3O7-δ(YBCO) thin films, using focused helium ion beam irradiation to create the Josephson barriers. Series arrays consisting of 600 long junctions, were fabricated and electrically tested. From fits of the current-voltage characteristics we estimate the standard deviation in critical current to be around 25%. Voltage-magnetic field measurements exhibit a sharp transfer function with a modulation depth of 11 mV over a range of 135μ $T$ at 71 K.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116071512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990966
D. Richter, A. Fleischmann, C. Enss, S. Kempf
We present a novel dc-SQUID readout scheme that provides linearization of the relation between the input and output signal without using a conventional flux-locked loop circuit. It relies on applying a periodic, sawtooth-shaped magnetic flux signal to the modulation coil of the SQUID to continuously measure the flux-to-voltage SQUID characteristic within each period of the flux ramp. In case that the amplitude and repetition rate of the ramp are chosen such that multiple flux quanta are induced in the SQUID and that the input signal is quasistatic within one period of the flux ramp, the input signal adds a constant magnetic flux offset to the SQUID that leads to a phase shift of the SQUID characteristic being proportional to the input signal. We show that this scheme allows for significantly increasing the dynamic range and that it intrinsically allows for MHz frequency-division SQUID multiplexing.
{"title":"Dc-SQUID Readout with High Dynamic Range and Intrinsic MHz Frequency-Division Multiplexing Capability","authors":"D. Richter, A. Fleischmann, C. Enss, S. Kempf","doi":"10.1109/ISEC46533.2019.8990966","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990966","url":null,"abstract":"We present a novel dc-SQUID readout scheme that provides linearization of the relation between the input and output signal without using a conventional flux-locked loop circuit. It relies on applying a periodic, sawtooth-shaped magnetic flux signal to the modulation coil of the SQUID to continuously measure the flux-to-voltage SQUID characteristic within each period of the flux ramp. In case that the amplitude and repetition rate of the ramp are chosen such that multiple flux quanta are induced in the SQUID and that the input signal is quasistatic within one period of the flux ramp, the input signal adds a constant magnetic flux offset to the SQUID that leads to a phase shift of the SQUID characteristic being proportional to the input signal. We show that this scheme allows for significantly increasing the dynamic range and that it intrinsically allows for MHz frequency-division SQUID multiplexing.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128050799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990923
M. E. Çelik, T. Filippov, A. Sahu, D. Kirichenko, S. Sarwana, A. E. Lehmann, D. Gupta
Historically one of the most challenging high-speed RSFQ circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums 7 inputs has been designed and tested at clock frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output was designed using two flavors of 8-to-4 summing circuits. The first (8-to-4a), based on the 7-to-3 parallel counter, sums 8 unweighted inputs whereas the second (8-to-4b) sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights from two 8-to-4a blocks. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.
历史上最具挑战性的高速RSFQ电路之一是一个并行计数器，它对一组未加权输入求和，并以相同的时钟速率产生二进制加权单词。设计了一个7对3并行计数器，该计数器将7个输入加起来，并使用自己的专用测试平台在时钟频率高达50 GHz的情况下进行测试。使用麻省理工学院林肯实验室的铸造厂，以10和20 ka /cm2的电流密度生产，这种7比3的求和电路已成为数字电路的基准。最近，一个具有15个并行输入产生4位输出的版本使用两种8对4求和电路设计。第一个(8-to-4a)基于7-to-3并行计数器，对8个未加权输入求和，而第二个(8-to-4b)通过对两个8-to-4a块中权重相等的位进行成对求和，对两个4位二进制加权单词求和。我们将在讨论电路性能和良率的同时，讨论该电路的设计考虑因素。
{"title":"Fast RSFQ and ERSFQ Parallel Counters","authors":"M. E. Çelik, T. Filippov, A. Sahu, D. Kirichenko, S. Sarwana, A. E. Lehmann, D. Gupta","doi":"10.1109/ISEC46533.2019.8990923","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990923","url":null,"abstract":"Historically one of the most challenging high-speed RSFQ circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums 7 inputs has been designed and tested at clock frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output was designed using two flavors of 8-to-4 summing circuits. The first (8-to-4a), based on the 7-to-3 parallel counter, sums 8 unweighted inputs whereas the second (8-to-4b) sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights from two 8-to-4a blocks. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121891115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990931
S. Whiteley, J. Kawa
Synopsys is developing a complete design flow tool set for use with superconductive digital logic, initially focusing on ERSFQ and AQFP technologies. This flow begins with design synthesis of a high level logic description, automating cell placement, routing, and design validation. Circuit simulation and statistical analysis tools utilizing advanced TCAD techniques are also under development. The flow will provide a tool set to address all requirements culminating with a tape-out. The proposed flow will parallel the functionality used routinely in the semiconductor industry, but is still at a very early stage of development for superconductors.
{"title":"Progress Toward VLSI-Capable EDA Tools for Superconductive Digital Electronics","authors":"S. Whiteley, J. Kawa","doi":"10.1109/ISEC46533.2019.8990931","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990931","url":null,"abstract":"Synopsys is developing a complete design flow tool set for use with superconductive digital logic, initially focusing on ERSFQ and AQFP technologies. This flow begins with design synthesis of a high level logic description, automating cell placement, routing, and design validation. Circuit simulation and statistical analysis tools utilizing advanced TCAD techniques are also under development. The flow will provide a tool set to address all requirements culminating with a tape-out. The proposed flow will parallel the functionality used routinely in the semiconductor industry, but is still at a very early stage of development for superconductors.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122455566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990937
N. Flowers-Jacobs, A. Rüfenacht, A. Fox, S. Waltman, R. Schwall, J. Brevik, P. Dresselhaus, S. Benz
We have recently created a 4 V rms cryocooled JAWS (Josephson Arbitrary Waveform Synthesizer) using 204,960 nearly identical Josephson junctions (JJs) that are embedded in coplanar-wave guides. The JJs are pulse-biased at repetition rates up to 16×109 pulses per second to create quantum-accurate, calculable AC waveforms at frequencies from DC to greater than 1 MHz. This system has metrological applications including in precision ac voltage calibrations, comparisons of arbitrary impedances, and ac power measurements.
我们最近创建了一个4 V rms的冷冻JAWS(约瑟夫森任意波形合成器)，使用204,960个几乎相同的约瑟夫森结(js)嵌入在共面波导中。JJs以每秒16×109脉冲的重复速率进行脉冲偏置，以在直流到大于1mhz的频率范围内创建量子精确的、可计算的交流波形。该系统具有计量应用，包括精密交流电压校准、任意阻抗比较和交流功率测量。
{"title":"Development and Applications of a Four-Volt Josephson Arbitrary Waveform Synthesizer","authors":"N. Flowers-Jacobs, A. Rüfenacht, A. Fox, S. Waltman, R. Schwall, J. Brevik, P. Dresselhaus, S. Benz","doi":"10.1109/ISEC46533.2019.8990937","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990937","url":null,"abstract":"We have recently created a 4 V rms cryocooled JAWS (Josephson Arbitrary Waveform Synthesizer) using 204,960 nearly identical Josephson junctions (JJs) that are embedded in coplanar-wave guides. The JJs are pulse-biased at repetition rates up to 16×109 pulses per second to create quantum-accurate, calculable AC waveforms at frequencies from DC to greater than 1 MHz. This system has metrological applications including in precision ac voltage calibrations, comparisons of arbitrary impedances, and ac power measurements.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122686370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990903
Takashi Dejima, K. Takagi, N. Takagi
We propose placement and routing methods integrated in automated layout design flow for rapid single-flux-quantum (RSFQ) circuits. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering proper use of JTLs and PTLs. The placement problem is divided into subproblems in order to reduce the computational cost. The placement method is composed of three steps, i.e., (i) Cell clustering, (ii) Cell placement and JTL routing in each cluster, and (iii) Cluster placement. Routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed with the proposed methods are smaller than those of the circuits designed manually.
{"title":"Placement and Routing Methods Based on Mixed Wiring of JTLs and PTLs for RSFQ circuits","authors":"Takashi Dejima, K. Takagi, N. Takagi","doi":"10.1109/ISEC46533.2019.8990903","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990903","url":null,"abstract":"We propose placement and routing methods integrated in automated layout design flow for rapid single-flux-quantum (RSFQ) circuits. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering proper use of JTLs and PTLs. The placement problem is divided into subproblems in order to reduce the computational cost. The placement method is composed of three steps, i.e., (i) Cell clustering, (ii) Cell placement and JTL routing in each cluster, and (iii) Cluster placement. Routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed with the proposed methods are smaller than those of the circuits designed manually.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122707609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990900
M. Frank, Rupert M. Lewis, N. Missert, M. Henry, M. Wolak, E. Debenedictis
In an ongoing project at Sandia National Laboratories, we are attempting to develop a novel style of superconducting digital processing, based on a new model of reversible computation called Asynchronous Ballistic Reversible Computing (ABRC). We envision an approach in which polarized flux-ons scatter elastically from near-lossless functional components, reversibly updating the local digital state of the circuit, while dissipating only a small fraction of the input fluxon energy. This approach to superconducting digital computation is sufficiently unconventional that an appropriate methodology for hand-design of such circuits is not immediately obvious. To gain insight into the design principles that are applicable in this new domain, we are creating a software tool to automatically enumerate possible topologies of reactive, undamped Josephson junction circuits, and sweep the parameter space of each circuit searching for designs exhibiting desired dynamical behaviors. But first, we identified by hand a circuit implementing the simplest possible nontrivial ABRC functional behavior with bits encoded as conserved polarized fluxons, namely, a one-bit reversible memory cell with one bidirectional I/O port. We expect the tool to be useful for designing more complex circuits.
{"title":"Semi-Automated Design of Functional Elements for a New Approach to Digital Superconducting Electronics: Methodology and Preliminary Results","authors":"M. Frank, Rupert M. Lewis, N. Missert, M. Henry, M. Wolak, E. Debenedictis","doi":"10.1109/ISEC46533.2019.8990900","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990900","url":null,"abstract":"In an ongoing project at Sandia National Laboratories, we are attempting to develop a novel style of superconducting digital processing, based on a new model of reversible computation called Asynchronous Ballistic Reversible Computing (ABRC). We envision an approach in which polarized flux-ons scatter elastically from near-lossless functional components, reversibly updating the local digital state of the circuit, while dissipating only a small fraction of the input fluxon energy. This approach to superconducting digital computation is sufficiently unconventional that an appropriate methodology for hand-design of such circuits is not immediately obvious. To gain insight into the design principles that are applicable in this new domain, we are creating a software tool to automatically enumerate possible topologies of reactive, undamped Josephson junction circuits, and sweep the parameter space of each circuit searching for designs exhibiting desired dynamical behaviors. But first, we identified by hand a circuit implementing the simplest possible nontrivial ABRC functional behavior with bits encoded as conserved polarized fluxons, namely, a one-bit reversible memory cell with one bidirectional I/O port. We expect the tool to be useful for designing more complex circuits.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"450 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124287560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990956
R. van Staden, J. Delport, J. A. Coetzee, C. Fourie
The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled inductors, all of which are not adequately supported by conventional semiconductor layout-versus-schematic verification (LVS) tools. Such circuits are also susceptible to failure in the presence of magnetic fields above about one tenth of the Earth's field strength and to magnetic flux trapped in layout structures during cool-down, so that magnetic rule checking (MRC) is essential. Under SuperTools we developed an open-source LVS framework, SPiRA, which allows for the parametric creation, alteration and verification of superconductor and quantum circuit layouts. SPiRA is a Python-based framework developed to aid the process of creating parameterized layouts while simultaneously taking into account design rule (DRC) as well as magnetic rule checking. SPiRA is designed to accept any process through a rule deck database (RDD) Python-based PDK schema from which cells are spawned as objects with inherent properties. This process allows rapid implementation of changes to layouts with the ability to extract an electrical netlist that can be simulated, and parameter extraction performed upon. SPiRA creates layouts in the GDSII layout format and allows quick visualization of the layout using the Gdspy library. We present extraction results for examples created parametrically with SPiRA, compare those to results for layouts created by hand and evaluate the capabilities of SPiRA. Finally we show how SPiRA improves models for inductance and compact model extraction with the inductance extraction tool InductEx.
{"title":"Layout versus Schematic with Design/Magnetic Rule Checking for Superconducting Integrated Circuit Layouts","authors":"R. van Staden, J. Delport, J. A. Coetzee, C. Fourie","doi":"10.1109/ISEC46533.2019.8990956","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990956","url":null,"abstract":"The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled inductors, all of which are not adequately supported by conventional semiconductor layout-versus-schematic verification (LVS) tools. Such circuits are also susceptible to failure in the presence of magnetic fields above about one tenth of the Earth's field strength and to magnetic flux trapped in layout structures during cool-down, so that magnetic rule checking (MRC) is essential. Under SuperTools we developed an open-source LVS framework, SPiRA, which allows for the parametric creation, alteration and verification of superconductor and quantum circuit layouts. SPiRA is a Python-based framework developed to aid the process of creating parameterized layouts while simultaneously taking into account design rule (DRC) as well as magnetic rule checking. SPiRA is designed to accept any process through a rule deck database (RDD) Python-based PDK schema from which cells are spawned as objects with inherent properties. This process allows rapid implementation of changes to layouts with the ability to extract an electrical netlist that can be simulated, and parameter extraction performed upon. SPiRA creates layouts in the GDSII layout format and allows quick visualization of the layout using the Gdspy library. We present extraction results for examples created parametrically with SPiRA, compare those to results for layouts created by hand and evaluate the capabilities of SPiRA. Finally we show how SPiRA improves models for inductance and compact model extraction with the inductance extraction tool InductEx.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129680665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ISEC46533.2019.8990958
T. Filippov, A. Sahu, M. E. Çelik, D. Kirichenko, D. Gupta
The Josephson balanced comparator is the key component of Single Flux Quantum logic devices because it is the decision making element. It is formed by two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured. Its noise properties are crucial for the performance of logic devices. The balanced comparator can also be used to monitor the fab process and design implementation as an indicator of excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure the comparator gray zone at different fabrication process nodes at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies. An analog testbed was used to perform high-frequency characterization. Experimental results for different current densities, sheet resistances, damping and clock frequencies are presented.
{"title":"The Josephson Balanced Comparator and its Gray Zone Measurements","authors":"T. Filippov, A. Sahu, M. E. Çelik, D. Kirichenko, D. Gupta","doi":"10.1109/ISEC46533.2019.8990958","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990958","url":null,"abstract":"The Josephson balanced comparator is the key component of Single Flux Quantum logic devices because it is the decision making element. It is formed by two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured. Its noise properties are crucial for the performance of logic devices. The balanced comparator can also be used to monitor the fab process and design implementation as an indicator of excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure the comparator gray zone at different fabrication process nodes at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies. An analog testbed was used to perform high-frequency characterization. Experimental results for different current densities, sheet resistances, damping and clock frequencies are presented.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131110313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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