Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122344
A. Dehqan, K. Mafinezhad, E. Kargaran, H. Nabovati
A low voltage, low power dual band Low Noise Amplifier (LNA) is presented in this paper. By employing a forward body bias of the MOSFET and current reuse topology the LNA can be operated at reduced supply voltage and power consumption while maintaining high gain due to its topology. Using 0.18 um CMOS process the LNA is designed at 2.4 GHz and 5.2GHz with 13.1 dB and 14.2 dB voltage gains and 2.9dB and 2.6dB NF respectively with 0.7V supply voltage and 3mW power consumption.
本文介绍了一种低电压、低功耗的双频低噪声放大器。通过采用MOSFET的正向偏置和电流复用拓扑，LNA可以在降低电源电压和功耗的情况下工作，同时由于其拓扑结构而保持高增益。LNA采用0.18 um CMOS工艺设计，工作频率分别为2.4 GHz和5.2GHz，电压增益分别为13.1 dB和14.2 dB, NF增益分别为2.9dB和2.6dB，电源电压为0.7V，功耗为3mW。
{"title":"Design of low voltage low power dual-band LNA with forward body biasing technique","authors":"A. Dehqan, K. Mafinezhad, E. Kargaran, H. Nabovati","doi":"10.1109/ICECS.2011.6122344","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122344","url":null,"abstract":"A low voltage, low power dual band Low Noise Amplifier (LNA) is presented in this paper. By employing a forward body bias of the MOSFET and current reuse topology the LNA can be operated at reduced supply voltage and power consumption while maintaining high gain due to its topology. Using 0.18 um CMOS process the LNA is designed at 2.4 GHz and 5.2GHz with 13.1 dB and 14.2 dB voltage gains and 2.9dB and 2.6dB NF respectively with 0.7V supply voltage and 3mW power consumption.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"49 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131374277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122297
S. Adami, N. Degrenne, C. Vollaire, B. Allard, F. Buret, F. Costa
In this paper, an ultra-low voltage and power DC/DC converter is presented. This converter harvests energy from a Microbial Fuel Cell (MFC) in order to feed another circuit such as an autonomous wireless sensor. The MFC behaves as a voltage generator of 475mV open-circuit voltage with a 600Ω serial internal impedance. The maximum delivered power is therefore around 100μW. The DC/DC converter provides output voltage in the range 2–7.5V and performs impedance matching with source. The converter achieves when associated with the MFC, 60% peak efficiency. Furthermore, this DC/DC converter is self-operating without the need for external power source of start-up assistance.
{"title":"Autonomous ultra-low power DC/DC converter for Microbial Fuel Cells","authors":"S. Adami, N. Degrenne, C. Vollaire, B. Allard, F. Buret, F. Costa","doi":"10.1109/ICECS.2011.6122297","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122297","url":null,"abstract":"In this paper, an ultra-low voltage and power DC/DC converter is presented. This converter harvests energy from a Microbial Fuel Cell (MFC) in order to feed another circuit such as an autonomous wireless sensor. The MFC behaves as a voltage generator of 475mV open-circuit voltage with a 600Ω serial internal impedance. The maximum delivered power is therefore around 100μW. The DC/DC converter provides output voltage in the range 2–7.5V and performs impedance matching with source. The converter achieves when associated with the MFC, 60% peak efficiency. Furthermore, this DC/DC converter is self-operating without the need for external power source of start-up assistance.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134266916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122373
Ji Qiu, Xiang Gao, Yifei Jiang, Xu Xiao
ISS (Instruction Set Simulator) plays an important role in pre-silicon software development for ASIP. However, the speed of traditional simulation is too slow to effectively support full-scale software development. In this paper, we propose a hybrid simulation framework which further improves the previous simulation methods by aggressively utilizing the host machine resources. The utilization is achieved by categorizing instructions of ASIP application into two types, namely custom and basic instructions, via binary instrumentation. Then in a way of hybrid simulation, only custom instructions are simulated on the ISS and basic instructions are executed fast and natively on the host machine. We implement this framework for an industrial ASIP to validate our approach. Experimental results show that when the implemented ISS, namely GS-Sim, is applied to practical multimedia decoders, an average simulation speed up to 1058.5MIPS can be achieved, which is 34.7 times of the state-of-art dynamic binary translation simulator and is the fastest to the best of our knowledge.
{"title":"An ultra-fast hybrid simulation framework for ASIP","authors":"Ji Qiu, Xiang Gao, Yifei Jiang, Xu Xiao","doi":"10.1109/ICECS.2011.6122373","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122373","url":null,"abstract":"ISS (Instruction Set Simulator) plays an important role in pre-silicon software development for ASIP. However, the speed of traditional simulation is too slow to effectively support full-scale software development. In this paper, we propose a hybrid simulation framework which further improves the previous simulation methods by aggressively utilizing the host machine resources. The utilization is achieved by categorizing instructions of ASIP application into two types, namely custom and basic instructions, via binary instrumentation. Then in a way of hybrid simulation, only custom instructions are simulated on the ISS and basic instructions are executed fast and natively on the host machine. We implement this framework for an industrial ASIP to validate our approach. Experimental results show that when the implemented ISS, namely GS-Sim, is applied to practical multimedia decoders, an average simulation speed up to 1058.5MIPS can be achieved, which is 34.7 times of the state-of-art dynamic binary translation simulator and is the fastest to the best of our knowledge.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122210832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122213
Y. Abiven, F. Rivet, Y. Deval, D. Dallet, D. Belot, T. Taris
Multi-standard applications encounter several developments in the wireless systems. A single receiver is required for any standard of communication. Software Radio (SR) is an illustration of this concept. This paper presents a design methodology to ease the design of a flexible RF receiver based on an analog discrete time Fast Fourier Transform (FFT). A proposed architecture named SASP (Sampled Analog Signal Processor) targets the previously exposed concept for wireless constraints. The FFT algorithm brings an analog weighting unit which is the most power hungry part in such an analog discrete time processor.
{"title":"A low-power 2 GHz discrete time weighting system dedicated to Sampled Analog Signal Processing","authors":"Y. Abiven, F. Rivet, Y. Deval, D. Dallet, D. Belot, T. Taris","doi":"10.1109/ICECS.2011.6122213","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122213","url":null,"abstract":"Multi-standard applications encounter several developments in the wireless systems. A single receiver is required for any standard of communication. Software Radio (SR) is an illustration of this concept. This paper presents a design methodology to ease the design of a flexible RF receiver based on an analog discrete time Fast Fourier Transform (FFT). A proposed architecture named SASP (Sampled Analog Signal Processor) targets the previously exposed concept for wireless constraints. The FFT algorithm brings an analog weighting unit which is the most power hungry part in such an analog discrete time processor.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117274878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122385
K. Leboeuf, Iman Makaremi, R. Muscedere, M. Ahmadi
Plastics are used in a truly vast number of applications, and research is continously carried out to improve every aspect of the plastics industry. A recent study of laser transmission welding [1] required cross-sectional images of the weld's microstructure to be analyzed for the presence of pores, which are tiny bubbles that may form during the weld process. It is believed that the number and size of pores may be indicative of the weld strength [1]. The current state of the art for detecting these pores involves manually drawing a contour around each one; a laborious process given that a typical sample may have hundreds-to-thousands of pores. This paper presents a segmentation system for classifying the pixels of a microstructural image of a thermoplastic laser weld as either belonging to a pore or the background. The algorithm is robust in terms of dealing with noise from flbreglass strands, cloudy pores, and varying exposure time. On average, it is estimated that the proposed algorithm is able to correctly classify pores at a rate of approximately 90% without requiring any user intervention.
{"title":"Image processing technique for segmenting microstructural porosity of laser-welded thermoplastics","authors":"K. Leboeuf, Iman Makaremi, R. Muscedere, M. Ahmadi","doi":"10.1109/ICECS.2011.6122385","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122385","url":null,"abstract":"Plastics are used in a truly vast number of applications, and research is continously carried out to improve every aspect of the plastics industry. A recent study of laser transmission welding [1] required cross-sectional images of the weld's microstructure to be analyzed for the presence of pores, which are tiny bubbles that may form during the weld process. It is believed that the number and size of pores may be indicative of the weld strength [1]. The current state of the art for detecting these pores involves manually drawing a contour around each one; a laborious process given that a typical sample may have hundreds-to-thousands of pores. This paper presents a segmentation system for classifying the pixels of a microstructural image of a thermoplastic laser weld as either belonging to a pore or the background. The algorithm is robust in terms of dealing with noise from flbreglass strands, cloudy pores, and varying exposure time. On average, it is estimated that the proposed algorithm is able to correctly classify pores at a rate of approximately 90% without requiring any user intervention.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116356399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122343
L. Mohjazi, M. Al-Qutayri, H. Barada, K. Poon
Self-optimization of coverage is an essential element for successful deployment of enterprise femtocells. This paper evaluates the performance of genetic algorithm, particle swarm and simulated annealing heuristic techniques to solve a multi-objective coverage optimization problem when a number of femtocells are deployed to jointly provide indoor coverage. This paper demonstrates the different behaviors of the proposed algorithms. The results show that genetic algorithm and particle swarm have a higher potential of solving the problem compared to simulated annealing. This is due to their faster convergence time which is an important parameter for dynamic update of femtocells.
{"title":"Performance evaluation of heuristic techniques for coverage optimization in femtocells","authors":"L. Mohjazi, M. Al-Qutayri, H. Barada, K. Poon","doi":"10.1109/ICECS.2011.6122343","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122343","url":null,"abstract":"Self-optimization of coverage is an essential element for successful deployment of enterprise femtocells. This paper evaluates the performance of genetic algorithm, particle swarm and simulated annealing heuristic techniques to solve a multi-objective coverage optimization problem when a number of femtocells are deployed to jointly provide indoor coverage. This paper demonstrates the different behaviors of the proposed algorithms. The results show that genetic algorithm and particle swarm have a higher potential of solving the problem compared to simulated annealing. This is due to their faster convergence time which is an important parameter for dynamic update of femtocells.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116258301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For a conventional SRAM, bit-lines dissipate the largest part of power consumption, since they are long lines with parasitical capacitance. Furthermore, the bit-lines consume more power in write cycle than in read cycle. A new charge-recycling method is proposed to reduce bit-line power consumption. The proposed SRAM pre-charge the bit-lines to VDD or GND respectively, they share the charge of adjacent bit-lines in write cycle. This is different from the former charge-recycling technique, because it does not need the additional voltage supply except VDD. SRAM cells also dissipate a lot of leakage power consumption in inactive cycle. The proposed SRAM uses non uniform cell method to reduce gate leakage. In this paper, a 64kb (4k∗16bits) 1-port SRAM is implemented with 100nm CMOS technology, the simulation results show that it reduces 32.9% leakage for SRAM cell in inactive mode, and 22% total power consumption to the conventional SRAM.
{"title":"A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme","authors":"Xu Wang, Jianfei Jiang, Zhigang Mao, Bingjing Ge, Xing-long Zhao","doi":"10.1109/ICECS.2011.6122329","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122329","url":null,"abstract":"For a conventional SRAM, bit-lines dissipate the largest part of power consumption, since they are long lines with parasitical capacitance. Furthermore, the bit-lines consume more power in write cycle than in read cycle. A new charge-recycling method is proposed to reduce bit-line power consumption. The proposed SRAM pre-charge the bit-lines to VDD or GND respectively, they share the charge of adjacent bit-lines in write cycle. This is different from the former charge-recycling technique, because it does not need the additional voltage supply except VDD. SRAM cells also dissipate a lot of leakage power consumption in inactive cycle. The proposed SRAM uses non uniform cell method to reduce gate leakage. In this paper, a 64kb (4k∗16bits) 1-port SRAM is implemented with 100nm CMOS technology, the simulation results show that it reduces 32.9% leakage for SRAM cell in inactive mode, and 22% total power consumption to the conventional SRAM.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114992982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122237
K. Manolopoulos, D. Reisis, V. Chouliaras
The current paper presents a multi-mode floating point multiplier operating efficiently with every precision format specified by the IEEE 754–2008 standard. The design performs one quadruple precision multiplication, or two double precision multiplications in parallel, or four single precision multiplications in parallel. The proposed multiplier is pipelined to achieve execution of one quadruple multiplication in 3 cycles and either two double precision operations in parallel or four single precision operations in parallel in only 2 cycles. The proposed design improves the throughput by a factor of two compared to a double precision multiplier and by four compared to a single precision multiplication. An example implementation on VLSI verifies the design and it achieves a maximum operating frequency of 505 MHz.
{"title":"An efficient multiple precision floating-point multiplier","authors":"K. Manolopoulos, D. Reisis, V. Chouliaras","doi":"10.1109/ICECS.2011.6122237","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122237","url":null,"abstract":"The current paper presents a multi-mode floating point multiplier operating efficiently with every precision format specified by the IEEE 754–2008 standard. The design performs one quadruple precision multiplication, or two double precision multiplications in parallel, or four single precision multiplications in parallel. The proposed multiplier is pipelined to achieve execution of one quadruple multiplication in 3 cycles and either two double precision operations in parallel or four single precision operations in parallel in only 2 cycles. The proposed design improves the throughput by a factor of two compared to a double precision multiplier and by four compared to a single precision multiplication. An example implementation on VLSI verifies the design and it achieves a maximum operating frequency of 505 MHz.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121662923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122273
Salim N. Batlouni, Hala S. Karaki, F. Zaraket, F. Karameh
Speech recognition has become widely used across many applications. Telephone systems can route a phone call based on what the caller says, control systems can respond to actions said by the controller, and mobile phones can recognize the speech of a contact's name and call the respective contact directly. However, speech recognition has found little use in recognition of textual material due to the large dictionary and hence large word error rates. Mathifier constricts the speech recognition to math equations; it takes as input math formulas presented in the form of user speech and produces the equations in digital mathematical form. The smaller dictionary and the specific grammar structure of the math equations help restrict the problem of the recognition process. The program has room for smartly guessing words based on the grammar structure and thus resulting in a lower error rate and better recognition. Mathifier uses Sphinx, a modular speech recognition tool from CMU, and adapts it to recognize math equations and convert them into latex form in real time.
{"title":"Mathifier — Speech recognition of math equations","authors":"Salim N. Batlouni, Hala S. Karaki, F. Zaraket, F. Karameh","doi":"10.1109/ICECS.2011.6122273","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122273","url":null,"abstract":"Speech recognition has become widely used across many applications. Telephone systems can route a phone call based on what the caller says, control systems can respond to actions said by the controller, and mobile phones can recognize the speech of a contact's name and call the respective contact directly. However, speech recognition has found little use in recognition of textual material due to the large dictionary and hence large word error rates. Mathifier constricts the speech recognition to math equations; it takes as input math formulas presented in the form of user speech and produces the equations in digital mathematical form. The smaller dictionary and the specific grammar structure of the math equations help restrict the problem of the recognition process. The program has room for smartly guessing words based on the grammar structure and thus resulting in a lower error rate and better recognition. Mathifier uses Sphinx, a modular speech recognition tool from CMU, and adapts it to recognize math equations and convert them into latex form in real time.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123643695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122310
Mohammad Javad Zavarei, MohammadReza Baghbanmanesh, E. Kargaran, H. Nabovati, A. Golmakani
In this paper, we propose a novel 1-bit full adder using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 28% improvement in power-delay product (PDP). Design of proposed full adder is based on improvement in the PDP and it provides full-swing output with good driving capability. Simulations demonstrate that full adder successfully operates in the PDP compared to similar circuits.
{"title":"Design of new full adder cell using hybrid-CMOS logic style","authors":"Mohammad Javad Zavarei, MohammadReza Baghbanmanesh, E. Kargaran, H. Nabovati, A. Golmakani","doi":"10.1109/ICECS.2011.6122310","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122310","url":null,"abstract":"In this paper, we propose a novel 1-bit full adder using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 28% improvement in power-delay product (PDP). Design of proposed full adder is based on improvement in the PDP and it provides full-swing output with good driving capability. Simulations demonstrate that full adder successfully operates in the PDP compared to similar circuits.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128898826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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