Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122213
Y. Abiven, F. Rivet, Y. Deval, D. Dallet, D. Belot, T. Taris
Multi-standard applications encounter several developments in the wireless systems. A single receiver is required for any standard of communication. Software Radio (SR) is an illustration of this concept. This paper presents a design methodology to ease the design of a flexible RF receiver based on an analog discrete time Fast Fourier Transform (FFT). A proposed architecture named SASP (Sampled Analog Signal Processor) targets the previously exposed concept for wireless constraints. The FFT algorithm brings an analog weighting unit which is the most power hungry part in such an analog discrete time processor.
{"title":"A low-power 2 GHz discrete time weighting system dedicated to Sampled Analog Signal Processing","authors":"Y. Abiven, F. Rivet, Y. Deval, D. Dallet, D. Belot, T. Taris","doi":"10.1109/ICECS.2011.6122213","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122213","url":null,"abstract":"Multi-standard applications encounter several developments in the wireless systems. A single receiver is required for any standard of communication. Software Radio (SR) is an illustration of this concept. This paper presents a design methodology to ease the design of a flexible RF receiver based on an analog discrete time Fast Fourier Transform (FFT). A proposed architecture named SASP (Sampled Analog Signal Processor) targets the previously exposed concept for wireless constraints. The FFT algorithm brings an analog weighting unit which is the most power hungry part in such an analog discrete time processor.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117274878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122343
L. Mohjazi, M. Al-Qutayri, H. Barada, K. Poon
Self-optimization of coverage is an essential element for successful deployment of enterprise femtocells. This paper evaluates the performance of genetic algorithm, particle swarm and simulated annealing heuristic techniques to solve a multi-objective coverage optimization problem when a number of femtocells are deployed to jointly provide indoor coverage. This paper demonstrates the different behaviors of the proposed algorithms. The results show that genetic algorithm and particle swarm have a higher potential of solving the problem compared to simulated annealing. This is due to their faster convergence time which is an important parameter for dynamic update of femtocells.
{"title":"Performance evaluation of heuristic techniques for coverage optimization in femtocells","authors":"L. Mohjazi, M. Al-Qutayri, H. Barada, K. Poon","doi":"10.1109/ICECS.2011.6122343","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122343","url":null,"abstract":"Self-optimization of coverage is an essential element for successful deployment of enterprise femtocells. This paper evaluates the performance of genetic algorithm, particle swarm and simulated annealing heuristic techniques to solve a multi-objective coverage optimization problem when a number of femtocells are deployed to jointly provide indoor coverage. This paper demonstrates the different behaviors of the proposed algorithms. The results show that genetic algorithm and particle swarm have a higher potential of solving the problem compared to simulated annealing. This is due to their faster convergence time which is an important parameter for dynamic update of femtocells.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116258301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For a conventional SRAM, bit-lines dissipate the largest part of power consumption, since they are long lines with parasitical capacitance. Furthermore, the bit-lines consume more power in write cycle than in read cycle. A new charge-recycling method is proposed to reduce bit-line power consumption. The proposed SRAM pre-charge the bit-lines to VDD or GND respectively, they share the charge of adjacent bit-lines in write cycle. This is different from the former charge-recycling technique, because it does not need the additional voltage supply except VDD. SRAM cells also dissipate a lot of leakage power consumption in inactive cycle. The proposed SRAM uses non uniform cell method to reduce gate leakage. In this paper, a 64kb (4k∗16bits) 1-port SRAM is implemented with 100nm CMOS technology, the simulation results show that it reduces 32.9% leakage for SRAM cell in inactive mode, and 22% total power consumption to the conventional SRAM.
{"title":"A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme","authors":"Xu Wang, Jianfei Jiang, Zhigang Mao, Bingjing Ge, Xing-long Zhao","doi":"10.1109/ICECS.2011.6122329","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122329","url":null,"abstract":"For a conventional SRAM, bit-lines dissipate the largest part of power consumption, since they are long lines with parasitical capacitance. Furthermore, the bit-lines consume more power in write cycle than in read cycle. A new charge-recycling method is proposed to reduce bit-line power consumption. The proposed SRAM pre-charge the bit-lines to VDD or GND respectively, they share the charge of adjacent bit-lines in write cycle. This is different from the former charge-recycling technique, because it does not need the additional voltage supply except VDD. SRAM cells also dissipate a lot of leakage power consumption in inactive cycle. The proposed SRAM uses non uniform cell method to reduce gate leakage. In this paper, a 64kb (4k∗16bits) 1-port SRAM is implemented with 100nm CMOS technology, the simulation results show that it reduces 32.9% leakage for SRAM cell in inactive mode, and 22% total power consumption to the conventional SRAM.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114992982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122347
Masoud Yavari, S. Naseh
The effect of the ground bond-wire inductance on the performance of class-E power amplifiers is analyzed and investigated. It is shown that for a given supply voltage and output power, this inductance decreases the value of the series excessive reactance and the voltage stress on the active device. The simulation results of a quasi-ideal circuit and a CMOS circuit in presence of a typical ground bond-wire inductance of 1 nH are presented to validate the analysis.
{"title":"The effect of ground bond-wire on the performance of CMOS class-E power amplifiers","authors":"Masoud Yavari, S. Naseh","doi":"10.1109/ICECS.2011.6122347","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122347","url":null,"abstract":"The effect of the ground bond-wire inductance on the performance of class-E power amplifiers is analyzed and investigated. It is shown that for a given supply voltage and output power, this inductance decreases the value of the series excessive reactance and the voltage stress on the active device. The simulation results of a quasi-ideal circuit and a CMOS circuit in presence of a typical ground bond-wire inductance of 1 nH are presented to validate the analysis.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125024779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122324
Y. A. Dama, A. Hussaini, R. Abd‐Alhameed, S. R. Jones, N. McEwan, T. Sadeghpour, Jonathan Rodriguez
The scattering parameter formulation for the envelope correlation in an (N, N) MIMO antenna array has been modified to take the intrinsic antenna power losses into account. This method of calculation provides a major simplification over the use of antenna radiation field patterns. Its accuracy is illustrated in three examples, which also show that the locations of the correlation minima are sensitive to the intrinsic losses.
{"title":"Envelope correlation formula for (N, N) MIMO antenna array including power losses","authors":"Y. A. Dama, A. Hussaini, R. Abd‐Alhameed, S. R. Jones, N. McEwan, T. Sadeghpour, Jonathan Rodriguez","doi":"10.1109/ICECS.2011.6122324","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122324","url":null,"abstract":"The scattering parameter formulation for the envelope correlation in an (N, N) MIMO antenna array has been modified to take the intrinsic antenna power losses into account. This method of calculation provides a major simplification over the use of antenna radiation field patterns. Its accuracy is illustrated in three examples, which also show that the locations of the correlation minima are sensitive to the intrinsic losses.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122984286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122273
Salim N. Batlouni, Hala S. Karaki, F. Zaraket, F. Karameh
Speech recognition has become widely used across many applications. Telephone systems can route a phone call based on what the caller says, control systems can respond to actions said by the controller, and mobile phones can recognize the speech of a contact's name and call the respective contact directly. However, speech recognition has found little use in recognition of textual material due to the large dictionary and hence large word error rates. Mathifier constricts the speech recognition to math equations; it takes as input math formulas presented in the form of user speech and produces the equations in digital mathematical form. The smaller dictionary and the specific grammar structure of the math equations help restrict the problem of the recognition process. The program has room for smartly guessing words based on the grammar structure and thus resulting in a lower error rate and better recognition. Mathifier uses Sphinx, a modular speech recognition tool from CMU, and adapts it to recognize math equations and convert them into latex form in real time.
{"title":"Mathifier — Speech recognition of math equations","authors":"Salim N. Batlouni, Hala S. Karaki, F. Zaraket, F. Karameh","doi":"10.1109/ICECS.2011.6122273","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122273","url":null,"abstract":"Speech recognition has become widely used across many applications. Telephone systems can route a phone call based on what the caller says, control systems can respond to actions said by the controller, and mobile phones can recognize the speech of a contact's name and call the respective contact directly. However, speech recognition has found little use in recognition of textual material due to the large dictionary and hence large word error rates. Mathifier constricts the speech recognition to math equations; it takes as input math formulas presented in the form of user speech and produces the equations in digital mathematical form. The smaller dictionary and the specific grammar structure of the math equations help restrict the problem of the recognition process. The program has room for smartly guessing words based on the grammar structure and thus resulting in a lower error rate and better recognition. Mathifier uses Sphinx, a modular speech recognition tool from CMU, and adapts it to recognize math equations and convert them into latex form in real time.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123643695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122266
K. Dev, V. Vivek, B. Hadimioglu, Y. Massoud
In this paper, we present an analytical modeling technique for circularly symmetric piezoelectric transducers. We also present the design of a flat/piston transducer that can generate unique acoustic wave patterns, having both converging and vortexing effects. The converging effect is generated by designing the transducer electrodes in the shapes of circular rings using Fresnel formula and exciting it with an RF signal of resonant frequency. The vortexing effect is achieved by cutting the rings to different sector angles: 90°, 180° and 270°. We use the analytical model to simulate the performance of these transducers.
{"title":"Analytical modeling and design of ring shaped piezoelectric transducers","authors":"K. Dev, V. Vivek, B. Hadimioglu, Y. Massoud","doi":"10.1109/ICECS.2011.6122266","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122266","url":null,"abstract":"In this paper, we present an analytical modeling technique for circularly symmetric piezoelectric transducers. We also present the design of a flat/piston transducer that can generate unique acoustic wave patterns, having both converging and vortexing effects. The converging effect is generated by designing the transducer electrodes in the shapes of circular rings using Fresnel formula and exciting it with an RF signal of resonant frequency. The vortexing effect is achieved by cutting the rings to different sector angles: 90°, 180° and 270°. We use the analytical model to simulate the performance of these transducers.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121416764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122375
Emilio Wuerges, R. S. Oliveira, L. Santos
Efficient embedded computing requires extended compiler awareness of the underlying hardware platform: execution time and energy consumption estimates should guide optimization. Conventional compilers employ rough (energy-unaware) estimates for fast decision making. Real-time compilers quickly determine bounds for WCET, but ignore energy. Embedded compilers accurately estimate average time/energy but require time-consuming profiling. We propose a novel estimation method based on energy-aware Abstract Interpretation from cache configuration and target technology. Our estimates exhibit derivatives that are as accurate as those obtained by profiling, but are computed at least 1000 times faster, being suitable for driving embedded code optimizations through iterative improvement.
{"title":"Fast estimation of memory consumption for energy-efficient compilers","authors":"Emilio Wuerges, R. S. Oliveira, L. Santos","doi":"10.1109/ICECS.2011.6122375","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122375","url":null,"abstract":"Efficient embedded computing requires extended compiler awareness of the underlying hardware platform: execution time and energy consumption estimates should guide optimization. Conventional compilers employ rough (energy-unaware) estimates for fast decision making. Real-time compilers quickly determine bounds for WCET, but ignore energy. Embedded compilers accurately estimate average time/energy but require time-consuming profiling. We propose a novel estimation method based on energy-aware Abstract Interpretation from cache configuration and target technology. Our estimates exhibit derivatives that are as accurate as those obtained by profiling, but are computed at least 1000 times faster, being suitable for driving embedded code optimizations through iterative improvement.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126208438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122374
F. Toufexis, A. Papanikolaou, D. Soudris, G. Stamoulis, S. Bantas
In this work, the impact of across-chip temperature and power supply voltage variations, on performance predictions in 3D ICs, is investigated. To make this possible, a novel design flow is proposed to perform design exploration of 3D ICs. Power supply voltage and thermal variations are modeled, to allow accurate PPA (power, performance and area) predictions. Using the main parts of this design flow, in a system comprising hundreds of million gates, complicated mechanisms are shown to determine the performance of the system. With increasing number of dies, timing is shown to exhibit 4 distinct regions, where either temperature or voltage drop is the dominant limiting factor. Power consumption does not scale monotonically with increasing die number. As a consequence, optimum system performance is in no way achieved by minimizing temperature and voltage drop, as is assumed in the literature so far. The across-chip temperature and power supply voltage variations are finally shown to cause on average 40% increase in timing and 53% decrease in power consumption, compared to the assumption of nominal conditions.
{"title":"Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm","authors":"F. Toufexis, A. Papanikolaou, D. Soudris, G. Stamoulis, S. Bantas","doi":"10.1109/ICECS.2011.6122374","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122374","url":null,"abstract":"In this work, the impact of across-chip temperature and power supply voltage variations, on performance predictions in 3D ICs, is investigated. To make this possible, a novel design flow is proposed to perform design exploration of 3D ICs. Power supply voltage and thermal variations are modeled, to allow accurate PPA (power, performance and area) predictions. Using the main parts of this design flow, in a system comprising hundreds of million gates, complicated mechanisms are shown to determine the performance of the system. With increasing number of dies, timing is shown to exhibit 4 distinct regions, where either temperature or voltage drop is the dominant limiting factor. Power consumption does not scale monotonically with increasing die number. As a consequence, optimum system performance is in no way achieved by minimizing temperature and voltage drop, as is assumed in the literature so far. The across-chip temperature and power supply voltage variations are finally shown to cause on average 40% increase in timing and 53% decrease in power consumption, compared to the assumption of nominal conditions.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130135551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122267
S. Boukhenous, M. Attari
This paper highlights the design of a low cost sensing system for the study of foot reaction stress recovering. For instance, measurements are made on Freeman platform for ankle rehabilitation sessions. The system is based on the design of a sensing element and to set it onto a flexible material as a foot shape. The sensor element is based on a Hall Effect device coupled with a magnet in a typical elastic polymer material. The sensors are mounted on a printed circuit board and recovered with a hard polymer layer in order to obtain a uniform distribution of strains. The output signal of each sensing element is carried out to an instrumentation amplifier for adjusting the level of signals and settings. First calibration was performed for the study of the polymer material and then for the mounted sensor element in order to show the feasibility of such stress sensing. After calibration procedure, a dynamic measurement in real environment has been carried out with the instrument bonded onto a Freeman platform.
{"title":"A low cost sensing system for foot stress recovering on a Freeman platform","authors":"S. Boukhenous, M. Attari","doi":"10.1109/ICECS.2011.6122267","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122267","url":null,"abstract":"This paper highlights the design of a low cost sensing system for the study of foot reaction stress recovering. For instance, measurements are made on Freeman platform for ankle rehabilitation sessions. The system is based on the design of a sensing element and to set it onto a flexible material as a foot shape. The sensor element is based on a Hall Effect device coupled with a magnet in a typical elastic polymer material. The sensors are mounted on a printed circuit board and recovered with a hard polymer layer in order to obtain a uniform distribution of strains. The output signal of each sensing element is carried out to an instrumentation amplifier for adjusting the level of signals and settings. First calibration was performed for the study of the polymer material and then for the mounted sensor element in order to show the feasibility of such stress sensing. After calibration procedure, a dynamic measurement in real environment has been carried out with the instrument bonded onto a Freeman platform.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130179569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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