Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122216
H. Daoud, S. B. Salem, S. Zouari, M. Loulou
This paper presents a design methodology for low-distortions (feed-forward) Delta-Sigma (ΔΣ) modulators topologies used in next generations wireless applications. Thus, optimized folded cascode OTA and telescopic OTA gain-boosting are selected to implement the switched capacitor (SC) integrator. First, a second order ΔΣ modulator is implemented for 2MHz bandwidth. Second, a 2–2 cascaded ΔΣ modulator is designed for 2MHz and 10MHz bandwidths in order to improve the modulator performances. These modulators are implemented using system-level simulations as well as device-level simulations implemented with SC circuits in AMS 0.35μm CMOS process. Device-level simulations results indicate that the 2nd and the 2–2 cascaded ΔΣ modulators achieve respectively SNRs of 43dB and 38dB over bandwidths of 2MHz and 10MHz with over-sampling ratios 16 and 8.
{"title":"Feed-forward ΔΣ modulators topologies design for broadband communications applications","authors":"H. Daoud, S. B. Salem, S. Zouari, M. Loulou","doi":"10.1109/ICECS.2011.6122216","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122216","url":null,"abstract":"This paper presents a design methodology for low-distortions (feed-forward) Delta-Sigma (ΔΣ) modulators topologies used in next generations wireless applications. Thus, optimized folded cascode OTA and telescopic OTA gain-boosting are selected to implement the switched capacitor (SC) integrator. First, a second order ΔΣ modulator is implemented for 2MHz bandwidth. Second, a 2–2 cascaded ΔΣ modulator is designed for 2MHz and 10MHz bandwidths in order to improve the modulator performances. These modulators are implemented using system-level simulations as well as device-level simulations implemented with SC circuits in AMS 0.35μm CMOS process. Device-level simulations results indicate that the 2nd and the 2–2 cascaded ΔΣ modulators achieve respectively SNRs of 43dB and 38dB over bandwidths of 2MHz and 10MHz with over-sampling ratios 16 and 8.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132345204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122274
Manal Jalloul, M. Baydoun, M. A. Al-Alaoui
Image registration is the process of matching different images whether 2D or 3D of certain similar or common properties for different purposes. This work addresses this field using a Gauss-Newton optimization approach. The problem is basically formulated as minimizing a cost function that is then solved by a backtracking line search. Since this is considered as a demanding problem especially for larger data, this paper presents the solution using the CUDA GPU architecture provided by Nvidia [1] in order to achieve better performance and reduce timing through parallelism.
{"title":"Gauss-Newton image registration with CUDA","authors":"Manal Jalloul, M. Baydoun, M. A. Al-Alaoui","doi":"10.1109/ICECS.2011.6122274","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122274","url":null,"abstract":"Image registration is the process of matching different images whether 2D or 3D of certain similar or common properties for different purposes. This work addresses this field using a Gauss-Newton optimization approach. The problem is basically formulated as minimizing a cost function that is then solved by a backtracking line search. Since this is considered as a demanding problem especially for larger data, this paper presents the solution using the CUDA GPU architecture provided by Nvidia [1] in order to achieve better performance and reduce timing through parallelism.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132351895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122221
M. Hofstätter, M. Litzenberger, D. Matolin, C. Posch
This paper presents a hardware implementation for high-speed, event-based data processing. A full-custom Address-Event (AER) processing system (GAEP) features a 10ns-resolution 33M/5.125M events·s−1 peak/sustained event rate sensor data interface for precision time-stamping of asynchronous sensor data and implements hardware-accelerated event pre-processing including rate dependent IRQ generation and address masking for ROI/RONI. The pre-processing functions are implemented in dedicated hardware and operate without loading the actual processor device, a SPARC-compatible general-purpose micro-processor. The complete SoC is implemented in 0.18μm standard CMOS technology. We present a camera system comprising the AER processor and a bio-inspired dynamic vision sensor in an exemplary high-speed vision application related to shape detection / object recognition. Relevant details of the system architecture and performance results characterizing the vision system in a real-world machine vision application are presented.
{"title":"Hardware-accelerated address-event processing for high-speed visual object recognition","authors":"M. Hofstätter, M. Litzenberger, D. Matolin, C. Posch","doi":"10.1109/ICECS.2011.6122221","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122221","url":null,"abstract":"This paper presents a hardware implementation for high-speed, event-based data processing. A full-custom Address-Event (AER) processing system (GAEP) features a 10ns-resolution 33M/5.125M events·s−1 peak/sustained event rate sensor data interface for precision time-stamping of asynchronous sensor data and implements hardware-accelerated event pre-processing including rate dependent IRQ generation and address masking for ROI/RONI. The pre-processing functions are implemented in dedicated hardware and operate without loading the actual processor device, a SPARC-compatible general-purpose micro-processor. The complete SoC is implemented in 0.18μm standard CMOS technology. We present a camera system comprising the AER processor and a bio-inspired dynamic vision sensor in an exemplary high-speed vision application related to shape detection / object recognition. Relevant details of the system architecture and performance results characterizing the vision system in a real-world machine vision application are presented.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132475581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122234
S. Sultana, K. Radecka
In this paper we present a novel reversible implementation of a square-root circuit with an array structure. In scientific computations such as numerical analysis, computer graphics, complex number computations, square root is an important operation. In classical irreversible arena we find different realizations of square root circuit. Since reversible circuit is emerging as an alternative to classical circuit, here we introduce a novel reversible realization of this operation. As a basic module, we propose a reversible controlled adder/subtractor (RCAS) block based on 2's Complement computation. In our design we use an array of such RCAS blocks which perform addition or subtraction based on the result generated from digit-by-digit square root operation. To our best knowledge this is the first methodical approach for implementing reversible square root circuit. The new structure of the circuit and different parameters — number of gates, garbage bits and quantum cost for n-bit realization is presented here.
{"title":"Reversible implementation of square-root circuit","authors":"S. Sultana, K. Radecka","doi":"10.1109/ICECS.2011.6122234","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122234","url":null,"abstract":"In this paper we present a novel reversible implementation of a square-root circuit with an array structure. In scientific computations such as numerical analysis, computer graphics, complex number computations, square root is an important operation. In classical irreversible arena we find different realizations of square root circuit. Since reversible circuit is emerging as an alternative to classical circuit, here we introduce a novel reversible realization of this operation. As a basic module, we propose a reversible controlled adder/subtractor (RCAS) block based on 2's Complement computation. In our design we use an array of such RCAS blocks which perform addition or subtraction based on the result generated from digit-by-digit square root operation. To our best knowledge this is the first methodical approach for implementing reversible square root circuit. The new structure of the circuit and different parameters — number of gates, garbage bits and quantum cost for n-bit realization is presented here.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"465 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132185796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122366
J. Athow, C. Rozon, D. Al-Khalili, J. Langlois
This paper introduces a framework to develop and characterize digital circuits using Carbon Nanotube Field Effect Transistors (CNFET). We define a 4-step process that involves design capture, pre-processing, circuit simulation and results extraction and interpretation. The initial work leading to this framework involves the selection of appropriate CNFET model and model parameters, and determination of optimized substrate voltage. Through a set of custom-design automated scripts, various logic gates were simulated, data were compiled and characterization results were obtained. A complete approximate squarer circuit was also designed, implemented and characterized using the framework. To demonstrate the power of Carbon Nanotube technology, the same circuit was also implemented in 16 nm CMOS technology for comparison. An improvement by factor of 17× in PDP was achieved with CNT.
{"title":"A CNFET-based characterization framework for digital circuits","authors":"J. Athow, C. Rozon, D. Al-Khalili, J. Langlois","doi":"10.1109/ICECS.2011.6122366","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122366","url":null,"abstract":"This paper introduces a framework to develop and characterize digital circuits using Carbon Nanotube Field Effect Transistors (CNFET). We define a 4-step process that involves design capture, pre-processing, circuit simulation and results extraction and interpretation. The initial work leading to this framework involves the selection of appropriate CNFET model and model parameters, and determination of optimized substrate voltage. Through a set of custom-design automated scripts, various logic gates were simulated, data were compiled and characterization results were obtained. A complete approximate squarer circuit was also designed, implemented and characterized using the framework. To demonstrate the power of Carbon Nanotube technology, the same circuit was also implemented in 16 nm CMOS technology for comparison. An improvement by factor of 17× in PDP was achieved with CNT.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132731289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122359
Céline Azar, S. Chevobbe, Yves Lhuillier, J. Diguet
The number of processors integrated in embedded platforms is expected to grow and reach thousands of cores in the near future. Manycore architectures gained a large interest over the years but the problem remains in scaling the control fabric and the interconnection network. We present in this paper CEDAR, a Configurable Embedded Distributed ARchitecture, and its adaptive routing strategy based on ACO (Ant Colony Optimization). CEDAR offers a high degree of flexibility and can handle any interconnection topology. Routing paths for remote data transfers are defined at runtime and allow a homogeneous distribution of traffic, avoiding deadlocks and contentions. We show that flexibility generates little overhead for exploring paths, which decreases for large amounts of data transfers. CEDAR is convenient for implementing irregular applications with high computational complexities.
{"title":"Dynamic routing strategy for embedded distributed architectures","authors":"Céline Azar, S. Chevobbe, Yves Lhuillier, J. Diguet","doi":"10.1109/ICECS.2011.6122359","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122359","url":null,"abstract":"The number of processors integrated in embedded platforms is expected to grow and reach thousands of cores in the near future. Manycore architectures gained a large interest over the years but the problem remains in scaling the control fabric and the interconnection network. We present in this paper CEDAR, a Configurable Embedded Distributed ARchitecture, and its adaptive routing strategy based on ACO (Ant Colony Optimization). CEDAR offers a high degree of flexibility and can handle any interconnection topology. Routing paths for remote data transfers are defined at runtime and allow a homogeneous distribution of traffic, avoiding deadlocks and contentions. We show that flexibility generates little overhead for exploring paths, which decreases for large amounts of data transfers. CEDAR is convenient for implementing irregular applications with high computational complexities.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115414909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122232
M. Karimi, H. Nabovati
A highly efficient fully integrated passive CMOS rectifier is proposed in this paper. Using four ultra low power and low voltage techniques with proper leakage current compensation technique, this new topology is very high efficient in wide input voltage range of both high voltages and low voltage advanced sub-micron applications simultaneously. In 0.5V AC input signal amplitude the power and voltage transmission efficiency are 58% and 62% respectively and these values reach to 68% and 72% in 0.8V. Unlike the recently proposed rectifiers, in this new rectifier, for wide range of AC input signal amplitude the power and voltage transmission efficiency are higher than 90%. New proposed rectifier is applicable for bio-implantable systems with high current demands. The new full-wave rectifier also simulated and optimized only for low voltage advanced sub-micron applications. This rectifier designed and simulated in 0.18μm standard CMOS technology.
{"title":"Design of a high efficient fully integrated CMOS rectifier using bootstrapped technique for sub-micron and wirelessly powered applications","authors":"M. Karimi, H. Nabovati","doi":"10.1109/ICECS.2011.6122232","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122232","url":null,"abstract":"A highly efficient fully integrated passive CMOS rectifier is proposed in this paper. Using four ultra low power and low voltage techniques with proper leakage current compensation technique, this new topology is very high efficient in wide input voltage range of both high voltages and low voltage advanced sub-micron applications simultaneously. In 0.5V AC input signal amplitude the power and voltage transmission efficiency are 58% and 62% respectively and these values reach to 68% and 72% in 0.8V. Unlike the recently proposed rectifiers, in this new rectifier, for wide range of AC input signal amplitude the power and voltage transmission efficiency are higher than 90%. New proposed rectifier is applicable for bio-implantable systems with high current demands. The new full-wave rectifier also simulated and optimized only for low voltage advanced sub-micron applications. This rectifier designed and simulated in 0.18μm standard CMOS technology.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117331638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122392
D. Galeano, M. Devy, J. Boizard, Wassim Filali
This paper presents an embedded architecture to implement in real time the Inverse Perspective Mapping (IPM) algorithm. The IPM algorithm allows a robot to detect obstacles under the hypothesis that the ground is flat, and the definition of an obstacle being anything that has a height above the ground. This algorithm is based on modifying the camera's angle of view to remove the perspective effect for the ground plane. The algorithm is implemented using co-design techniques and validated on a Stratix 3 FPGA. Several approaches proposed to develop an architecture devoted to this algorithm, are compared. Finally the proposed methodology can be extended to many cameras. The algorithm was fully tested for one camera and partially tested for 4 cameras.
{"title":"Real-time architecture on FPGA for obstacle detection using inverse perspective mapping","authors":"D. Galeano, M. Devy, J. Boizard, Wassim Filali","doi":"10.1109/ICECS.2011.6122392","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122392","url":null,"abstract":"This paper presents an embedded architecture to implement in real time the Inverse Perspective Mapping (IPM) algorithm. The IPM algorithm allows a robot to detect obstacles under the hypothesis that the ground is flat, and the definition of an obstacle being anything that has a height above the ground. This algorithm is based on modifying the camera's angle of view to remove the perspective effect for the ground plane. The algorithm is implemented using co-design techniques and validated on a Stratix 3 FPGA. Several approaches proposed to develop an architecture devoted to this algorithm, are compared. Finally the proposed methodology can be extended to many cameras. The algorithm was fully tested for one camera and partially tested for 4 cameras.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116845056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122215
Imene Ben Hafaiedh, S. Graf, Mohamad Jaber
The contribution of this paper is twofold. First we propose a high-level distributed and abstract model of the bus arbiter for multiprocessors. Our model provides a way for describing several existing arbitration protocols in a distributed and abstract manner so that their properties and performance could be easily compared and analyzed. Second, we propose to automatically verify deadlock freedom property of these protocols and to automatically generate their distributed implementation.
{"title":"Model-based design and distributed implementation of bus arbiter for multiprocessors","authors":"Imene Ben Hafaiedh, S. Graf, Mohamad Jaber","doi":"10.1109/ICECS.2011.6122215","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122215","url":null,"abstract":"The contribution of this paper is twofold. First we propose a high-level distributed and abstract model of the bus arbiter for multiprocessors. Our model provides a way for describing several existing arbitration protocols in a distributed and abstract manner so that their properties and performance could be easily compared and analyzed. Second, we propose to automatically verify deadlock freedom property of these protocols and to automatically generate their distributed implementation.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129430410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122276
Boram Lee, T. Higman
In this paper we present a novel, extremely simple constant transconductance (gm) technique for a rail-to-rail CMOS amplifier input stage. While the level shifting technique is one of the most popular conventional methods to achieve constant-gm ([1], [6]), in [1], two PMOS source followers, totalling 4 PMOS transistors, are used for level shifting. But in this paper, only one diode connected NMOS transistor is used and similar results to the conventional level shifting method have been achieved. Rail-to-rail input stage with 1.6V supply voltage is proposed and simulated by Cadence SPECTRE with TSMC 0.25-μm CMOS technology.
{"title":"Extremely simple constant-gm technique for low voltage rail-to-rail amplifier input stage","authors":"Boram Lee, T. Higman","doi":"10.1109/ICECS.2011.6122276","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122276","url":null,"abstract":"In this paper we present a novel, extremely simple constant transconductance (gm) technique for a rail-to-rail CMOS amplifier input stage. While the level shifting technique is one of the most popular conventional methods to achieve constant-gm ([1], [6]), in [1], two PMOS source followers, totalling 4 PMOS transistors, are used for level shifting. But in this paper, only one diode connected NMOS transistor is used and similar results to the conventional level shifting method have been achieved. Rail-to-rail input stage with 1.6V supply voltage is proposed and simulated by Cadence SPECTRE with TSMC 0.25-μm CMOS technology.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129516883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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