Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122344
A. Dehqan, K. Mafinezhad, E. Kargaran, H. Nabovati
A low voltage, low power dual band Low Noise Amplifier (LNA) is presented in this paper. By employing a forward body bias of the MOSFET and current reuse topology the LNA can be operated at reduced supply voltage and power consumption while maintaining high gain due to its topology. Using 0.18 um CMOS process the LNA is designed at 2.4 GHz and 5.2GHz with 13.1 dB and 14.2 dB voltage gains and 2.9dB and 2.6dB NF respectively with 0.7V supply voltage and 3mW power consumption.
本文介绍了一种低电压、低功耗的双频低噪声放大器。通过采用MOSFET的正向偏置和电流复用拓扑，LNA可以在降低电源电压和功耗的情况下工作，同时由于其拓扑结构而保持高增益。LNA采用0.18 um CMOS工艺设计，工作频率分别为2.4 GHz和5.2GHz，电压增益分别为13.1 dB和14.2 dB, NF增益分别为2.9dB和2.6dB，电源电压为0.7V，功耗为3mW。
{"title":"Design of low voltage low power dual-band LNA with forward body biasing technique","authors":"A. Dehqan, K. Mafinezhad, E. Kargaran, H. Nabovati","doi":"10.1109/ICECS.2011.6122344","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122344","url":null,"abstract":"A low voltage, low power dual band Low Noise Amplifier (LNA) is presented in this paper. By employing a forward body bias of the MOSFET and current reuse topology the LNA can be operated at reduced supply voltage and power consumption while maintaining high gain due to its topology. Using 0.18 um CMOS process the LNA is designed at 2.4 GHz and 5.2GHz with 13.1 dB and 14.2 dB voltage gains and 2.9dB and 2.6dB NF respectively with 0.7V supply voltage and 3mW power consumption.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"49 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131374277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122211
H. Zarghi, M. Sharifkhani, I. Gholampour
Among Sound Source Localization (SSL) methods, beamformed microphone arrays using Steering Response Power(SRP) has received significant attention. Yet, its application is stumbled by its computational complexity which cannot meet low-power/low-cost applications requirements. In this paper, Angular beamforming is presented. By applying this beamforming approach to the conventional SRP-PHAT one can find that the complexity of SRP-PHAT will decreased by two orders of magnitudes with a mere three fold reduction in resolution. The proposed method is implemented both on FPGA and 0.18um CMOS technology for a practical case.
{"title":"Implementation of a cost efficient SSL based on an Angular beamformer SRP-PHAT","authors":"H. Zarghi, M. Sharifkhani, I. Gholampour","doi":"10.1109/ICECS.2011.6122211","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122211","url":null,"abstract":"Among Sound Source Localization (SSL) methods, beamformed microphone arrays using Steering Response Power(SRP) has received significant attention. Yet, its application is stumbled by its computational complexity which cannot meet low-power/low-cost applications requirements. In this paper, Angular beamforming is presented. By applying this beamforming approach to the conventional SRP-PHAT one can find that the complexity of SRP-PHAT will decreased by two orders of magnitudes with a mere three fold reduction in resolution. The proposed method is implemented both on FPGA and 0.18um CMOS technology for a practical case.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130219744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122353
Rosario Arjona, I. Baturone
Since singular point extraction plays an important role in many fingerprint recognition systems, a digital circuit to implement such processing is presented herein. A novel algorithm that combines hardware efficiency with precision in the extraction of the points has been developed. The circuit architecture contains three main building blocks to carry out the three main stages of the algorithm: extraction of a partitioned directional image, smoothing, and searching for the patterns associated with singular points. The circuit processes the pixels in a serial way, following a pipeline scheme and executing in parallel several operations. The design flow employed has been supported by CAD tools. It starts with high-level descriptions and ends with the hardware prototyping into a FPGA from Xilinx.
{"title":"A digital circuit for extracting singular points from fingerprint images","authors":"Rosario Arjona, I. Baturone","doi":"10.1109/ICECS.2011.6122353","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122353","url":null,"abstract":"Since singular point extraction plays an important role in many fingerprint recognition systems, a digital circuit to implement such processing is presented herein. A novel algorithm that combines hardware efficiency with precision in the extraction of the points has been developed. The circuit architecture contains three main building blocks to carry out the three main stages of the algorithm: extraction of a partitioned directional image, smoothing, and searching for the patterns associated with singular points. The circuit processes the pixels in a serial way, following a pipeline scheme and executing in parallel several operations. The design flow employed has been supported by CAD tools. It starts with high-level descriptions and ends with the hardware prototyping into a FPGA from Xilinx.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128871047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122310
Mohammad Javad Zavarei, MohammadReza Baghbanmanesh, E. Kargaran, H. Nabovati, A. Golmakani
In this paper, we propose a novel 1-bit full adder using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 28% improvement in power-delay product (PDP). Design of proposed full adder is based on improvement in the PDP and it provides full-swing output with good driving capability. Simulations demonstrate that full adder successfully operates in the PDP compared to similar circuits.
{"title":"Design of new full adder cell using hybrid-CMOS logic style","authors":"Mohammad Javad Zavarei, MohammadReza Baghbanmanesh, E. Kargaran, H. Nabovati, A. Golmakani","doi":"10.1109/ICECS.2011.6122310","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122310","url":null,"abstract":"In this paper, we propose a novel 1-bit full adder using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 28% improvement in power-delay product (PDP). Design of proposed full adder is based on improvement in the PDP and it provides full-swing output with good driving capability. Simulations demonstrate that full adder successfully operates in the PDP compared to similar circuits.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128898826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122237
K. Manolopoulos, D. Reisis, V. Chouliaras
The current paper presents a multi-mode floating point multiplier operating efficiently with every precision format specified by the IEEE 754–2008 standard. The design performs one quadruple precision multiplication, or two double precision multiplications in parallel, or four single precision multiplications in parallel. The proposed multiplier is pipelined to achieve execution of one quadruple multiplication in 3 cycles and either two double precision operations in parallel or four single precision operations in parallel in only 2 cycles. The proposed design improves the throughput by a factor of two compared to a double precision multiplier and by four compared to a single precision multiplication. An example implementation on VLSI verifies the design and it achieves a maximum operating frequency of 505 MHz.
{"title":"An efficient multiple precision floating-point multiplier","authors":"K. Manolopoulos, D. Reisis, V. Chouliaras","doi":"10.1109/ICECS.2011.6122237","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122237","url":null,"abstract":"The current paper presents a multi-mode floating point multiplier operating efficiently with every precision format specified by the IEEE 754–2008 standard. The design performs one quadruple precision multiplication, or two double precision multiplications in parallel, or four single precision multiplications in parallel. The proposed multiplier is pipelined to achieve execution of one quadruple multiplication in 3 cycles and either two double precision operations in parallel or four single precision operations in parallel in only 2 cycles. The proposed design improves the throughput by a factor of two compared to a double precision multiplier and by four compared to a single precision multiplication. An example implementation on VLSI verifies the design and it achieves a maximum operating frequency of 505 MHz.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121662923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122385
K. Leboeuf, Iman Makaremi, R. Muscedere, M. Ahmadi
Plastics are used in a truly vast number of applications, and research is continously carried out to improve every aspect of the plastics industry. A recent study of laser transmission welding [1] required cross-sectional images of the weld's microstructure to be analyzed for the presence of pores, which are tiny bubbles that may form during the weld process. It is believed that the number and size of pores may be indicative of the weld strength [1]. The current state of the art for detecting these pores involves manually drawing a contour around each one; a laborious process given that a typical sample may have hundreds-to-thousands of pores. This paper presents a segmentation system for classifying the pixels of a microstructural image of a thermoplastic laser weld as either belonging to a pore or the background. The algorithm is robust in terms of dealing with noise from flbreglass strands, cloudy pores, and varying exposure time. On average, it is estimated that the proposed algorithm is able to correctly classify pores at a rate of approximately 90% without requiring any user intervention.
{"title":"Image processing technique for segmenting microstructural porosity of laser-welded thermoplastics","authors":"K. Leboeuf, Iman Makaremi, R. Muscedere, M. Ahmadi","doi":"10.1109/ICECS.2011.6122385","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122385","url":null,"abstract":"Plastics are used in a truly vast number of applications, and research is continously carried out to improve every aspect of the plastics industry. A recent study of laser transmission welding [1] required cross-sectional images of the weld's microstructure to be analyzed for the presence of pores, which are tiny bubbles that may form during the weld process. It is believed that the number and size of pores may be indicative of the weld strength [1]. The current state of the art for detecting these pores involves manually drawing a contour around each one; a laborious process given that a typical sample may have hundreds-to-thousands of pores. This paper presents a segmentation system for classifying the pixels of a microstructural image of a thermoplastic laser weld as either belonging to a pore or the background. The algorithm is robust in terms of dealing with noise from flbreglass strands, cloudy pores, and varying exposure time. On average, it is estimated that the proposed algorithm is able to correctly classify pores at a rate of approximately 90% without requiring any user intervention.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116356399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122306
Jin Fan
Many complex networks show community structure, i.e., fewer connections between different subgraphs than within each subgraph. In this paper, synchronization as an important dynamics of complex networks is studied. Inspired on the growth and preferential attachment, an evolving community network is proposed firstly. By exploiting the inner- and intercommunity connections, we find that weakening the community structure, that is, rewiring the inner-community connections into the inter-community ones, could efficiently improve the synchronizability of complex networks.
{"title":"Enhancing synchronizability of complex networks by community weakening","authors":"Jin Fan","doi":"10.1109/ICECS.2011.6122306","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122306","url":null,"abstract":"Many complex networks show community structure, i.e., fewer connections between different subgraphs than within each subgraph. In this paper, synchronization as an important dynamics of complex networks is studied. Inspired on the growth and preferential attachment, an evolving community network is proposed firstly. By exploiting the inner- and intercommunity connections, we find that weakening the community structure, that is, rewiring the inner-community connections into the inter-community ones, could efficiently improve the synchronizability of complex networks.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125468894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122369
V. Petrovic, G. Schoof, S. Montenegro
The middleware (MW) switch processor as a part of the new spacecraft area network (SCAN) system for internal satellite communication provides the data transfer between different components, sensors and devices. The new data transfer approach provides more reliable, cheaper and faster solution instead of current board computer based systems. The processor is currently in fabrication process in the 250 nm IHP technology. In this paper we are representing description of MW switch architecture, comparison between different architecture approaches and properties of the implemented MW Switch processor.
{"title":"Middleware switch ASIC implementation","authors":"V. Petrovic, G. Schoof, S. Montenegro","doi":"10.1109/ICECS.2011.6122369","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122369","url":null,"abstract":"The middleware (MW) switch processor as a part of the new spacecraft area network (SCAN) system for internal satellite communication provides the data transfer between different components, sensors and devices. The new data transfer approach provides more reliable, cheaper and faster solution instead of current board computer based systems. The processor is currently in fabrication process in the 250 nm IHP technology. In this paper we are representing description of MW switch architecture, comparison between different architecture approaches and properties of the implemented MW Switch processor.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127349406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122373
Ji Qiu, Xiang Gao, Yifei Jiang, Xu Xiao
ISS (Instruction Set Simulator) plays an important role in pre-silicon software development for ASIP. However, the speed of traditional simulation is too slow to effectively support full-scale software development. In this paper, we propose a hybrid simulation framework which further improves the previous simulation methods by aggressively utilizing the host machine resources. The utilization is achieved by categorizing instructions of ASIP application into two types, namely custom and basic instructions, via binary instrumentation. Then in a way of hybrid simulation, only custom instructions are simulated on the ISS and basic instructions are executed fast and natively on the host machine. We implement this framework for an industrial ASIP to validate our approach. Experimental results show that when the implemented ISS, namely GS-Sim, is applied to practical multimedia decoders, an average simulation speed up to 1058.5MIPS can be achieved, which is 34.7 times of the state-of-art dynamic binary translation simulator and is the fastest to the best of our knowledge.
{"title":"An ultra-fast hybrid simulation framework for ASIP","authors":"Ji Qiu, Xiang Gao, Yifei Jiang, Xu Xiao","doi":"10.1109/ICECS.2011.6122373","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122373","url":null,"abstract":"ISS (Instruction Set Simulator) plays an important role in pre-silicon software development for ASIP. However, the speed of traditional simulation is too slow to effectively support full-scale software development. In this paper, we propose a hybrid simulation framework which further improves the previous simulation methods by aggressively utilizing the host machine resources. The utilization is achieved by categorizing instructions of ASIP application into two types, namely custom and basic instructions, via binary instrumentation. Then in a way of hybrid simulation, only custom instructions are simulated on the ISS and basic instructions are executed fast and natively on the host machine. We implement this framework for an industrial ASIP to validate our approach. Experimental results show that when the implemented ISS, namely GS-Sim, is applied to practical multimedia decoders, an average simulation speed up to 1058.5MIPS can be achieved, which is 34.7 times of the state-of-art dynamic binary translation simulator and is the fastest to the best of our knowledge.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122210832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122330
S. Esmaeeli, M. Hosseini, B. Vahdat, B. Rashidian
The vulnerability of microprocessors to soft errors is increasing due to continuous shrinking in fabrication process. Recent studies show that 1–5% of the SEUs (single event upset) can cause MBUs (multiple bit upsets). The probability of MBU generation due to SEU is increasing because of the reduction in minimum energy required to flip a memory bit in modern technologies. Register file is the most sensitive component in a microprocessor. In this paper, we present an innovative way to protect registers in a 64-bit register file for a RISC processor using extended Hamming (8, 4) code (SEC-DED code) and narrow-width values. A narrow-width value can be represented by half number of bits of the register width. Two additional bits for each data register have been used to store the information for a narrow-width value. Each 64-bit data in register file has its unique 64-bit extended Hamming code that is stored in another register file in a bit-interleaved manner. Two copies of narrow-width values can be stored in one register and each copy has its unique extended Hamming code in other register file. Proposed method has been tested using fault injection simulation with SPEC2000 benchmarks. Error probability of a word that stores generated values for register file in SPEC2000 benchmarks and is protected with proposed method is less than the error probability of the same word that is protected with TMR or various extended Hamming codes. The implementation on a Xilinx Virtex-4 FPGA shows that the area overhead of a register file with 64-bit wide and more than 64-word entry that is protected with proposed method is less than the area overhead of the same register file that is protected with TMR. Error detection and correction is performed in parallel with execute stage to prevent performance degradation. More than 99% of errors in adjacent 32 bits in data or extended Hamming code registers can be corrected with the proposed method. Presented method employs pure combinational logics and can be used for 16-bit and 32-bit register files too.
{"title":"A multi-bit error tolerant register file for a high reliable embedded processor","authors":"S. Esmaeeli, M. Hosseini, B. Vahdat, B. Rashidian","doi":"10.1109/ICECS.2011.6122330","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122330","url":null,"abstract":"The vulnerability of microprocessors to soft errors is increasing due to continuous shrinking in fabrication process. Recent studies show that 1–5% of the SEUs (single event upset) can cause MBUs (multiple bit upsets). The probability of MBU generation due to SEU is increasing because of the reduction in minimum energy required to flip a memory bit in modern technologies. Register file is the most sensitive component in a microprocessor. In this paper, we present an innovative way to protect registers in a 64-bit register file for a RISC processor using extended Hamming (8, 4) code (SEC-DED code) and narrow-width values. A narrow-width value can be represented by half number of bits of the register width. Two additional bits for each data register have been used to store the information for a narrow-width value. Each 64-bit data in register file has its unique 64-bit extended Hamming code that is stored in another register file in a bit-interleaved manner. Two copies of narrow-width values can be stored in one register and each copy has its unique extended Hamming code in other register file. Proposed method has been tested using fault injection simulation with SPEC2000 benchmarks. Error probability of a word that stores generated values for register file in SPEC2000 benchmarks and is protected with proposed method is less than the error probability of the same word that is protected with TMR or various extended Hamming codes. The implementation on a Xilinx Virtex-4 FPGA shows that the area overhead of a register file with 64-bit wide and more than 64-word entry that is protected with proposed method is less than the area overhead of the same register file that is protected with TMR. Error detection and correction is performed in parallel with execute stage to prevent performance degradation. More than 99% of errors in adjacent 32 bits in data or extended Hamming code registers can be corrected with the proposed method. Presented method employs pure combinational logics and can be used for 16-bit and 32-bit register files too.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131674724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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