Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122267
S. Boukhenous, M. Attari
This paper highlights the design of a low cost sensing system for the study of foot reaction stress recovering. For instance, measurements are made on Freeman platform for ankle rehabilitation sessions. The system is based on the design of a sensing element and to set it onto a flexible material as a foot shape. The sensor element is based on a Hall Effect device coupled with a magnet in a typical elastic polymer material. The sensors are mounted on a printed circuit board and recovered with a hard polymer layer in order to obtain a uniform distribution of strains. The output signal of each sensing element is carried out to an instrumentation amplifier for adjusting the level of signals and settings. First calibration was performed for the study of the polymer material and then for the mounted sensor element in order to show the feasibility of such stress sensing. After calibration procedure, a dynamic measurement in real environment has been carried out with the instrument bonded onto a Freeman platform.
{"title":"A low cost sensing system for foot stress recovering on a Freeman platform","authors":"S. Boukhenous, M. Attari","doi":"10.1109/ICECS.2011.6122267","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122267","url":null,"abstract":"This paper highlights the design of a low cost sensing system for the study of foot reaction stress recovering. For instance, measurements are made on Freeman platform for ankle rehabilitation sessions. The system is based on the design of a sensing element and to set it onto a flexible material as a foot shape. The sensor element is based on a Hall Effect device coupled with a magnet in a typical elastic polymer material. The sensors are mounted on a printed circuit board and recovered with a hard polymer layer in order to obtain a uniform distribution of strains. The output signal of each sensing element is carried out to an instrumentation amplifier for adjusting the level of signals and settings. First calibration was performed for the study of the polymer material and then for the mounted sensor element in order to show the feasibility of such stress sensing. After calibration procedure, a dynamic measurement in real environment has been carried out with the instrument bonded onto a Freeman platform.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130179569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122347
Masoud Yavari, S. Naseh
The effect of the ground bond-wire inductance on the performance of class-E power amplifiers is analyzed and investigated. It is shown that for a given supply voltage and output power, this inductance decreases the value of the series excessive reactance and the voltage stress on the active device. The simulation results of a quasi-ideal circuit and a CMOS circuit in presence of a typical ground bond-wire inductance of 1 nH are presented to validate the analysis.
{"title":"The effect of ground bond-wire on the performance of CMOS class-E power amplifiers","authors":"Masoud Yavari, S. Naseh","doi":"10.1109/ICECS.2011.6122347","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122347","url":null,"abstract":"The effect of the ground bond-wire inductance on the performance of class-E power amplifiers is analyzed and investigated. It is shown that for a given supply voltage and output power, this inductance decreases the value of the series excessive reactance and the voltage stress on the active device. The simulation results of a quasi-ideal circuit and a CMOS circuit in presence of a typical ground bond-wire inductance of 1 nH are presented to validate the analysis.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125024779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122306
Jin Fan
Many complex networks show community structure, i.e., fewer connections between different subgraphs than within each subgraph. In this paper, synchronization as an important dynamics of complex networks is studied. Inspired on the growth and preferential attachment, an evolving community network is proposed firstly. By exploiting the inner- and intercommunity connections, we find that weakening the community structure, that is, rewiring the inner-community connections into the inter-community ones, could efficiently improve the synchronizability of complex networks.
{"title":"Enhancing synchronizability of complex networks by community weakening","authors":"Jin Fan","doi":"10.1109/ICECS.2011.6122306","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122306","url":null,"abstract":"Many complex networks show community structure, i.e., fewer connections between different subgraphs than within each subgraph. In this paper, synchronization as an important dynamics of complex networks is studied. Inspired on the growth and preferential attachment, an evolving community network is proposed firstly. By exploiting the inner- and intercommunity connections, we find that weakening the community structure, that is, rewiring the inner-community connections into the inter-community ones, could efficiently improve the synchronizability of complex networks.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125468894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122353
Rosario Arjona, I. Baturone
Since singular point extraction plays an important role in many fingerprint recognition systems, a digital circuit to implement such processing is presented herein. A novel algorithm that combines hardware efficiency with precision in the extraction of the points has been developed. The circuit architecture contains three main building blocks to carry out the three main stages of the algorithm: extraction of a partitioned directional image, smoothing, and searching for the patterns associated with singular points. The circuit processes the pixels in a serial way, following a pipeline scheme and executing in parallel several operations. The design flow employed has been supported by CAD tools. It starts with high-level descriptions and ends with the hardware prototyping into a FPGA from Xilinx.
{"title":"A digital circuit for extracting singular points from fingerprint images","authors":"Rosario Arjona, I. Baturone","doi":"10.1109/ICECS.2011.6122353","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122353","url":null,"abstract":"Since singular point extraction plays an important role in many fingerprint recognition systems, a digital circuit to implement such processing is presented herein. A novel algorithm that combines hardware efficiency with precision in the extraction of the points has been developed. The circuit architecture contains three main building blocks to carry out the three main stages of the algorithm: extraction of a partitioned directional image, smoothing, and searching for the patterns associated with singular points. The circuit processes the pixels in a serial way, following a pipeline scheme and executing in parallel several operations. The design flow employed has been supported by CAD tools. It starts with high-level descriptions and ends with the hardware prototyping into a FPGA from Xilinx.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128871047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122369
V. Petrovic, G. Schoof, S. Montenegro
The middleware (MW) switch processor as a part of the new spacecraft area network (SCAN) system for internal satellite communication provides the data transfer between different components, sensors and devices. The new data transfer approach provides more reliable, cheaper and faster solution instead of current board computer based systems. The processor is currently in fabrication process in the 250 nm IHP technology. In this paper we are representing description of MW switch architecture, comparison between different architecture approaches and properties of the implemented MW Switch processor.
{"title":"Middleware switch ASIC implementation","authors":"V. Petrovic, G. Schoof, S. Montenegro","doi":"10.1109/ICECS.2011.6122369","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122369","url":null,"abstract":"The middleware (MW) switch processor as a part of the new spacecraft area network (SCAN) system for internal satellite communication provides the data transfer between different components, sensors and devices. The new data transfer approach provides more reliable, cheaper and faster solution instead of current board computer based systems. The processor is currently in fabrication process in the 250 nm IHP technology. In this paper we are representing description of MW switch architecture, comparison between different architecture approaches and properties of the implemented MW Switch processor.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127349406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122266
K. Dev, V. Vivek, B. Hadimioglu, Y. Massoud
In this paper, we present an analytical modeling technique for circularly symmetric piezoelectric transducers. We also present the design of a flat/piston transducer that can generate unique acoustic wave patterns, having both converging and vortexing effects. The converging effect is generated by designing the transducer electrodes in the shapes of circular rings using Fresnel formula and exciting it with an RF signal of resonant frequency. The vortexing effect is achieved by cutting the rings to different sector angles: 90°, 180° and 270°. We use the analytical model to simulate the performance of these transducers.
{"title":"Analytical modeling and design of ring shaped piezoelectric transducers","authors":"K. Dev, V. Vivek, B. Hadimioglu, Y. Massoud","doi":"10.1109/ICECS.2011.6122266","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122266","url":null,"abstract":"In this paper, we present an analytical modeling technique for circularly symmetric piezoelectric transducers. We also present the design of a flat/piston transducer that can generate unique acoustic wave patterns, having both converging and vortexing effects. The converging effect is generated by designing the transducer electrodes in the shapes of circular rings using Fresnel formula and exciting it with an RF signal of resonant frequency. The vortexing effect is achieved by cutting the rings to different sector angles: 90°, 180° and 270°. We use the analytical model to simulate the performance of these transducers.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121416764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122375
Emilio Wuerges, R. S. Oliveira, L. Santos
Efficient embedded computing requires extended compiler awareness of the underlying hardware platform: execution time and energy consumption estimates should guide optimization. Conventional compilers employ rough (energy-unaware) estimates for fast decision making. Real-time compilers quickly determine bounds for WCET, but ignore energy. Embedded compilers accurately estimate average time/energy but require time-consuming profiling. We propose a novel estimation method based on energy-aware Abstract Interpretation from cache configuration and target technology. Our estimates exhibit derivatives that are as accurate as those obtained by profiling, but are computed at least 1000 times faster, being suitable for driving embedded code optimizations through iterative improvement.
{"title":"Fast estimation of memory consumption for energy-efficient compilers","authors":"Emilio Wuerges, R. S. Oliveira, L. Santos","doi":"10.1109/ICECS.2011.6122375","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122375","url":null,"abstract":"Efficient embedded computing requires extended compiler awareness of the underlying hardware platform: execution time and energy consumption estimates should guide optimization. Conventional compilers employ rough (energy-unaware) estimates for fast decision making. Real-time compilers quickly determine bounds for WCET, but ignore energy. Embedded compilers accurately estimate average time/energy but require time-consuming profiling. We propose a novel estimation method based on energy-aware Abstract Interpretation from cache configuration and target technology. Our estimates exhibit derivatives that are as accurate as those obtained by profiling, but are computed at least 1000 times faster, being suitable for driving embedded code optimizations through iterative improvement.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126208438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122324
Y. A. Dama, A. Hussaini, R. Abd‐Alhameed, S. R. Jones, N. McEwan, T. Sadeghpour, Jonathan Rodriguez
The scattering parameter formulation for the envelope correlation in an (N, N) MIMO antenna array has been modified to take the intrinsic antenna power losses into account. This method of calculation provides a major simplification over the use of antenna radiation field patterns. Its accuracy is illustrated in three examples, which also show that the locations of the correlation minima are sensitive to the intrinsic losses.
{"title":"Envelope correlation formula for (N, N) MIMO antenna array including power losses","authors":"Y. A. Dama, A. Hussaini, R. Abd‐Alhameed, S. R. Jones, N. McEwan, T. Sadeghpour, Jonathan Rodriguez","doi":"10.1109/ICECS.2011.6122324","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122324","url":null,"abstract":"The scattering parameter formulation for the envelope correlation in an (N, N) MIMO antenna array has been modified to take the intrinsic antenna power losses into account. This method of calculation provides a major simplification over the use of antenna radiation field patterns. Its accuracy is illustrated in three examples, which also show that the locations of the correlation minima are sensitive to the intrinsic losses.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122984286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122211
H. Zarghi, M. Sharifkhani, I. Gholampour
Among Sound Source Localization (SSL) methods, beamformed microphone arrays using Steering Response Power(SRP) has received significant attention. Yet, its application is stumbled by its computational complexity which cannot meet low-power/low-cost applications requirements. In this paper, Angular beamforming is presented. By applying this beamforming approach to the conventional SRP-PHAT one can find that the complexity of SRP-PHAT will decreased by two orders of magnitudes with a mere three fold reduction in resolution. The proposed method is implemented both on FPGA and 0.18um CMOS technology for a practical case.
{"title":"Implementation of a cost efficient SSL based on an Angular beamformer SRP-PHAT","authors":"H. Zarghi, M. Sharifkhani, I. Gholampour","doi":"10.1109/ICECS.2011.6122211","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122211","url":null,"abstract":"Among Sound Source Localization (SSL) methods, beamformed microphone arrays using Steering Response Power(SRP) has received significant attention. Yet, its application is stumbled by its computational complexity which cannot meet low-power/low-cost applications requirements. In this paper, Angular beamforming is presented. By applying this beamforming approach to the conventional SRP-PHAT one can find that the complexity of SRP-PHAT will decreased by two orders of magnitudes with a mere three fold reduction in resolution. The proposed method is implemented both on FPGA and 0.18um CMOS technology for a practical case.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130219744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122374
F. Toufexis, A. Papanikolaou, D. Soudris, G. Stamoulis, S. Bantas
In this work, the impact of across-chip temperature and power supply voltage variations, on performance predictions in 3D ICs, is investigated. To make this possible, a novel design flow is proposed to perform design exploration of 3D ICs. Power supply voltage and thermal variations are modeled, to allow accurate PPA (power, performance and area) predictions. Using the main parts of this design flow, in a system comprising hundreds of million gates, complicated mechanisms are shown to determine the performance of the system. With increasing number of dies, timing is shown to exhibit 4 distinct regions, where either temperature or voltage drop is the dominant limiting factor. Power consumption does not scale monotonically with increasing die number. As a consequence, optimum system performance is in no way achieved by minimizing temperature and voltage drop, as is assumed in the literature so far. The across-chip temperature and power supply voltage variations are finally shown to cause on average 40% increase in timing and 53% decrease in power consumption, compared to the assumption of nominal conditions.
{"title":"Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm","authors":"F. Toufexis, A. Papanikolaou, D. Soudris, G. Stamoulis, S. Bantas","doi":"10.1109/ICECS.2011.6122374","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122374","url":null,"abstract":"In this work, the impact of across-chip temperature and power supply voltage variations, on performance predictions in 3D ICs, is investigated. To make this possible, a novel design flow is proposed to perform design exploration of 3D ICs. Power supply voltage and thermal variations are modeled, to allow accurate PPA (power, performance and area) predictions. Using the main parts of this design flow, in a system comprising hundreds of million gates, complicated mechanisms are shown to determine the performance of the system. With increasing number of dies, timing is shown to exhibit 4 distinct regions, where either temperature or voltage drop is the dominant limiting factor. Power consumption does not scale monotonically with increasing die number. As a consequence, optimum system performance is in no way achieved by minimizing temperature and voltage drop, as is assumed in the literature so far. The across-chip temperature and power supply voltage variations are finally shown to cause on average 40% increase in timing and 53% decrease in power consumption, compared to the assumption of nominal conditions.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130135551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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