Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122291
P. Possa, David Schaillie, C. Valderrama
One of the main challenges for embedded system designers is to find a tradeoff between performance and power consumption. In order to reach this goal, hardware accelerators have been used to offload specific tasks from the CPU, improving the global performance of the system and reducing its dynamic power consumption. Enabling the use of accelerators could become a tricky task for embedded system designers. This paper presents a complete acceleration design flow for embedded systems with an exploration of different interfaces between CPU and accelerator, analyzing their performances, resources overhead, power consumption, and implementation methods.
{"title":"FPGA-based hardware acceleration: A CPU/accelerator interface exploration","authors":"P. Possa, David Schaillie, C. Valderrama","doi":"10.1109/ICECS.2011.6122291","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122291","url":null,"abstract":"One of the main challenges for embedded system designers is to find a tradeoff between performance and power consumption. In order to reach this goal, hardware accelerators have been used to offload specific tasks from the CPU, improving the global performance of the system and reducing its dynamic power consumption. Enabling the use of accelerators could become a tricky task for embedded system designers. This paper presents a complete acceleration design flow for embedded systems with an exploration of different interfaces between CPU and accelerator, analyzing their performances, resources overhead, power consumption, and implementation methods.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128175130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122292
Todd E. Schmuland, M. Jamali, M. Longbrake, P. Buxa
This paper describes a software tool for simulating and generating fully parallel generic VHDL representations of Fast Fourier Transforms. A comparison between parallel-parallel and serial-parallel butterflies is performed with emphasis on maximizing speed and/or minimizing FPGA area. Comparisons of the software tool to other VHDL/Verilog generators, namely CoreGen and SPIRAL, are also explored.
{"title":"CAD tool for parameterized FPGA based FFT architectures","authors":"Todd E. Schmuland, M. Jamali, M. Longbrake, P. Buxa","doi":"10.1109/ICECS.2011.6122292","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122292","url":null,"abstract":"This paper describes a software tool for simulating and generating fully parallel generic VHDL representations of Fast Fourier Transforms. A comparison between parallel-parallel and serial-parallel butterflies is performed with emphasis on maximizing speed and/or minimizing FPGA area. Comparisons of the software tool to other VHDL/Verilog generators, namely CoreGen and SPIRAL, are also explored.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130397302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122239
S. V. Bussche, P. D. Wit, Elie Maricau, G. Gielen
Advanced CMOS technology introduces reliability challenges that are no longer fully resolved at the technology level. This paper studies the impact of transistor degradation at the circuit level. Particular attention is paid to the change in matching characteristics. This mismatch is critical for the performance of a lot of analog circuits such as current-steering DACs. A ‘design for reliability’ technique using higher-than-nominal supply voltage allows increased performance and lower area usage at the expense of increased degradation. A ‘Switching-Sequence Post Adjustment’ (SSPA) digital calibration method is used to reduce the area even more, but can also provide a ‘dynamic resequencing’, which ensures reliable operation of the circuit at all times. A 10-bit DAC is analysed using 32nm data. A degradation-induced accuracy decrease of 0.33 bit, of which 0.21 bit can be compensated using the SSPA algorithm, is observed, yielding a factor 25 area reduction.
{"title":"Impact analysis of stochastic transistor aging on current-steering DACs in 32nm CMOS","authors":"S. V. Bussche, P. D. Wit, Elie Maricau, G. Gielen","doi":"10.1109/ICECS.2011.6122239","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122239","url":null,"abstract":"Advanced CMOS technology introduces reliability challenges that are no longer fully resolved at the technology level. This paper studies the impact of transistor degradation at the circuit level. Particular attention is paid to the change in matching characteristics. This mismatch is critical for the performance of a lot of analog circuits such as current-steering DACs. A ‘design for reliability’ technique using higher-than-nominal supply voltage allows increased performance and lower area usage at the expense of increased degradation. A ‘Switching-Sequence Post Adjustment’ (SSPA) digital calibration method is used to reduce the area even more, but can also provide a ‘dynamic resequencing’, which ensures reliable operation of the circuit at all times. A 10-bit DAC is analysed using 32nm data. A degradation-induced accuracy decrease of 0.33 bit, of which 0.21 bit can be compensated using the SSPA algorithm, is observed, yielding a factor 25 area reduction.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129268090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122248
M. Asgari, Seyyed Hossein Pishgar Komleh, O. Hashemipour
A reliable low-distortion CMOS bootstrapped sampling switch is presented. Compared to conventional bootstrapped switch, this scheme achieves more reliability because the limits of proposed circuit are VDD+VTHn and −|VTHp|. The variation of equivalent conductance of this CMOS sampling switch through input signal is alleviated by a specific switch's voltage control. The proposed switch is realized with the half number of transistors compared to previously reported scheme which results more simplicity and less area. Simulations using a standard 0.18μm CMOS technology model show about 10dB improvements in both THD and SFDR while using it in a conventional fully-differential sample-and-hold circuit.
{"title":"A reliable full-swing low-distortion CMOS bootstrapped sampling switch","authors":"M. Asgari, Seyyed Hossein Pishgar Komleh, O. Hashemipour","doi":"10.1109/ICECS.2011.6122248","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122248","url":null,"abstract":"A reliable low-distortion CMOS bootstrapped sampling switch is presented. Compared to conventional bootstrapped switch, this scheme achieves more reliability because the limits of proposed circuit are VDD+VTHn and −|VTHp|. The variation of equivalent conductance of this CMOS sampling switch through input signal is alleviated by a specific switch's voltage control. The proposed switch is realized with the half number of transistors compared to previously reported scheme which results more simplicity and less area. Simulations using a standard 0.18μm CMOS technology model show about 10dB improvements in both THD and SFDR while using it in a conventional fully-differential sample-and-hold circuit.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123043767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122368
Susana Eiroa, I. Baturone
The use of Ring Oscillator PUFs to provide circuit authentication is analyzed in this paper. The limitations of the previously reported approach in terms of false rejection (due to high intra-die variations) and false acceptance (due to small inter-die variations) are discussed. These limitations are overcome by a new proposal that makes the authentication more robust against noise, temperature and power supply variations, without increasing considerably hardware complexity. All these issues are illustrated with experimental results obtained with FPGAs from Xilinx.
{"title":"Circuit authentication based on Ring-Oscillator PUFs","authors":"Susana Eiroa, I. Baturone","doi":"10.1109/ICECS.2011.6122368","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122368","url":null,"abstract":"The use of Ring Oscillator PUFs to provide circuit authentication is analyzed in this paper. The limitations of the previously reported approach in terms of false rejection (due to high intra-die variations) and false acceptance (due to small inter-die variations) are discussed. These limitations are overcome by a new proposal that makes the authentication more robust against noise, temperature and power supply variations, without increasing considerably hardware complexity. All these issues are illustrated with experimental results obtained with FPGAs from Xilinx.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114093471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122251
M. Hashemi, M. Sharifkhani, M. Gholami
A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of low-power techniques are proposed in various levels of abstraction. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum stage scaling factors, tail current and opamp transistor sizes. Simulations in 0.13um CMOS technology show that the ADC achieves 56.04dB signal-to-noise ratio (SNDR), 9.02 effective numbers of bits (ENOB) and INL/DNL of less than 1 LSB, while consuming only 3.9 mW from a 1-V power supply. The Figure-of-Merit (FOM) value is less than 0.19 pJ/Conversion.
{"title":"A low power 1-V 10-bit 40-MS/s pipeline ADC","authors":"M. Hashemi, M. Sharifkhani, M. Gholami","doi":"10.1109/ICECS.2011.6122251","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122251","url":null,"abstract":"A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of low-power techniques are proposed in various levels of abstraction. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum stage scaling factors, tail current and opamp transistor sizes. Simulations in 0.13um CMOS technology show that the ADC achieves 56.04dB signal-to-noise ratio (SNDR), 9.02 effective numbers of bits (ENOB) and INL/DNL of less than 1 LSB, while consuming only 3.9 mW from a 1-V power supply. The Figure-of-Merit (FOM) value is less than 0.19 pJ/Conversion.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115315503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122332
Eberle A. Rambo, Olav P. Henschel, L. Santos
Chip multiprocessing (CMP) changed the architectural landscape of PCs and servers and is now changing the way personal mobile devices are designed. CMP requires access to shared variables in private memories, leading to complex chains of interacting events that must offer a consistent view of shared memory. Checking if a memory system implements a specified memory consistency model (MCM) is a challenging verification problem. We propose a generator of multi-threading random-instruction sequences for MCM checking. It complies with an arbitrary MCM and can be used by most checkers. Its ability to provide full coverage was evaluated through 1200 test cases.
{"title":"Automatic generation of memory consistency tests for chip multiprocessing","authors":"Eberle A. Rambo, Olav P. Henschel, L. Santos","doi":"10.1109/ICECS.2011.6122332","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122332","url":null,"abstract":"Chip multiprocessing (CMP) changed the architectural landscape of PCs and servers and is now changing the way personal mobile devices are designed. CMP requires access to shared variables in private memories, leading to complex chains of interacting events that must offer a consistent view of shared memory. Checking if a memory system implements a specified memory consistency model (MCM) is a challenging verification problem. We propose a generator of multi-threading random-instruction sequences for MCM checking. It complies with an arbitrary MCM and can be used by most checkers. Its ability to provide full coverage was evaluated through 1200 test cases.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115624825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122253
M. Abbas, Takahiro J. Yamaguchi, Y. Furukawa, S. Komatsu, K. Asada
This paper presents a new technique to compensate the comparator delay dispersion caused by variable input overdrive. The technique is composed of three main blocks, namely, conventional comparator, fixed delay block and variable delay block. The variable delay block is controlled such that it implements the inverse overdrive-delay characteristics of the conventional comparator. Therefore, the overall delay dispersion of the technique is effectively reduced. The technique is implemented in 65nm technology. The measurement and simulation results show that the delay dispersion of the proposed technique is 10% of its counterpart in the conventional comparator. The active area of the technique 267.8μm2 and the measured power consumption is 273μW at 200MHz.
{"title":"Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology","authors":"M. Abbas, Takahiro J. Yamaguchi, Y. Furukawa, S. Komatsu, K. Asada","doi":"10.1109/ICECS.2011.6122253","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122253","url":null,"abstract":"This paper presents a new technique to compensate the comparator delay dispersion caused by variable input overdrive. The technique is composed of three main blocks, namely, conventional comparator, fixed delay block and variable delay block. The variable delay block is controlled such that it implements the inverse overdrive-delay characteristics of the conventional comparator. Therefore, the overall delay dispersion of the technique is effectively reduced. The technique is implemented in 65nm technology. The measurement and simulation results show that the delay dispersion of the proposed technique is 10% of its counterpart in the conventional comparator. The active area of the technique 267.8μm2 and the measured power consumption is 273μW at 200MHz.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122442137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122377
H. Zarrabi, A. Al-Khalili, Y. Savaria
Portable battery-powered embedded systems necessitate sustainable energy-aware computing. For energy-efficient realization of such systems, static and possibly dynamic optimizations need to be applied to both the hardware and software design abstraction layers. In this paper, models for estimating the energy consumption based on application “activity” are proposed. By “activity” we mean the rate at which the computing platform performs a set of predefined application functions; and managing them aims at extending battery life. The proposed models can be used for both static and/or dynamic (on the fly) design/exploration of such systems. In order to validate the models, a generic low duty-cycle ZigBee® Wireless Sensor Network (WSN) application has been considered as a case study. Experimental results confirm fair accuracy for the proposed models (3% error on average); based on comparisons of estimated values with those obtained from experimentations.
{"title":"Activity management in battery-powered embedded systems: A case study of ZigBee® WSN","authors":"H. Zarrabi, A. Al-Khalili, Y. Savaria","doi":"10.1109/ICECS.2011.6122377","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122377","url":null,"abstract":"Portable battery-powered embedded systems necessitate sustainable energy-aware computing. For energy-efficient realization of such systems, static and possibly dynamic optimizations need to be applied to both the hardware and software design abstraction layers. In this paper, models for estimating the energy consumption based on application “activity” are proposed. By “activity” we mean the rate at which the computing platform performs a set of predefined application functions; and managing them aims at extending battery life. The proposed models can be used for both static and/or dynamic (on the fly) design/exploration of such systems. In order to validate the models, a generic low duty-cycle ZigBee® Wireless Sensor Network (WSN) application has been considered as a case study. Experimental results confirm fair accuracy for the proposed models (3% error on average); based on comparisons of estimated values with those obtained from experimentations.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122793326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122355
P. Hoseini, A. Khoei, K. Hadidi, Sajjad Moshfe
In this paper a generic genetic algorithm processor (GAP) with high flexibility in parameter tuning is introduced. The proposed processor utilizes pipeline structure to have low processing time. In order to further increase in the speed, genetic population has been duplicated, one for replacement stage of genetic algorithm (GA) and another for selection phase. Additionally, parallel processing method in the selection stage boosts GA processor's speed. The proposed GA has been designed so that it can work in online controlling circumstances. It supports for constraints in search space and changing environments. Also, a large bit number of chromosomes can be achieved by connecting the proposed 32-bit processors to work as one n-bit chip. Ability to work with two fitness function chips, supporting pipelined fitness functions, and capability of distributed processing are other factors that increase the speed in our design.
{"title":"Fast and flexible genetic algorithm processor","authors":"P. Hoseini, A. Khoei, K. Hadidi, Sajjad Moshfe","doi":"10.1109/ICECS.2011.6122355","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122355","url":null,"abstract":"In this paper a generic genetic algorithm processor (GAP) with high flexibility in parameter tuning is introduced. The proposed processor utilizes pipeline structure to have low processing time. In order to further increase in the speed, genetic population has been duplicated, one for replacement stage of genetic algorithm (GA) and another for selection phase. Additionally, parallel processing method in the selection stage boosts GA processor's speed. The proposed GA has been designed so that it can work in online controlling circumstances. It supports for constraints in search space and changing environments. Also, a large bit number of chromosomes can be achieved by connecting the proposed 32-bit processors to work as one n-bit chip. Ability to work with two fitness function chips, supporting pipelined fitness functions, and capability of distributed processing are other factors that increase the speed in our design.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133564044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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