Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122372
C. Killian, C. Tanougast, F. Monteiro, A. Dandache
We present an optimization of reliable Network on Chip (NoC) suitable for dynamic reconfigurable systems based on FPGA. The originality of our approach resides on a strategic placement of routers incorporating elements of dependability in order to detect and correct the errors of the data packets. The solution is a factorization of these reliable routers encompassing routers without any error detection block. This ensures the global reliability of the network, and reduces the area overhead and the latency of the data packets. We present a theoretical study and hardware implementations which validates our reliable approach.
{"title":"Strategic placement of reliable routers for the optimization of dependable dynamic NoC","authors":"C. Killian, C. Tanougast, F. Monteiro, A. Dandache","doi":"10.1109/ICECS.2011.6122372","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122372","url":null,"abstract":"We present an optimization of reliable Network on Chip (NoC) suitable for dynamic reconfigurable systems based on FPGA. The originality of our approach resides on a strategic placement of routers incorporating elements of dependability in order to detect and correct the errors of the data packets. The solution is a factorization of these reliable routers encompassing routers without any error detection block. This ensures the global reliability of the network, and reduces the area overhead and the latency of the data packets. We present a theoretical study and hardware implementations which validates our reliable approach.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117004125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122323
T. Sadeghpour, R. Abd‐Alhameed, N. Ali, I. Elfergani, Y. A. Dama, O. O. Anoh
This paper studies the effect of nonlinear and linear crosstalk in a MIMO (multiple in, multiple out) transceiver. These effects are mainly due to the power amplifier (PA) nonlinear behaviour and mutual coupling of antennas in the MIMO transmitter. The effects of the crosstalk interference on the signal performance are studied based on the measured error vector magnitude (EVM) at the transmitting antennas. The simulation and measurement results show that PA nonlinearity and RF crosstalk need to be considered in the design process.
{"title":"Linear and nonlinear crosstalk in MIMO OFDM transceivers","authors":"T. Sadeghpour, R. Abd‐Alhameed, N. Ali, I. Elfergani, Y. A. Dama, O. O. Anoh","doi":"10.1109/ICECS.2011.6122323","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122323","url":null,"abstract":"This paper studies the effect of nonlinear and linear crosstalk in a MIMO (multiple in, multiple out) transceiver. These effects are mainly due to the power amplifier (PA) nonlinear behaviour and mutual coupling of antennas in the MIMO transmitter. The effects of the crosstalk interference on the signal performance are studied based on the measured error vector magnitude (EVM) at the transmitting antennas. The simulation and measurement results show that PA nonlinearity and RF crosstalk need to be considered in the design process.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"10 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120992960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122256
B. Yousefzadeh, M. Sharifkhani
This paper presents the design and implementation of a low power, low voltage, continuous time delta sigma modulator for audio band in 90 nm CMOS technology. A VCO-based integrator and quantizer are used. Inherent dynamic element matching (DEM) of the quantizer eliminates the need for explicit DEM logic which results in a short excess-delay and power saving. Simulation results show that the modulator achieves 78 dB SNDR and 87 dB SNR in a 20 kHz input bandwidth and dissipates 106 μW from 1 V supply. The power consumption for different parts is discussed.
{"title":"An audio band low voltage CT-ΔΣ modulator with VCO-based quantizer","authors":"B. Yousefzadeh, M. Sharifkhani","doi":"10.1109/ICECS.2011.6122256","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122256","url":null,"abstract":"This paper presents the design and implementation of a low power, low voltage, continuous time delta sigma modulator for audio band in 90 nm CMOS technology. A VCO-based integrator and quantizer are used. Inherent dynamic element matching (DEM) of the quantizer eliminates the need for explicit DEM logic which results in a short excess-delay and power saving. Simulation results show that the modulator achieves 78 dB SNDR and 87 dB SNR in a 20 kHz input bandwidth and dissipates 106 μW from 1 V supply. The power consumption for different parts is discussed.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"R-22 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121010794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122245
Naveen Naraharisetti, Sleiman Bou-Sleiman, M. Ismail
The performance of the quadrature receivers are degraded due to the gain and phase mismatch in I and Q channels. In this paper we develop a mixed-mode technique for self calibration in quadrature receivers. A novel mismatch measurement and estimation scheme using an RF amplitude detector and the IC's digital core is shown. Then, digital and digitally-assisted analog correction is employed to remove phase and gain mismatches in the quadrature channels. The mixed-mode configuration is shown to be of low complexity and overhead. Test cases for QAM-16 demonstrate the effectiveness of the proposed approach in suppressing quadrature mismatch and enhancing image rejection.
{"title":"Mixed-Mode I/Q mismatches compensation in low-IF quadrature receivers","authors":"Naveen Naraharisetti, Sleiman Bou-Sleiman, M. Ismail","doi":"10.1109/ICECS.2011.6122245","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122245","url":null,"abstract":"The performance of the quadrature receivers are degraded due to the gain and phase mismatch in I and Q channels. In this paper we develop a mixed-mode technique for self calibration in quadrature receivers. A novel mismatch measurement and estimation scheme using an RF amplitude detector and the IC's digital core is shown. Then, digital and digitally-assisted analog correction is employed to remove phase and gain mismatches in the quadrature channels. The mixed-mode configuration is shown to be of low complexity and overhead. Test cases for QAM-16 demonstrate the effectiveness of the proposed approach in suppressing quadrature mismatch and enhancing image rejection.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121114316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122200
Willy Aubry, B. Gal, D. Dallet, S. Desfarges, D. Négru
Power consumption is a major issue for handheld devices like mobile phones that decode and display multimedia streams through networks. Their power consumption during video playback directly depends on (1) network communications required to access video streams (2) video decoding process which complexity increases according to video characteristics (codec and video dimension). This paper describes a novel system approach to reduce power consumption through video resizing. This transformation implemented on an external device (i.e. a home gateway that transport video streams from the Internet to the embedded devices) reduces the computation complexity on the handled device up to 70% and reduce its amount of network communications up to 50%.
{"title":"A system aproach for reducing power consumption of multimedia devices with a low QoE impact","authors":"Willy Aubry, B. Gal, D. Dallet, S. Desfarges, D. Négru","doi":"10.1109/ICECS.2011.6122200","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122200","url":null,"abstract":"Power consumption is a major issue for handheld devices like mobile phones that decode and display multimedia streams through networks. Their power consumption during video playback directly depends on (1) network communications required to access video streams (2) video decoding process which complexity increases according to video characteristics (codec and video dimension). This paper describes a novel system approach to reduce power consumption through video resizing. This transformation implemented on an external device (i.e. a home gateway that transport video streams from the Internet to the embedded devices) reduces the computation complexity on the handled device up to 70% and reduce its amount of network communications up to 50%.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131694344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122294
John Hu, Brian Hu, Yanli Fan, M. Ismail
Ultra low quiescent, wide output current range low-dropout regulators (LDO) are in high demand in portable applications to extend battery lives. This paper presents a 500 nA quiescent, 0 to 100 mA load, 3.5–7 V input to 3 V output LDO in a digital 0.35 μm 2P3M CMOS technology. The challenges in designing with nano-ampere of quiescent current are discussed, namely the leakage, the parasitics, and the excessive DC gain. CMOS super source follower voltage buffer and input excessive gain reduction are then proposed. The LDO is internally compensated using Ahuja method with a minimum phase margin of 55° across all load conditions. The maximum transient voltage variation is less than 150 and 75 mV when used with 1 and 10 μF external capacitor. Compared with existing work, this LDO achieves the best transient flgure-of-merit with close to best dynamic current efficiency (maximum-to-quiescent current ratio).
{"title":"A 500 nA quiescent, 100 mA maximum load CMOS low-dropout regulator","authors":"John Hu, Brian Hu, Yanli Fan, M. Ismail","doi":"10.1109/ICECS.2011.6122294","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122294","url":null,"abstract":"Ultra low quiescent, wide output current range low-dropout regulators (LDO) are in high demand in portable applications to extend battery lives. This paper presents a 500 nA quiescent, 0 to 100 mA load, 3.5–7 V input to 3 V output LDO in a digital 0.35 μm 2P3M CMOS technology. The challenges in designing with nano-ampere of quiescent current are discussed, namely the leakage, the parasitics, and the excessive DC gain. CMOS super source follower voltage buffer and input excessive gain reduction are then proposed. The LDO is internally compensated using Ahuja method with a minimum phase margin of 55° across all load conditions. The maximum transient voltage variation is less than 150 and 75 mV when used with 1 and 10 μF external capacitor. Compared with existing work, this LDO achieves the best transient flgure-of-merit with close to best dynamic current efficiency (maximum-to-quiescent current ratio).","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130725254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122356
R. Fareh, M. Saad, A. Brahmi, M. Saad
In this paper, a strategy of control is presented to track a desired trajectory in workspace for a hyper redundant articulated nimble adaptable trunk (ANAT) robot. The pseudo-inverse of the Jacobean is used to ensure the transformation of the desired trajectory from workspace to joint space. The control strategy consists of controlling the last joint by assuming that the remaining joints follow their desired values. Then we go backward for the (n-1)-th joint by following the same strategy, and so on until the first joint. In each step, the feedback linearization approach is used to develop the control law. This algorithm was experimented on a 7 DOF ANAT manipulator and gave effective results and good tracking in the robot's workspace.
{"title":"Real time tracking trajectory in workspace for ANAT robot manipulator using hierarchical control","authors":"R. Fareh, M. Saad, A. Brahmi, M. Saad","doi":"10.1109/ICECS.2011.6122356","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122356","url":null,"abstract":"In this paper, a strategy of control is presented to track a desired trajectory in workspace for a hyper redundant articulated nimble adaptable trunk (ANAT) robot. The pseudo-inverse of the Jacobean is used to ensure the transformation of the desired trajectory from workspace to joint space. The control strategy consists of controlling the last joint by assuming that the remaining joints follow their desired values. Then we go backward for the (n-1)-th joint by following the same strategy, and so on until the first joint. In each step, the feedback linearization approach is used to develop the control law. This algorithm was experimented on a 7 DOF ANAT manipulator and gave effective results and good tracking in the robot's workspace.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116929143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122314
L. Pinna, G. Carlini, L. Seminara, M. Valle
This paper presents the interface electronics design and implementation of a tactile sensing system for humanoid robot applications. The tactile system is designed to cover the human tactile sensing bandwidth ranging from 1Hz to 1kHz and to operate on a wide range of input forces/pressures. Some interface electronics prototypes have been designed and fabricated. The paper reports the experimental results and the validation of the proposed implementation. We report also results of the electro-mechanical response of the tactile sensing system (i.e. tactile sensing array + interface electronics) to external mechanical stimuli. The current implementation is a first step towards dedicated IC integration.
{"title":"Interface electronics for tactile sensing arrays","authors":"L. Pinna, G. Carlini, L. Seminara, M. Valle","doi":"10.1109/ICECS.2011.6122314","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122314","url":null,"abstract":"This paper presents the interface electronics design and implementation of a tactile sensing system for humanoid robot applications. The tactile system is designed to cover the human tactile sensing bandwidth ranging from 1Hz to 1kHz and to operate on a wide range of input forces/pressures. Some interface electronics prototypes have been designed and fabricated. The paper reports the experimental results and the validation of the proposed implementation. We report also results of the electro-mechanical response of the tactile sensing system (i.e. tactile sensing array + interface electronics) to external mechanical stimuli. The current implementation is a first step towards dedicated IC integration.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123340510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122364
David A. Marquez-Gamez, M. Devy
This paper describes the design and testing of a system to enable large scale cooperative navigation of autonomous vehicles moving on a priori unknown routes in changing environments. A large-scale learning-mapping approach and a replay-localization method are combined to achieve cooperative navigation. The mapping approach is based on a proposed hierarchical/hybrid BiCam SLAM approach-global level and local maps-, which will be generalized to be executed on multiple vehicles moving as a convoy. A global 3D map maintains the relationships between a series of local submaps built by the first vehicle of the convoy (leader), defining a path that all other vehicles (followers) must stay on. Only single camera setups are considered. The overall approach is evaluated with real data acquired in an urban environment.
{"title":"Visual navigation of communicating vehicles in unknown and changing environment","authors":"David A. Marquez-Gamez, M. Devy","doi":"10.1109/ICECS.2011.6122364","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122364","url":null,"abstract":"This paper describes the design and testing of a system to enable large scale cooperative navigation of autonomous vehicles moving on a priori unknown routes in changing environments. A large-scale learning-mapping approach and a replay-localization method are combined to achieve cooperative navigation. The mapping approach is based on a proposed hierarchical/hybrid BiCam SLAM approach-global level and local maps-, which will be generalized to be executed on multiple vehicles moving as a convoy. A global 3D map maintains the relationships between a series of local submaps built by the first vehicle of the convoy (leader), defining a path that all other vehicles (followers) must stay on. Only single camera setups are considered. The overall approach is evaluated with real data acquired in an urban environment.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129670092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ICECS.2011.6122312
Habib Ghasemizadeh Tamar, Akbar Ghasemizadeh Tamar, K. Hadidi, A. Khoei, P. Hoseini
In carry-select adders (CSAs), using a single ripple carry adder and a first zero finder (FZF) circuit instead of dual ripple carry adder has an impressive impact on reduction of number of transistors and so power consumption of adder. On the other hand, combination of CSA and carry-lookahead adder (CLA) improves speed of this adder. In this paper a 64-bit static adder with structure of a hybrid CLA/CSA is presented. This adder operates with low power and occupies lower area in comparison to conventional CSA circuit due to using a first zero finder circuit. Besides by three basic changes in the critical path of adder, speed is improved considerably; First of all we used a high speed compact CLA as partial adder in each block, then a block carry generator (BCG) circuit is used for faster carry propagation and finally we replaced multiplexer gate with a XNOR gate. This circuit is implemented in TSMC 0.18μm CMOS technology at 1.8V power supply. Critical path delay of this adder decreased to 592ps, equivalent to 7.6 FO4 (fanout-of-4) inverter delays.
{"title":"High speed area reduced 64-bit static hybrid carry-lookahead/carry-select adder","authors":"Habib Ghasemizadeh Tamar, Akbar Ghasemizadeh Tamar, K. Hadidi, A. Khoei, P. Hoseini","doi":"10.1109/ICECS.2011.6122312","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122312","url":null,"abstract":"In carry-select adders (CSAs), using a single ripple carry adder and a first zero finder (FZF) circuit instead of dual ripple carry adder has an impressive impact on reduction of number of transistors and so power consumption of adder. On the other hand, combination of CSA and carry-lookahead adder (CLA) improves speed of this adder. In this paper a 64-bit static adder with structure of a hybrid CLA/CSA is presented. This adder operates with low power and occupies lower area in comparison to conventional CSA circuit due to using a first zero finder circuit. Besides by three basic changes in the critical path of adder, speed is improved considerably; First of all we used a high speed compact CLA as partial adder in each block, then a block carry generator (BCG) circuit is used for faster carry propagation and finally we replaced multiplexer gate with a XNOR gate. This circuit is implemented in TSMC 0.18μm CMOS technology at 1.8V power supply. Critical path delay of this adder decreased to 592ps, equivalent to 7.6 FO4 (fanout-of-4) inverter delays.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127727302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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