Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334614
Y. Dai, Mei Zhen Ng, P. Anantha, C. Gan, C. S. Tan
A novel copper paste with copper micro particles mixed with copper nanoparticles is proposed in this study. The mixed ratio between the two kinds of particles is simulated based on the Monte Carlo method. The copper micro particles are assumed to have a Face-Centered-Cubic (FCC) structure and the nanoparticles are filled randomly in the interstices between micro particles. The nanoparticles arrangement with maximum occupancy in the interstitial space is calculated, which enable its weight percentage estimation. Based on the simulation results, experiments are carried out to examine the micro paste, nano paste and mixed paste quality by optical microscope, contact angle measurements and thermogravimetric analysis (TGA). The experimental results reveal that the mixed paste is denser in structure and has a lower transition temperature.
{"title":"Copper micro and nano particles mixture for 3D interconnections application","authors":"Y. Dai, Mei Zhen Ng, P. Anantha, C. Gan, C. S. Tan","doi":"10.1109/3DIC.2015.7334614","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334614","url":null,"abstract":"A novel copper paste with copper micro particles mixed with copper nanoparticles is proposed in this study. The mixed ratio between the two kinds of particles is simulated based on the Monte Carlo method. The copper micro particles are assumed to have a Face-Centered-Cubic (FCC) structure and the nanoparticles are filled randomly in the interstices between micro particles. The nanoparticles arrangement with maximum occupancy in the interstitial space is calculated, which enable its weight percentage estimation. Based on the simulation results, experiments are carried out to examine the micro paste, nano paste and mixed paste quality by optical microscope, contact angle measurements and thermogravimetric analysis (TGA). The experimental results reveal that the mixed paste is denser in structure and has a lower transition temperature.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130407873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334466
A. Heinig, Muhammad Waqas Chaudhary, P. Schneider, P. Ramm, J. Weber
In this presentation we will show different manufacturing approaches for TSVs which results in different shapes and dimensions. For example, geometries for tungsten filled very small TSVs (smaller than 5um) into very thin 2D chips (under 50um thickness) are shown. Also different assembly technologies for the mounting of the different chips to 2.5D and real 3D systems are explained. The usage of such 2.5 or 3D integrated systems in real world examples for high bandwidth processor memory communications are demonstrated.
{"title":"Current and future 3D activities at Fraunhofer","authors":"A. Heinig, Muhammad Waqas Chaudhary, P. Schneider, P. Ramm, J. Weber","doi":"10.1109/3DIC.2015.7334466","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334466","url":null,"abstract":"In this presentation we will show different manufacturing approaches for TSVs which results in different shapes and dimensions. For example, geometries for tungsten filled very small TSVs (smaller than 5um) into very thin 2D chips (under 50um thickness) are shown. Also different assembly technologies for the mounting of the different chips to 2.5D and real 3D systems are explained. The usage of such 2.5 or 3D integrated systems in real world examples for high bandwidth processor memory communications are demonstrated.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131120802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334598
J. Tada, Ryusuke Egawa, Hiroaki Kobayashi
In the design of 3-D stacked floating-point units, a partitioning method affects the performance and the power consumption. To realize a high-performance and low-power 3-D stacked floating point divider, this paper proposes a circuit partitioning method for the Goldschmidt divider. The proposed partitioning method equalizes the sizes of silicon layers and reduces the number of vertical interconnects. Experimental results show the 3-D stacked Goldschmidt divider which is designed based on the proposed partitioning method achieves an 8.1% critical path delay reduction and a 6.8% average power reduction compared to the 2-D implementation.
{"title":"Design of a 3-D stacked floating-point Goldschmidt divider","authors":"J. Tada, Ryusuke Egawa, Hiroaki Kobayashi","doi":"10.1109/3DIC.2015.7334598","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334598","url":null,"abstract":"In the design of 3-D stacked floating-point units, a partitioning method affects the performance and the power consumption. To realize a high-performance and low-power 3-D stacked floating point divider, this paper proposes a circuit partitioning method for the Goldschmidt divider. The proposed partitioning method equalizes the sizes of silicon layers and reduces the number of vertical interconnects. Experimental results show the 3-D stacked Goldschmidt divider which is designed based on the proposed partitioning method achieves an 8.1% critical path delay reduction and a 6.8% average power reduction compared to the 2-D implementation.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133300494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334606
R. R. Reddy, Sugandh Tanna, S. Singh, Om Krishan Singh
Three Dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Major efforts are currently underway throughout the IC industry to develop the capability to integrate device chips by stacking them vertically and using through-silicon vias (TSVs). In 3D IC using TSV, TSV noise coupling is one of the most significant consideration for circuit design. In this paper for the noise isolation between TSV and silicon substrate, p+ guard ring structure was proposed around signal TSV and examine with different doping concentration levels of the guard ring. In addition to that noise coupling from TSV to silicon substrate was analyzed with different liner (silicon dioxide, CVD diamond, Benzocyclobutene (BCB)) materials for the above structure. After investigating all results, TSV with BCB as liner material surrounded by p+ guard ring gives the better noise reduction from TSV to substrate by considering all constraints.
{"title":"TSV noise coupling in 3D IC using guard ring","authors":"R. R. Reddy, Sugandh Tanna, S. Singh, Om Krishan Singh","doi":"10.1109/3DIC.2015.7334606","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334606","url":null,"abstract":"Three Dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Major efforts are currently underway throughout the IC industry to develop the capability to integrate device chips by stacking them vertically and using through-silicon vias (TSVs). In 3D IC using TSV, TSV noise coupling is one of the most significant consideration for circuit design. In this paper for the noise isolation between TSV and silicon substrate, p+ guard ring structure was proposed around signal TSV and examine with different doping concentration levels of the guard ring. In addition to that noise coupling from TSV to silicon substrate was analyzed with different liner (silicon dioxide, CVD diamond, Benzocyclobutene (BCB)) materials for the above structure. After investigating all results, TSV with BCB as liner material surrounded by p+ guard ring gives the better noise reduction from TSV to substrate by considering all constraints.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128543761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334601
S. Melamed, K. Kikuchi, M. Aoyagi
In three-dimensional integrated circuits (3DICs) aggressive wafer-thinning can lead to large thermal gradients, including spikes in individual device temperatures. In this paper we have simulated the impact of highly directionalized metallization on the transistor temperatures of a two-tier bump-bonded 3D system for various thicknesses of the top tier. A 90 μm × 90 μm area of active devices in the top tier dissipates power at 250 W/cm2, creating a hotspot. The maximum difference between temperatures in-line and out-of-line with the directional wiring is 4.5% for the 20 μm thick case and 17.3% for the 1 μm thick case.
{"title":"Investigation of effects of metalization on heat spreading in bump-bonded 3D systems","authors":"S. Melamed, K. Kikuchi, M. Aoyagi","doi":"10.1109/3DIC.2015.7334601","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334601","url":null,"abstract":"In three-dimensional integrated circuits (3DICs) aggressive wafer-thinning can lead to large thermal gradients, including spikes in individual device temperatures. In this paper we have simulated the impact of highly directionalized metallization on the transistor temperatures of a two-tier bump-bonded 3D system for various thicknesses of the top tier. A 90 μm × 90 μm area of active devices in the top tier dissipates power at 250 W/cm2, creating a hotspot. The maximum difference between temperatures in-line and out-of-line with the directional wiring is 4.5% for the 20 μm thick case and 17.3% for the 1 μm thick case.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133469381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334557
S. Tanikawa, H. Kino, T. Fukushima, M. Koyanagi, Tetsu Tanaka
Three-dimensional integrated circuit (3D IC) is one of the promising ways to enhance IC performance. Each IC chip is mechanically connected by organic adhesive and metal microbumps. Coefficient of thermal expansion (CTE) mismatch between materials causes local bending stress in IC chips, leading to negative effects in IC performance. In this study, we have fabricated a test structure with DRAM cell array having planar MOS capacitors. Using the test structure, we measured both DRAM chip bending profiles and retention time modulations of DRAM cell array. Consequently, we have successfully demonstrated that the local bending stress in IC chips can be two-dimensionally evaluated using the DRAM cell array with planar MOS capacitances. This evaluation methods leads to realization of 3D IC with high reliability.
{"title":"Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors","authors":"S. Tanikawa, H. Kino, T. Fukushima, M. Koyanagi, Tetsu Tanaka","doi":"10.1109/3DIC.2015.7334557","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334557","url":null,"abstract":"Three-dimensional integrated circuit (3D IC) is one of the promising ways to enhance IC performance. Each IC chip is mechanically connected by organic adhesive and metal microbumps. Coefficient of thermal expansion (CTE) mismatch between materials causes local bending stress in IC chips, leading to negative effects in IC performance. In this study, we have fabricated a test structure with DRAM cell array having planar MOS capacitors. Using the test structure, we measured both DRAM chip bending profiles and retention time modulations of DRAM cell array. Consequently, we have successfully demonstrated that the local bending stress in IC chips can be two-dimensionally evaluated using the DRAM cell array with planar MOS capacitances. This evaluation methods leads to realization of 3D IC with high reliability.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127369243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334468
P. Vivet, C. Bernard, F. Clermidy, D. Dutoit, E. Guthmuller, I. Panades, G. Pillonnet, Y. Thonnart, A. Garnier, D. Lattard, A. Jouve, F. Bana, T. Mourier, S. Chéramy
3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, μ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description.
{"title":"3D advanced integration technology for heterogeneous systems","authors":"P. Vivet, C. Bernard, F. Clermidy, D. Dutoit, E. Guthmuller, I. Panades, G. Pillonnet, Y. Thonnart, A. Garnier, D. Lattard, A. Jouve, F. Bana, T. Mourier, S. Chéramy","doi":"10.1109/3DIC.2015.7334468","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334468","url":null,"abstract":"3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, μ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121582891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334555
Hyunsuk Lee, Kyungjun Cho, Heegon Kim, Sumin Choi, Jaemin Lim, Joungho Kim
Recently, IT trends such as big data, cloud computing, internet of things (IoT), 3D visualization, network, and so on demand terabyte/s bandwidth computer performance in a graphics card. In order to meet these performance, terabyte/s bandwidth graphics module using 2.5D-IC with high bandwidth memory (HBM) technology has been emerged. Due to the difference in scale of interconnect pitch between GPU or HBM and package substrate, the HBM interposer is certainly required for terabyte/s bandwidth graphics module. In this paper, the electrical performance of the HBM interposer channel in consideration of the manufacturing capabilities is analyzed by simulation both the frequency- and time-domain. Furthermore, although the silicon substrate is most widely employed for the HBM interposer fabrication, the organic and glass substrate are also proposed to replace the high cost and high loss silicon substrate. Therefore, comparison and analysis of the electrical performance of the HBM interposer channel using silicon, organic, and glass substrate are conducted.
{"title":"Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module","authors":"Hyunsuk Lee, Kyungjun Cho, Heegon Kim, Sumin Choi, Jaemin Lim, Joungho Kim","doi":"10.1109/3DIC.2015.7334555","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334555","url":null,"abstract":"Recently, IT trends such as big data, cloud computing, internet of things (IoT), 3D visualization, network, and so on demand terabyte/s bandwidth computer performance in a graphics card. In order to meet these performance, terabyte/s bandwidth graphics module using 2.5D-IC with high bandwidth memory (HBM) technology has been emerged. Due to the difference in scale of interconnect pitch between GPU or HBM and package substrate, the HBM interposer is certainly required for terabyte/s bandwidth graphics module. In this paper, the electrical performance of the HBM interposer channel in consideration of the manufacturing capabilities is analyzed by simulation both the frequency- and time-domain. Furthermore, although the silicon substrate is most widely employed for the HBM interposer fabrication, the organic and glass substrate are also proposed to replace the high cost and high loss silicon substrate. Therefore, comparison and analysis of the electrical performance of the HBM interposer channel using silicon, organic, and glass substrate are conducted.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131606439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334610
Jiatong Liu, Ken Suzuki, H. Miura
In this study, the change in residual stress in electroplated copper thin-film interconnections during thermal cycling was investigated from a view point of their initial crystallinity. The crystallinity is mainly dominated by the seed layer material for electroplating because of the lattice mismatch between the seed layer material and copper. By applying a ruthenium seed layer, which is effective for decreasing the lattice mismatch, the crystallinity of electroplated copper thin films was improved and their stability was very high during annealing up to 200°C. In addition, the amplitude of residual stress in the interconnection formed on the ruthenium seed layer decreased drastically during thermal cycling. Therefore, it is very important to improve the crystallinity of the interconnection for assuring the high thermal stability of 3D modules.
{"title":"Variation of thermal stress in TSV structures caused by crystallinity of electroplated copper interconnections","authors":"Jiatong Liu, Ken Suzuki, H. Miura","doi":"10.1109/3DIC.2015.7334610","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334610","url":null,"abstract":"In this study, the change in residual stress in electroplated copper thin-film interconnections during thermal cycling was investigated from a view point of their initial crystallinity. The crystallinity is mainly dominated by the seed layer material for electroplating because of the lattice mismatch between the seed layer material and copper. By applying a ruthenium seed layer, which is effective for decreasing the lattice mismatch, the crystallinity of electroplated copper thin films was improved and their stability was very high during annealing up to 200°C. In addition, the amplitude of residual stress in the interconnection formed on the ruthenium seed layer decreased drastically during thermal cycling. Therefore, it is very important to improve the crystallinity of the interconnection for assuring the high thermal stability of 3D modules.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125437821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334588
Daisuke Suga, M. Hashizume, H. Yotsuyanagi, Shyue-Kung Lu
In this paper, an electrical test method and a power supply circuit are proposed for open defects at interconnects between dies in a 3D IC. The test method is based on volume of charge injected from the power supply circuit. Feasibility of the electrical tests is examined by Spice simulation. The simulation results show that a hard open defect, capacitive ones and resistive ones whose resistance is greater than or equal to 100Ω may be detected at a test speed of 0.9MHz.
{"title":"Electrical interconnect test method of 3D ICs by injected charge volume","authors":"Daisuke Suga, M. Hashizume, H. Yotsuyanagi, Shyue-Kung Lu","doi":"10.1109/3DIC.2015.7334588","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334588","url":null,"abstract":"In this paper, an electrical test method and a power supply circuit are proposed for open defects at interconnects between dies in a 3D IC. The test method is based on volume of charge injected from the power supply circuit. Feasibility of the electrical tests is examined by Spice simulation. The simulation results show that a hard open defect, capacitive ones and resistive ones whose resistance is greater than or equal to 100Ω may be detected at a test speed of 0.9MHz.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128103674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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