Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334582
A. Panigrahi, Satish Bonam, Tamal Ghosh, S. Vanjari, S. Singh
In this paper, we report the efficiency of Cu surface passivation by optimally chosen ultra-thin layer of Ti resulting low temperature, low pressure CMOS compatible Wafer-on-Wafer (WoW) Cu-Cu thermo-compression bonding. Ultra-thin Ti layer is regarded as one of the promising passivation layer as the presence of the same prevents oxidation of copper over an extended period of time. This allows various semiconductor industries dealing with heterogeneous technologies which are geographically located at different places to sync up and carry out 3D integration through WoW bonding. The optimum thickness for achieving low temperature and low pressure bonding is found to be 3 nm. In this endeavor, efficiency of ultra-thin Ti passivation layer in preventing oxidation of Cu over a long period was analyzed using various characterization techniques. These include contact angle measurements and X-Ray Photoelectron Spectroscopy (XPS). The samples got successfully bonded even after their exposure to non-vacuum, ambient conditions and quality of the bonding was characterized using Cross-sectional Field Emission-Scanning Electron Microscopy (FE-SEM), Surface Acoustic Microscopy (SAM) and bond strength analysis by tensile Pull test. The results are similar to the passivated samples bonded just after the deposition indicating that Ti is an ideal candidate for passivating Cu over extended period of time.
{"title":"Long term efficacy of ultra-thin Ti passivation layer for achieving low temperature, low pressure Cu-Cu Wafer-on-Wafer bonding","authors":"A. Panigrahi, Satish Bonam, Tamal Ghosh, S. Vanjari, S. Singh","doi":"10.1109/3DIC.2015.7334582","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334582","url":null,"abstract":"In this paper, we report the efficiency of Cu surface passivation by optimally chosen ultra-thin layer of Ti resulting low temperature, low pressure CMOS compatible Wafer-on-Wafer (WoW) Cu-Cu thermo-compression bonding. Ultra-thin Ti layer is regarded as one of the promising passivation layer as the presence of the same prevents oxidation of copper over an extended period of time. This allows various semiconductor industries dealing with heterogeneous technologies which are geographically located at different places to sync up and carry out 3D integration through WoW bonding. The optimum thickness for achieving low temperature and low pressure bonding is found to be 3 nm. In this endeavor, efficiency of ultra-thin Ti passivation layer in preventing oxidation of Cu over a long period was analyzed using various characterization techniques. These include contact angle measurements and X-Ray Photoelectron Spectroscopy (XPS). The samples got successfully bonded even after their exposure to non-vacuum, ambient conditions and quality of the bonding was characterized using Cross-sectional Field Emission-Scanning Electron Microscopy (FE-SEM), Surface Acoustic Microscopy (SAM) and bond strength analysis by tensile Pull test. The results are similar to the passivated samples bonded just after the deposition indicating that Ti is an ideal candidate for passivating Cu over extended period of time.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131532326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334472
H. Sarhan, S. Thuries, O. Billoint, F. Deprat, Alexandre Ayres De Sousa, P. Batude, C. Fenouillet-Béranger, F. Clermidy
3D VLSI technology based on CoolCube™ process offers ultra-high density of integration with up to 108 3D Vias (3D-V) per mm2 offering gate level 3D integration capability. For process stability and wide range of temperature compliancy, Intermediate Back End of Line (IBEOL) is targeted to be made with Tungsten lines in a SiO2 (k=3.9) dielectric, increasing equivalent resistivity by 6 and capacitance by 1.6 compared to standard Back End of Line (BEOL) (copper lines in low k dielectrics). In this study we propose to study impact in Performance, Power and Area (PPA) using W/SiO2 compared to Cu/low-k IBEOL. Results show area gain up to 60.9% and performance gain up to 21.7% for 3D cases comparing to 2D using 28 nm FDSOI technology. Using W/SiO2 shows limited impact on performance with maximal 1.93% degradation comparing to Cu/low-k IBEOL.
{"title":"Intermediate BEOL process influence on power and performance for 3DVLSI","authors":"H. Sarhan, S. Thuries, O. Billoint, F. Deprat, Alexandre Ayres De Sousa, P. Batude, C. Fenouillet-Béranger, F. Clermidy","doi":"10.1109/3DIC.2015.7334472","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334472","url":null,"abstract":"3D VLSI technology based on CoolCube™ process offers ultra-high density of integration with up to 108 3D Vias (3D-V) per mm2 offering gate level 3D integration capability. For process stability and wide range of temperature compliancy, Intermediate Back End of Line (IBEOL) is targeted to be made with Tungsten lines in a SiO2 (k=3.9) dielectric, increasing equivalent resistivity by 6 and capacitance by 1.6 compared to standard Back End of Line (BEOL) (copper lines in low k dielectrics). In this study we propose to study impact in Performance, Power and Area (PPA) using W/SiO2 compared to Cu/low-k IBEOL. Results show area gain up to 60.9% and performance gain up to 21.7% for 3D cases comparing to 2D using 28 nm FDSOI technology. Using W/SiO2 shows limited impact on performance with maximal 1.93% degradation comparing to Cu/low-k IBEOL.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128543973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334575
Isao Sugaya, Hajime Mitsuishi, Hidehiro Maeda, K. Okamoto
A new precision wafer-to-wafer (W2W) bonding system for three-dimensional integrated circuits (3DICs) fabrication including a new precision alignment methodology and a unique thermocompression bonding procedure is proposed. Experimental results show that the alignment capability is 100 nm or better, and permanent bonding accuracy of 260 nm (|mean| + 3σ) in 300 mm Cu wafer bonding. An analysis of overlay error components is useful for identifying the causes of the error and improving the tool conditions. These capabilities are key enablers for the future of cost-effective 3DIC manufacturing.
{"title":"New precision wafer bonding technologies for 3DIC","authors":"Isao Sugaya, Hajime Mitsuishi, Hidehiro Maeda, K. Okamoto","doi":"10.1109/3DIC.2015.7334575","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334575","url":null,"abstract":"A new precision wafer-to-wafer (W2W) bonding system for three-dimensional integrated circuits (3DICs) fabrication including a new precision alignment methodology and a unique thermocompression bonding procedure is proposed. Experimental results show that the alignment capability is 100 nm or better, and permanent bonding accuracy of 260 nm (|mean| + 3σ) in 300 mm Cu wafer bonding. An analysis of overlay error components is useful for identifying the causes of the error and improving the tool conditions. These capabilities are key enablers for the future of cost-effective 3DIC manufacturing.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128763458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334580
T. Murayama, Y. Morikawa
TSV (Thru Silicon Via) application for 2.5D silicon interposers and 3D stacked devices is expected to realize a next-generation semiconductor device with high packaging density, power saving, and high-speed signal transmission, etc. Recently, discussions on long-term reliability of TSV has been triggered, the establishment of TSV integration technologies contribute to reliability is strongly requested to enable TSV packaging promote mass production. Compared with Bosch etching method, relatively smooth sidewall could be obtained in TSV fabrication by using scallop-free etching method. In scallop-free TSV, there is possibility that TSV reliability can progress due to the thermal-mechanical stress-relief of heterogeneous stacked layer in TSVs, and the continuous PVD barrier metal layer relatively easily obtained on the smooth sidewall of TSV. However, TSV reliability is not decided by only etching method. For example, the wiring-delay by the dielectric constants of the liner film is an important problem which is referred to both case of scallop existence and scallop-free. SiO2 film is adopted generally in TSVs, but is fatal to the high frequency device of the GHz band. Therefore, kind of polymer film is introduced as a low dielectric constant for a high frequency band. And also, the film stress is quite small. This suggests the anti-stress high tolerance capability on the thin wafer. Not depended on scallop-free etching method only, the use of polymer film will contribute to more reliable TSV integration from the perspective of liner material.
{"title":"TSV etching and VDP process integration for high reliability","authors":"T. Murayama, Y. Morikawa","doi":"10.1109/3DIC.2015.7334580","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334580","url":null,"abstract":"TSV (Thru Silicon Via) application for 2.5D silicon interposers and 3D stacked devices is expected to realize a next-generation semiconductor device with high packaging density, power saving, and high-speed signal transmission, etc. Recently, discussions on long-term reliability of TSV has been triggered, the establishment of TSV integration technologies contribute to reliability is strongly requested to enable TSV packaging promote mass production. Compared with Bosch etching method, relatively smooth sidewall could be obtained in TSV fabrication by using scallop-free etching method. In scallop-free TSV, there is possibility that TSV reliability can progress due to the thermal-mechanical stress-relief of heterogeneous stacked layer in TSVs, and the continuous PVD barrier metal layer relatively easily obtained on the smooth sidewall of TSV. However, TSV reliability is not decided by only etching method. For example, the wiring-delay by the dielectric constants of the liner film is an important problem which is referred to both case of scallop existence and scallop-free. SiO2 film is adopted generally in TSVs, but is fatal to the high frequency device of the GHz band. Therefore, kind of polymer film is introduced as a low dielectric constant for a high frequency band. And also, the film stress is quite small. This suggests the anti-stress high tolerance capability on the thin wafer. Not depended on scallop-free etching method only, the use of polymer film will contribute to more reliable TSV integration from the perspective of liner material.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124280106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334465
Wei-Chung Lo
The document was not made available for publication as part of the conference proceedings.
该文件没有作为会议记录的一部分提供出版。
{"title":"3D research activities in ITRI","authors":"Wei-Chung Lo","doi":"10.1109/3DIC.2015.7334465","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334465","url":null,"abstract":"The document was not made available for publication as part of the conference proceedings.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126339103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334578
T. Fukushima, Taku Suzuki, H. Hashiguchi, C. Nagai, J. Bea, H. Hashimoto, M. Murugesan, Kang-wook Lee, Tetsu Tanaka, K. Asami, Yasuhiro Kitamura, M. Koyanagi
Two types of high-throughput and high-precision multichip-to-wafer 3D stacking approaches are demonstrated: one is non-transfer stacking and the other one is transfer stacking. Both the stacking approaches employ a self-assembly technologies using liquid surface tension. In the former stacking scheme, large number of chips having 20-μm-square Cu/SnAg microbumps are directly self-assembled face-down on an interposer wafer, like flip-chip bonding. On the other hand, in the latter stacking scheme, the many chips having the microbumps are self-assembled face-up on a carrier wafer with bipolar electrodes for electrostatic chucking. Then, the latter chips are transferred from the carrier to another interposer in wafer-level processing. The alignment accuracies are evaluated and compared between the two stacking approaches. The resulting daisy chains show good electrical properties comparable to conventional flip-chip bonding.
{"title":"Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding","authors":"T. Fukushima, Taku Suzuki, H. Hashiguchi, C. Nagai, J. Bea, H. Hashimoto, M. Murugesan, Kang-wook Lee, Tetsu Tanaka, K. Asami, Yasuhiro Kitamura, M. Koyanagi","doi":"10.1109/3DIC.2015.7334578","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334578","url":null,"abstract":"Two types of high-throughput and high-precision multichip-to-wafer 3D stacking approaches are demonstrated: one is non-transfer stacking and the other one is transfer stacking. Both the stacking approaches employ a self-assembly technologies using liquid surface tension. In the former stacking scheme, large number of chips having 20-μm-square Cu/SnAg microbumps are directly self-assembled face-down on an interposer wafer, like flip-chip bonding. On the other hand, in the latter stacking scheme, the many chips having the microbumps are self-assembled face-up on a carrier wafer with bipolar electrodes for electrostatic chucking. Then, the latter chips are transferred from the carrier to another interposer in wafer-level processing. The alignment accuracies are evaluated and compared between the two stacking approaches. The resulting daisy chains show good electrical properties comparable to conventional flip-chip bonding.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126727032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-20DOI: 10.1109/3DIC.2015.7334570
R. Takigawa, K. Nitta, A. Ikeda, M. Kumazawa, Toshiharu Hirai, M. Komatsu, T. Asano
As an alternative to conventional electroplating, we propose TSV filling using the electrophoresis of metal nanoparticles. Colloidal solution of Ag nanoparticles having a high zeta potential has been designed and made up. Via holes for the test experiment were prepared in a photoresist layer on a Au film which acts as anode. Ag nanoparticles were completely filled into the cavities of depth of 30 μm and diameter of 10 μm within one minute. After annealing at 250°C, the electric conductivity was 1.57 × 10-5 [Ω·cm]. These results demonstrate the potentials of the application of electrophoresis of metal nanoparticles to high speed TSV filling.
{"title":"High-speed via hole filling using electrophoresis of Ag nanoparticles","authors":"R. Takigawa, K. Nitta, A. Ikeda, M. Kumazawa, Toshiharu Hirai, M. Komatsu, T. Asano","doi":"10.1109/3DIC.2015.7334570","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334570","url":null,"abstract":"As an alternative to conventional electroplating, we propose TSV filling using the electrophoresis of metal nanoparticles. Colloidal solution of Ag nanoparticles having a high zeta potential has been designed and made up. Via holes for the test experiment were prepared in a photoresist layer on a Au film which acts as anode. Ag nanoparticles were completely filled into the cavities of depth of 30 μm and diameter of 10 μm within one minute. After annealing at 250°C, the electric conductivity was 1.57 × 10-5 [Ω·cm]. These results demonstrate the potentials of the application of electrophoresis of metal nanoparticles to high speed TSV filling.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114588015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/3DIC.2015.7334595
Sumin Choi, Heegon Kim, D. Jung, Jonghoon J. Kim, Jaemin Lim, Hyunsuk Lee, Kyungjun Cho, Joungho Kim, Hyungsoo Kim, Yong-Ju Kim, Yunsaing Kim
In this paper, crosstalk-included eye-diagram of high-speed interposer channels are estimated and investigated. To analyze the crosstalk effect of various interposer channels, silicon, organic, and glass substrates are compared under the same physical structure and dimensions. Moreover, crosstalk-included eye-diagrams are estimated in short time with high accuracy using 8 worst input cases. The estimated crosstalk-included eye-diagrams are analyzed at data rate of 1 and 2 Gbps.
{"title":"Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC","authors":"Sumin Choi, Heegon Kim, D. Jung, Jonghoon J. Kim, Jaemin Lim, Hyunsuk Lee, Kyungjun Cho, Joungho Kim, Hyungsoo Kim, Yong-Ju Kim, Yunsaing Kim","doi":"10.1109/3DIC.2015.7334595","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334595","url":null,"abstract":"In this paper, crosstalk-included eye-diagram of high-speed interposer channels are estimated and investigated. To analyze the crosstalk effect of various interposer channels, silicon, organic, and glass substrates are compared under the same physical structure and dimensions. Moreover, crosstalk-included eye-diagrams are estimated in short time with high accuracy using 8 worst input cases. The estimated crosstalk-included eye-diagrams are analyzed at data rate of 1 and 2 Gbps.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127494212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/3DIC.2015.7334585
Ryouya Shirahama, S. Duangchan, Yusuke Koishikawa, A. Baba
We investigate the influential factor in low-temperature bonding of silicon dioxide. Two surfaces were formed by thermal oxidation and plasma-enhanced chemical vapor deposition with 50 nm thick. Surface characterization by atomic force microscopy. Wafer cleaning by piranha, surface-activated by oxygen plasma, pre-bonding at room temperature and post-bonding anneal by 100-400 degrees Celsius in 0.03 Pascal for 1 hour. Bonding area was tested by dicing machine that PECVD silicon dioxide showed weak bonding, whereas oxide from thermal oxidation showed good results between 200-400 degrees Celsius. Thus surface roughness and annealing temperature are an influential factor of low-temperature bonding of silicon dioxide.
{"title":"Influential factors in low-temperature direct bonding of silicon dioxide","authors":"Ryouya Shirahama, S. Duangchan, Yusuke Koishikawa, A. Baba","doi":"10.1109/3DIC.2015.7334585","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334585","url":null,"abstract":"We investigate the influential factor in low-temperature bonding of silicon dioxide. Two surfaces were formed by thermal oxidation and plasma-enhanced chemical vapor deposition with 50 nm thick. Surface characterization by atomic force microscopy. Wafer cleaning by piranha, surface-activated by oxygen plasma, pre-bonding at room temperature and post-bonding anneal by 100-400 degrees Celsius in 0.03 Pascal for 1 hour. Bonding area was tested by dicing machine that PECVD silicon dioxide showed weak bonding, whereas oxide from thermal oxidation showed good results between 200-400 degrees Celsius. Thus surface roughness and annealing temperature are an influential factor of low-temperature bonding of silicon dioxide.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127847420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/3DIC.2015.7334587
Y. Araga, K. Kikuchi, M. Aoyagi
Three-dimensional ICs are expected to bring about a new generation of integration by allowing for a smaller footprint, faster operation, and lower energy consumption. Manufacturing defects in through-silicon via (TSV) and disconnection defects among tiers are concerns in this new technology. To prevent yield loss from these defects, confirming known-good-die (KGD) and known-good-stacks (KGS) by test is a critical issue. In this paper, embedded circuitry is proposed to guarantee KGD and KGS by measuring noise on the guard-ring (GR) around TSVs. The proposed test circuit consists of simple circuitry and potentially can test multiple TSVs with just a single channel of test circuitry. A simple analytical model is created to discuss test capability of the circuitry with model of TSV array, such as would be encountered in Wide-I/O. After testing, GR is grounded for signal integrity of TSV data bus. Hence, it doesn't spoil wiring resources. Additionally, the test structure does not have any additional load to TSVs because of absence of wiring between the test structure and TSVs.
{"title":"Guard-ring monitoring system for inspecting defects in TSV-based data buses","authors":"Y. Araga, K. Kikuchi, M. Aoyagi","doi":"10.1109/3DIC.2015.7334587","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334587","url":null,"abstract":"Three-dimensional ICs are expected to bring about a new generation of integration by allowing for a smaller footprint, faster operation, and lower energy consumption. Manufacturing defects in through-silicon via (TSV) and disconnection defects among tiers are concerns in this new technology. To prevent yield loss from these defects, confirming known-good-die (KGD) and known-good-stacks (KGS) by test is a critical issue. In this paper, embedded circuitry is proposed to guarantee KGD and KGS by measuring noise on the guard-ring (GR) around TSVs. The proposed test circuit consists of simple circuitry and potentially can test multiple TSVs with just a single channel of test circuitry. A simple analytical model is created to discuss test capability of the circuitry with model of TSV array, such as would be encountered in Wide-I/O. After testing, GR is grounded for signal integrity of TSV data bus. Hence, it doesn't spoil wiring resources. Additionally, the test structure does not have any additional load to TSVs because of absence of wiring between the test structure and TSVs.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125503969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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